CN118693160B - Silicon carbide MOSFET device with gate oxide protection structure and preparation method - Google Patents

Abstract

The invention discloses a silicon carbide MOSFET device with a gate oxide protection structure and a preparation method thereof, wherein the device comprises the following components: drain and source metals, an N+ type silicon carbide substrate, an N-type first silicon carbide epitaxial layer, an N-type second silicon carbide epitaxial layer, an interlayer insulating medium, P-type and N-type first doping regions, an N+ type first source region, a P-type body region and an N+ type second source region; the source electrode groove penetrates through the N-type second silicon carbide epitaxial layer to the N-type first silicon carbide epitaxial layer, the outer side is a P+ type source region, and source electrode metals are arranged in the source electrode groove and on the interlayer insulating medium; a gate oxide layer is arranged in the gate groove, polysilicon is also used as a gate, and the gate oxide layer is contacted with the N+ type second source region and the N+ type first source region; the N+ type first source region and the P+ type source region are overlapped and contact with the source metal; the upper surfaces of the P-type body region and the N+ type second source region are contacted with source metal, and one side of the P-type body region is contacted with the P+ type source region. The invention can solve the problem of overhigh electric field of the gate oxide layer.

Description

Silicon carbide MOSFET device with gate oxide protection structure and preparation method

Technical Field

The present invention belongs to the field of semiconductor technology, and in particular relates to a silicon carbide MOSFET device with a gate oxide protection structure and a preparation method thereof.

Background Art

Silicon carbide (SiC) materials have begun to attract attention and research due to their superior physical properties. The higher thermal conductivity of silicon carbide materials determines its high current density characteristics, and the higher bandgap width determines the high breakdown field strength and high operating temperature characteristics of SiC devices.

Compared with planar VDMOS devices, the conductive channel of trench silicon carbide MOSFET is located in the vertical direction, which eliminates the parasitic JFET resistance of planar VDMOS, reduces the cell size, and increases the cell density, thereby significantly increasing the current density and greatly reducing the on-resistance of the device.

In view of the advantages of trench silicon carbide MOSFET, more and more research institutions have increased their research and development efforts on trench silicon carbide MOSFET. However, the trench silicon carbide MOSFET prepared by the existing preparation scheme does not provide sufficient electric field protection for the gate oxide layer, especially the gate oxide layer at the corner is easily broken down by the electric field. In order to reduce the peak electric field strength of the gate oxide layer, introducing a P+ shielding region at the bottom of the trench has been proven to be a very effective means. Usually, in order to give full play to the shielding effect of the P+ shielding region and avoid the dynamic degradation problem that may occur when the P+ shielding region is floating, the injection region needs to be connected to the source ground potential. However, when the device is turned on, the P+ shielding region and the N-type epitaxial layer will form a depletion region, which greatly reduces the flow path of the electron current and increases the on-resistance of the SiCMOSFET.

Summary of the invention

In order to solve the above problems existing in the prior art, the present invention provides a silicon carbide MOSFET device with a gate oxide protection structure and a preparation method. The technical problem to be solved by the present invention is achieved by the following technical solutions:

In a first aspect, an embodiment of the present invention provides a silicon carbide MOSFET device with a gate oxide protection structure, comprising:

The drain metal, N+ type silicon carbide substrate, N-type first silicon carbide epitaxial layer, N-type second silicon carbide epitaxial layer, interlayer insulating medium, and source metal are arranged in sequence from bottom to top; wherein,

In the N-type first silicon carbide epitaxial layer, P-type first doping regions are arranged on both sides of the top layer region, and an N-type first doping region is arranged between the P-type first doping regions on both sides; an N+ type first source region is arranged in part of the top layer region of the P-type first doping region on one side;

A P-type body region is arranged in a part of the top region of the N-type second silicon carbide epitaxial layer, and an N+-type second source region is arranged on one side of the P-type body region;

In the N-type second silicon carbide epitaxial layer, source trenches are arranged on both sides, and a gate trench is arranged between the two source trenches; the source trench runs through the N-type second silicon carbide epitaxial layer and the P-type first doped region, and the lower end extends into the N-type first silicon carbide epitaxial layer; a P+ type source region is arranged outside the source trench;

The source metal is arranged inside the source trench and on the interlayer insulating medium, and contacts the upper surface of a portion of the P-type body region and the N+ type second source region through the gap of the interlayer insulating medium; the side of the P-type body region away from the N+ type second source region contacts the P+ type source region of a source trench;

A gate oxide layer is arranged inside the gate trench, and polysilicon is deposited as a gate. The gate oxide layer on one side of the gate trench contacts the N+ type second source region, and the gate oxide layer on the bottom side contacts the N+ type first source region; the side of the N+ type first source region away from the gate oxide layer overlaps with the P+ type source region of another source trench and contacts the internal source metal.

In a second aspect, an embodiment of the present invention provides a method for preparing a silicon carbide MOSFET device with a gate oxide protection structure, which is used to prepare the silicon carbide MOSFET device with a gate oxide protection structure according to the first aspect, and the method comprises:

Selecting an N+ type silicon carbide substrate, and growing an N-type first silicon carbide epitaxial layer on the upper surface of the N+ type silicon carbide substrate;

By selectively injecting ions through a mask layer, a P-type first doping region is formed on both sides of the top layer region in the N-type first silicon carbide epitaxial layer, an N-type first doping region is formed between the P-type first doping regions on both sides, and an N+ type first source region is formed in a portion of the top layer region in the P-type first doping region on one side;

growing an N-type second silicon carbide epitaxial layer on the upper surface of the current structure;

By selectively injecting ions through a mask layer, a P-type body region is formed in a preset top region of the N-type second silicon carbide epitaxial layer, and an N+-type second source region is formed on one side of the P-type body region;

In the two side regions of the N-type second silicon carbide epitaxial layer, a source trench is formed by a dry plasma etching process, wherein the source trench penetrates the N-type second silicon carbide epitaxial layer and the P-type first doped region, and the lower end extends into the N-type first silicon carbide epitaxial layer; and a P+ type source region is formed on the outer side and bottom of the source trench by ion implantation, so that the P+ type source region on one side of the source trench overlaps with the N+ type first source region, and the P+ type source region on the other side of the source trench contacts the P type body region;

A gate trench is etched at a position between two source trenches in the N-type second silicon carbide epitaxial layer, a gate oxide layer is grown on an inner wall of the gate trench, so that the gate oxide layer on one side of the gate trench contacts the N+ type second source region, and the gate oxide layer on the bottom side contacts the N+ type first source region below, and polysilicon is deposited in the gate trench as a gate;

Depositing an interlayer insulating dielectric on the upper surface of the current structure, and removing the interlayer insulating dielectric inside the source trench, and above a portion of the P-type body region and the N+-type second source region;

A source metal is formed inside the source trench and on the interlayer insulating medium, and a drain metal is formed on the lower surface of the N+ type silicon carbide substrate.

Beneficial effects of the present invention:

The silicon carbide MOSFET device with a gate oxide protection structure provided by the embodiment of the present invention solves the technical problem that the electric field protection of the gate oxide layer of the trench-type silicon carbide MOSFET in the prior art is insufficient, especially the gate oxide layer at the corner is easily broken down by the electric field. The structure of the present invention not only solves the problem of the excessively high electric field of the gate oxide layer, but also innovatively proposes two conduction channels, vertical and horizontal, to increase the current density and solve the problem of increasing the on-resistance due to the introduction of the gate oxide protection structure. The structure of the present invention can maximize the use of the chip area.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic structural diagram of a silicon carbide MOSFET device with a gate oxide protection structure provided by an embodiment of the present invention;

FIG2a is a schematic diagram of the final structure of a silicon carbide MOSFET device with a gate oxide protection structure provided by an embodiment of the present invention;

FIG2b is a schematic diagram of the electric field intensity distribution along the AA direction of the structure 2a when simulating the reverse withstand voltage state;

FIG3 a is a schematic diagram of the final structure of a silicon carbide MOSFET device with a gate oxide protection structure provided by an embodiment of the present invention;

FIG3b is a schematic diagram of the electric field intensity distribution along the AB direction of the structure of FIG3a when simulating the reverse withstand voltage state;

FIG4 is a schematic diagram of the current path of the device structure of the present invention in the forward conduction state;

5 is a schematic flow chart of a method for preparing a silicon carbide MOSFET device with a gate oxide protection structure provided by an embodiment of the present invention;

6a to 6n are schematic diagrams of the process structure of a method for preparing a silicon carbide MOSFET device with a gate oxide protection structure provided by an embodiment of the present invention;

Reference numerals:

01: N+ type silicon carbide substrate; 02: N- type first silicon carbide epitaxial layer; 03: P-type first doped region; 04: N-type first doped region; 05: N+ type first source region; 06: N- type second silicon carbide epitaxial layer; 07: P-type body region; 08: N+ type second source region; 09: source trench; 10: P+ type source region; 11: silicon dioxide; 12: gate trench; 13: gate oxide layer; 14: polysilicon; 15: interlayer insulating dielectric; 16: source metal; 17: drain metal.

DETAILED DESCRIPTION

The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

In a first aspect, an embodiment of the present invention provides a silicon carbide MOSFET device with a gate oxide protection structure. Referring to FIG. 1 , the silicon carbide MOSFET device with a gate oxide protection structure includes:

The drain metal 17, N+ type silicon carbide substrate 01, N-type first silicon carbide epitaxial layer 02, N-type second silicon carbide epitaxial layer 06, interlayer insulating medium 15, and source metal 16 are arranged in sequence from bottom to top; wherein,

The N-type first silicon carbide epitaxial layer 02 has P-type first doping regions 03 on both sides of the top region, and an N-type first doping region 04 is arranged between the P-type first doping regions 03 on both sides; an N+ type first source region 05 is arranged in part of the top region of the P-type first doping region 03 on one side;

A P-type body region 07 is disposed in a portion of the top region of the N-type second silicon carbide epitaxial layer 06, and an N+-type second source region 08 is disposed on one side of the P-type body region 07;

In the N-type second silicon carbide epitaxial layer 06, source trenches 09 are arranged on both sides, and a gate trench 12 is arranged between the two source trenches 09; the source trench 09 penetrates the N-type second silicon carbide epitaxial layer 06 and the P-type first doped region 03, and the lower end extends into the N-type first silicon carbide epitaxial layer 02; the outer side of the source trench 09 is provided with a P+ type source region 10;

The source metal 16 is arranged inside the source trench 09 and on the interlayer insulating medium 15, and contacts the upper surface of a part of the P-type body region 07 and the N+ type second source region 08 through the gap of the interlayer insulating medium 15; the side of the P-type body region 07 away from the N+ type second source region 08 contacts the P+ type source region 10 of a source trench 09;

A gate oxide layer 13 is provided inside the gate trench 12, and polysilicon 14 is deposited as a gate. The gate oxide layer 13 on one side of the gate trench 12 is in contact with the N+ type second source region 08, and the gate oxide layer 13 on the bottom side is in contact with the N+ type first source region 05; the side of the N+ type first source region 05 away from the gate oxide layer 13 overlaps with the P+ type source region 10 of another source trench 09 and contacts the internal source metal 16.

For simplicity, the source trench 09 and the gate trench 12 are not shown in FIG. 1 .

Among them, an N+ type substrate is selected for preparing a high-concentration N-type drain, and the N+ type silicon carbide substrate 01 can be made of materials such as 4H SiC, 6H SiC or 3C SiC. For example, in the embodiment of the present invention, 4H SiC can be selected to prepare the N+ type silicon carbide substrate 01. The thickness of the N+ type silicon carbide substrate 01 can be 250-350 μm.

The N-type first silicon carbide epitaxial layer 02 is epitaxially grown on the N+ type silicon carbide substrate 01, and may have a thickness of 5 to 20 μm and a doping concentration of 4e15 cm ^-3 to 1.5e16 cm ^-3 .

Referring to Figure 1, P-type first doping regions 03 are arranged on both sides of the top layer area in the N-type first silicon carbide epitaxial layer 02, and N-type first doping regions 04 are arranged between the P-type first doping regions 03 on both sides; the P-type first doping region 03 arranged on one side has a larger width, which is used for the area corresponding to a source trench 09 and a gate trench 12 in the later stage, and the P-type first doping region 03 arranged on the other side has a smaller width, which corresponds to another source trench 09.

The P-type first doping region 03 is formed by ion implantation into the top region of the N-type first silicon carbide epitaxial layer 02. In an optional embodiment, the doping ions of the P-type first doping region 03 include aluminum ions, and the doping concentration may be 4e16cm ^-3 ~9e16cm ^-3 . The depth of the P-type first doping region 03 may be 1~1.5μm.

The N-type first doping region 04 and the P-type first doping regions 03 on both sides have a distance therebetween; the depth of the N-type first doping region 04 may be the same as the depth of the P-type first doping region 03 , and the depth of the N-type first doping region 04 may be 0.5-1.2 μm.

The N-type first doping region 04 is formed by ion implantation into the top region of the N-type first silicon carbide epitaxial layer 02 . The implanted ions may be nitrogen ions, and the doping concentration may be 1e15 cm ⁻³ to 6e15 cm ⁻³ , which reduces the on-resistance and protects the gate oxide layer 13 .

1 , an N+ type first source region 05 is disposed in a portion of the top region of the P-type first doping region 03 having a relatively large width; the depth of the N+ type first source region 05 does not exceed the depth of the P-type first doping region 03. The N+ type first source region 05 is also formed by ion implantation, and in an optional embodiment, the ions doped in the N+ type first source region 05 may be nitrogen ions, with a doping concentration higher than 1e19 cm-3.

The N-type second silicon carbide epitaxial layer 06 is located on the upper surface of the N-type first silicon carbide epitaxial layer 02, and is therefore also located on the upper surfaces of the P-type first doping region 03 and the N-type first doping region 04. The N-type second silicon carbide epitaxial layer 06 is obtained by epitaxial growth. The thickness of the N-type second silicon carbide epitaxial layer 06 can be 0.8~1.2μm, and the doping concentration range can be the same as the doping concentration range of the N-type first silicon carbide epitaxial layer 02.

A P-type body region 07 is disposed in a portion of the top region of the N-type second silicon carbide epitaxial layer 06, and the depth of the P-type body region 07 does not exceed the depth of the N-type second silicon carbide epitaxial layer 06; the P-type body region 07 is also formed by ion implantation, and the implanted ions include aluminum ions, and the doping concentration can be 2e16cm ^-3 ~8e16cm ^-3 .

From the perspective of position, the P-type body region 07 may be located above the N-type first doping region 04 and a portion of the P-type first doping region 03 .

An N+ type second source region 08 is disposed on one side of the P type body region 07. In an optional embodiment, the N+ type second source region 08 is disposed in the top region on one side of the P type body region 07. Of course, it can also be disposed in the entire region on one side of the P type body region 07, that is, the depth is consistent with the P type body region 07, and the specific selection can be made as needed. The N+ type second source region 08 is also formed by ion implantation, and the implanted ions include nitrogen ions, and the doping concentration can be the same as the doping concentration of the N+ type first source region 05.

In the embodiment of the present invention, the source trench 09 penetrates the N-type second silicon carbide epitaxial layer 06 and the P-type first doped region 03, so its width is smaller than the width of the P-type first doped region 03 penetrated, and its lower end extends into the N-type first silicon carbide epitaxial layer 02, but does not exceed the lower surface of the N-type first silicon carbide epitaxial layer 02. It can be specifically set according to device requirements. For example, in an optional implementation, the depth of the source trench 09 is 1.4~2.6μm, which is the optimal depth under the existing process capabilities to ensure that the depth of the source trench 09 is greater than or equal to the depth of the gate trench 12.

The bottom edge of the source trench 09 is arc-shaped to increase the contact area between the source metal 16 in the source trench 09 and the P+ source region 10 at the bottom of the outer side of the source trench 09, which is more conducive to the stability of the potential. The P+ source region 10 is arranged outside the source trench 09, that is, the P+ source region 10 is arranged on the left, right and bottom of the outer side of the source trench 09; the P+ source region 10 is formed by ion implantation of the outer side of the source trench 09, and the implanted ions can be aluminum ions, and the doping concentration can be 8e15cm ^-3 ~1e16cm ^-3 .

1 , the P+ type source region 10 on one side of the source trench 09 on the left side contacts the P type body region 07 to achieve ohmic contact, thereby achieving the function of stabilizing the potential.

The source metal 16 is arranged inside the source trench 09 and on the upper surface of the interlayer insulating medium 15; and the upper surfaces of the P-type body region 07 and the N+-type second source region 08 are also in contact with the source metal 16 filled in the gaps through the gaps of the interlayer insulating medium 15 to achieve ohmic contact.

The interlayer insulating medium 15 can be one of silicon dioxide, silicon nitride, silicon oxynitride, or any combination thereof. The source metal 16 can be an aluminum-silicon combination, an aluminum-copper combination, or pure aluminum, and can have a thickness of 3 to 5 μm. The drain metal 17 can be a titanium-nickel-silver combination, and can have a thickness of 0.2 to 0.8 μm.

As shown in Figure 1, the source trench 09 close to the N+ type first source region 05, that is, the source trench 09 on the right side, has a side wall on one side contacting the N+ type first source region 05, so that the N+ type first source region 05 can contact the inside of the source trench 09, so that outside the side wall of the source trench 09, after ions are injected to form the P+ type source region 10, there is a partial overlap with the N+ type first source region 05, and the overlapping area is the width of the P+ type source region 10 on this side. The embodiment of the present invention sets the doping concentration of the N+ type first source region 05 to be higher than the doping concentration of the P+ type source region 10, the N+ type first source region 05 is N-doped, and the P+ type source region 10 is P-doped, and the overlapping area between the N+ type first source region 05 and the P+ type source region 10 will show the characteristics of the N+ type first source region 05. After the N+ type first source region 05 contacts the source metal 16 in the source trench 09 , current can flow from the N+ type first source region 05 to the source metal 16 .

The inner wall of the gate trench 12 is provided with a gate oxide layer 13, and the material of the gate oxide layer 13 can be silicon dioxide, a combination of silicon dioxide and silicon nitride, or a combination of silicon dioxide and hafnium dioxide. The gate trench 12 is filled with polysilicon 14 as a gate. The side wall of the gate trench 12 away from the source trench 09 is in contact with the N+ type second source region 08, that is, the gate oxide layer 13 on the side wall is in contact with the N+ type second source region 08 (but the N+ type second source region 08 does not contact the polysilicon 14), thereby forming a corresponding current path C; and the gate oxide layer 13 on the bottom side of the gate trench 12 is in contact with the N+ type first source region 05. As can be seen from FIG. 1, the gate oxide layer 13 in the lower part of the gate trench 12 is in contact with the N+ type first source region 05.

Specifically, current can only flow in semiconductors of the same doping type. In the embodiment of the present invention, for example, N-type doping is divided into N+ type first source region 05, N+ type second source region 08, N- type second silicon carbide epitaxial layer 06, N- type first silicon carbide epitaxial layer 02, N-type first doping region 04, and N+ type silicon carbide substrate 01. After these regions are in contact, they are like conductors, and current can shuttle through these regions. If the current encounters a P-type region, it will stop. For example, the current C path is shown in Figure 4. The current flows from the drain metal 17—N+ type silicon carbide substrate 01—N- type first silicon carbide epitaxial layer 02—N-type first doping region 04—N- type second silicon carbide epitaxial layer 06, and is blocked by the P-type body region 07 when it reaches the P-type body region 07. At this time, the role of the gate will be reflected. When a forward voltage of 15-20V is applied to the polysilicon 14, a very thin channel (about 50nm) will be formed between the gate oxide layer 13 and the P-type body region 07. At this time, the current will pass through the channel between the gate oxide layer 13 and the P-type body region 07, flow to the N+ type second source region 08, and then flow to the source metal 16. If the N+ type second source region 08 is not in contact with the gate oxide layer 13, the current cannot form a path.

The gate oxide layer 13 on the side wall of the gate trench 12 close to the N+ type first source region 05 contacts the N+ type first source region 05 to form a corresponding current path D as shown in FIG4 . The same principle as the contact between the N+ type second source region 08 and the gate oxide layer 13, only when the gate oxide layer 13 contacts the N+ type first source region 05, the current path D can be established. Specifically, the current D path, the current goes from the drain metal 17—N+ type silicon carbide substrate 01—N-type first silicon carbide epitaxial layer 02—current to the right, the path is blocked by the P-type first doping region 03 on the right, when a forward voltage of 15~20V is applied to the polysilicon 14, a very thin channel (about 50nm) will be formed between the gate oxide layer 13 and the P-type first doping region 03, and the current flows through the channel and flows to the N+ type first source region 05, and then the current enters the source metal 16. The P-type body region 07 and the P-type first doped region 03 on the right side play a role of current blocking, and the polysilicon 14 and the gate oxide layer 13 function like a current switch.

In the embodiment of the present invention, the depth of the source trench 09 is greater than or equal to the depth of the gate trench 12 , so as to protect the gate oxide layer 13 of the gate.

The depth and width of the gate trench 12 can be set as needed, and its depth can reach the upper surface of the corresponding P-type first doping region 03, or extend therein, but the depth cannot exceed the depth of the N+ type first source region 05. For example, in an optional embodiment, the depth of the gate trench 12 can be 0.8-1.2 μm. The width of the gate trench 12 is 0.8-1.5 μm.

In the embodiment of the present invention, the gate of the silicon carbide MOSFET device with a gate oxide protection structure controls the opening of both lateral and longitudinal channels at the same time. The details can be understood in conjunction with the above text and related drawings, and will not be described in detail here.

The main problem of trench silicon carbide MOSFET devices is that the high electric field strength of the gate oxide layer in the reverse withstand state is too high. In order to maintain the long-term reliability of silicon carbide MOSFET devices, the maximum electric field strength of the gate oxide layer in the reverse withstand state of the device needs to be limited to below 3MV/cm. The field strength of the gate oxide layer in the reverse withstand state of trench silicon carbide MOSFET without a protection structure often reaches more than 8MV/cm, which is far higher than the requirement for electric field strength working reliability.

In the prior art, the most commonly used trench-type silicon carbide gate oxide protection structure is the asymmetric trench MOSFET proposed by Infineon, where one side of the gate trench is used for conduction and the other side is used for making a P+ shielding area, but this structure still introduces a large JFET resistance. Another method is the double trench MOSFET of Rohm, which introduces a gate trench and a source trench, but this structure still has a large gate oxide layer electric field strength in the center of the gate trench.

The breakdown electric field strength of silicon carbide material is 2.5MV/cm. At present, the biggest problem of trench silicon carbide is that when the device reaches the breakdown electric field strength, the electric field strength of the unprotected gate oxide layer can reach about 7.5MV/cm, while the safe electric field strength of the gate oxide layer for long-term operation must be below 3MV/cm. The silicon carbide MOSFET device proposed in the embodiment of the present invention has the effect of shielding and protecting the gate oxide layer. When the device is in a reverse withstand voltage state, the P+ type source region 10, the P-type first doping region 03, the N-type first doping region 04 and the N-type first silicon carbide epitaxial layer 02 are specifically used as the gate oxide protection structure to jointly deplete the gate oxide layer 13 of the gate trench 12 to reduce the electric field strength at the gate corner. Please refer to Figures 2a and 2b. Figure 2a is the final structure of the device of the present invention; Figure 2b is the electric field strength distribution of the 2a structure along the AA direction when simulating the reverse withstand voltage state. In Figure 2b, the horizontal axis represents the length of the simulated cross-sectional structure of the device, in μm, and the vertical axis represents the electric field strength, in V/cm. It can be seen from Figure 2b that the gate oxide strength at the gate corner is below 1MV/cm, which is much lower than the electric field strength of 3MV/cm. The gate oxide is effectively relieved, ensuring the reliability of the device.

Please refer to Figure 3a and Figure 3b. Figure 3a is the final structure of the device of the present invention; Figure 3b is the electric field intensity distribution along the AB direction of the structure of Figure 3a when simulating the reverse withstand voltage state. In Figure 3b, the horizontal axis represents the length of the simulated cross-sectional structure of the device, in μm, and the vertical axis represents the electric field intensity, in V/cm. It can be seen from Figure 3b that the strongest electric field intensity reaches more than 2.5MV/cm, and the strongest electric field intensity occurs in the P+ type source region 10 and the N-type first silicon carbide epitaxial layer 02 depletion region on the left, as well as the P-type first doping region 03 and the N-type first silicon carbide epitaxial layer 02 depletion region.

FIG2b and FIG3b are electric field strengths at different positions when the device is broken down. FIG3b proves that the breakdown point of the device is in the depletion region of the P+ type source region 10 and the N-type first silicon carbide epitaxial layer 02, and the depletion region of the P-type first doping region 03 and the N-type first silicon carbide epitaxial layer 02. At this time, the electric field strength of the gate oxide layer 13 is below 1MV/cm. The gate oxide layer 13 is in a relatively safe electric field environment.

It can be seen that the embodiment of the present invention forms a depletion region by depleting the P+ type source region 10 and the N-type first silicon carbide epitaxial layer 02 and the N-type first doping region 04, and depleting the N+ type first source region 05 and the N-type first silicon carbide epitaxial layer 02 and the N-type first doping region 04, shielding the high electric field and protecting the gate oxide layer 13. The structure of the present invention can solve the technical problem in the prior art that the electric field protection of the gate oxide layer of the trench silicon carbide MOSFET is insufficient, especially the gate oxide layer at the corner is easily broken down by the electric field.

The embodiment of the present invention solves the problem of too high electric field strength at the corners of the gate trench while increasing the path for device current flow. Specifically, two current paths, horizontal and vertical, are designed, which can effectively reduce the on-resistance of the device by increasing the current density of the device, thereby improving the current path of the chip.

Please refer to FIG. 4, which is a schematic diagram of the current path of the device structure of the present invention in the forward conduction state. Specifically, the two current paths when the device is working are C and D, where C is a longitudinal circuit path and D is a transverse current path. These two current paths are two conduction channels. As mentioned above:

For the current C path, the current flows from the drain metal 17—N+ type silicon carbide substrate 01—N- type first silicon carbide epitaxial layer 02—N- type first doped region 04—N- type second silicon carbide epitaxial layer 06, and is blocked by the P-type body region 07 when it reaches the P-type body region 07. At this time, the role of the gate will be reflected. When a forward voltage of 15~20V is applied to the polysilicon 14, a very thin channel (about 50nm) will be formed between the gate oxide layer 13 and the P-type body region 07. At this time, the current will pass through the channel between the gate oxide layer 13 and the P-type body region 07, flow to the N+ type second source region 08, and then flow to the source metal 16.

For the current D path, the current goes from the drain metal 17—N+ type silicon carbide substrate 01—N- type first silicon carbide epitaxial layer 02—current to the right, and the path is blocked by the P-type first doped region 03 on the right. When a forward voltage of 15~20V is applied to the polysilicon 14, a very thin channel (about 50nm) is formed between the gate oxide layer 13 and the P-type first doped region 03. After the current flows through the channel, it flows to the N+ type first source region 05, and then the current enters the source metal 16.

In summary, the silicon carbide MOSFET device with a gate oxide protection structure provided by the embodiment of the present invention solves the technical problem in the prior art that the electric field protection of the gate oxide layer of the trench-type silicon carbide MOSFET is insufficient, especially the gate oxide layer at the corner is easily broken down by the electric field. The structure of the present invention not only solves the problem of the excessively high electric field of the gate oxide layer, but also innovatively proposes two conduction channels, vertical and horizontal, to increase the current density, solve the problem of increasing the on-resistance due to the introduction of the gate oxide protection structure, and the structure of the present invention can maximize the use of the chip area.

In a second aspect, an embodiment of the present invention further provides a method for preparing a silicon carbide MOSFET device with a gate oxide protection structure, which is used to prepare the silicon carbide MOSFET device with a gate oxide protection structure provided in the first aspect. As shown in FIG. 5 , the preparation method includes:

S1 , selecting an N+ type silicon carbide substrate 01 , and growing an N− type first silicon carbide epitaxial layer 02 on the N+ type silicon carbide substrate 01 .

Specifically, an N+ type substrate is selected to form a high concentration N-type drain, and the N+ type substrate uses silicon carbide material. Specifically, the N+ type silicon carbide substrate 01 of the embodiment of the present invention can be 4H-SiC, 6H-SiC or 3C-SiC. For example, in an optional implementation, 4H-SiC material can be used. The thickness of the N+ type silicon carbide substrate 01 can be 250~350μm.

Then, an N-type first silicon carbide epitaxial layer 02 is epitaxially grown on the upper surface of the N+ type silicon carbide substrate 01, with a thickness of 5-20 μm and a doping concentration of 4e15 cm ^-3 -1.5e16 cm ^-3 . The epitaxial wafer is then cleaned, and the obtained structure is shown in FIG. 6a .

S2, by means of selective ion injection through a mask layer, a P-type first doping region 03 is formed on both sides of the top layer region in the N-type first silicon carbide epitaxial layer 02, an N-type first doping region 04 is formed between the P-type first doping regions 03 on both sides, and an N+ type first source region 05 is formed in part of the top layer region in the P-type first doping region 03 on one side.

Specifically, firstly, an oxide layer (the oxide layer is silicon dioxide) is deposited on the N-type first silicon carbide epitaxial layer 02, and an ion implantation window is etched by photolithography and etching processes, and ions are selectively implanted to form a P-type first doping region 03. The implanted ions may be aluminum ions, and the energy of the ion implantation may be 50-400 KeV, and the doping concentration may be 4e16 cm ^-3 -9e16 cm ^-3 . The depth of the P-type first doping region 03 may be 1-1.5 μm. The mask layer is removed to obtain the device structure shown in FIG. 6 b; the P-type first doping region 03 is located on both sides of the top layer region in the N-type first silicon carbide epitaxial layer 02.

Then, an oxide layer is deposited on the upper surface of the N-type first silicon carbide epitaxial layer 02 after ion implantation, and an ion implantation window is etched by photolithography and etching processes. Ions are selectively implanted in the region between the P-type first doping regions 03 to form an N-type first doping region 04; the doping ions of the N-type first doping region 04 include nitrogen ions, the energy of ion implantation can be 100~300KeV, and the doping concentration can be 1e15cm ^-3 ~6e15cm ^-3 . The mask layer is removed to obtain the device structure shown in Figure 6c; wherein, the N-type first doping region 04 and the P-type first doping regions 03 on both sides have a spacing; the depth of the N-type first doping region 04 can be the same as the depth of the P-type first doping region 03. The depth of the N-type first doping region 04 can be 0.5~1.2μm.

After that, an oxide layer is deposited on the upper surface of the N-type first silicon carbide epitaxial layer 02 after the second ion implantation, and an ion implantation window is etched out by photolithography and etching processes, and an N+ type first source region 05 is formed in a part of the top region of the P-type first doping region 03 on one side; the doping ions of the N+ type first source region 05 include nitrogen ions, and the ion implantation energy can be 50-120 KeV, and the doping concentration is higher than 1e19 cm ^-3 . The mask layer is removed to obtain the device structure shown in FIG6d ;

S3, growing an N-type second silicon carbide epitaxial layer 06 on the upper surface of the current structure.

That is, an N-type second silicon carbide epitaxial layer 06 is grown on the upper surface of the device structure shown in FIG. 6 d .

The thickness of the N-type second silicon carbide epitaxial layer 06 may be 0.8-1.2 μm, and the doping concentration range may be the same as the doping concentration range of the N-type first silicon carbide epitaxial layer 02. The device structure obtained in this step is shown in FIG6e.

S4, forming a P-type body region 07 in a preset top region of the N-type second silicon carbide epitaxial layer 06 by selectively injecting ions through a mask layer, and forming an N+-type second source region 08 on one side of the P-type body region 07 .

Specifically, firstly, an oxide layer is deposited on the N-type second silicon carbide epitaxial layer 06, and an ion implantation window is etched by photolithography and etching processes, and ions are selectively implanted to form a P-type body region 07. The P-type body region 07 can be located above the N-type first doping region 04 and part of the P-type first doping region 03, and the depth of the P-type body region 07 does not exceed the depth of the N-type second silicon carbide epitaxial layer 06. The ions implanted into the P-type body region 07 include aluminum ions, and the energy of the ion implantation can be 100~350KeV, and the doping concentration can be 2e16cm ^-3 ~8e16cm ^-3 . The mask layer is removed to obtain the device structure shown in FIG6f;

Then, an oxide layer is deposited on the N-type second silicon carbide epitaxial layer 06 after ion implantation, and an ion implantation window is etched in a local area on the upper surface of the P-type body region 07 by photolithography and etching processes, and ions are selectively implanted to form an N+ type second source region 08. The implanted ions may be nitrogen ions, the energy of the ion implantation may be 80-150 KeV, and the doping concentration may be 5e16cm ^-3 ~8e16cm ^-3 . The depth of the N+ type second source region 08 does not exceed the depth of the P-type body region 07, and may be close to one side edge of the P-type body region 07. After removing the mask, the device structure shown in FIG. 6g is obtained.

S5, forming source trenches 09 in the two side regions of the N-type second silicon carbide epitaxial layer 06 by dry plasma etching process, wherein the source trenches 09 penetrate the N-type second silicon carbide epitaxial layer 06 and the P-type first doped region 03, and the lower end extends into the N-type first silicon carbide epitaxial layer 02; and forming a P+ type source region 10 on the outer side and bottom of the source trench 09 by ion implantation, so that the P+ type source region 10 on one side of the source trench 09 overlaps with the N+ type first source region 05, and the P+ type source region 10 on the other side of the source trench 09 contacts with the P type body region 07.

Specifically, an oxide layer is first deposited on the entire upper surface of the current N-type second silicon carbide epitaxial layer 06, and a source trench 09 is etched in the two side regions through photolithography and dry plasma etching processes, which penetrates the N-type second silicon carbide epitaxial layer 06 and the P-type first doped region 03, and the lower end extends to the N-type first silicon carbide epitaxial layer 02. The source trench 09 may have a depth of 1.4-2.6 μm. After ion implantation at a certain angle outside the source trench 09, a P+ type source region 10 is formed on the left and right sides and the bottom outside the source trench 09. The bottom of the source trench 09 is arc-shaped. The implanted ions may be aluminum ions with a doping concentration of 8e15 cm ^-3 ~1e16 cm ^-3 , which is less than the doping concentration of the N+ type first source region 05, so that the P+ type source region 10 on one side overlaps with the N+ type first source region 05, and the overlapping area exhibits the characteristics of the N+ type first source region 05. The P+ type source region 10 on another side of the source trench 09 contacts the P type body region 07, thereby obtaining a device structure as shown in FIG. 6h ;

Next, the source trench 09 is filled on the entire upper surface of the current N-type second silicon carbide epitaxial layer 06 by chemical deposition. The filling material may be silicon dioxide 11, so as to obtain the device structure shown in FIG. 6i.

S6, etching a gate trench 12 at a position between two source trenches 09 in the N-type second silicon carbide epitaxial layer 06, growing a gate oxide layer 13 on the inner wall of the gate trench 12, so that the gate oxide layer 13 on one side of the gate trench 12 is in contact with the N+ type second source region 08, and the gate oxide layer 13 on the bottom side is in contact with the N+ type first source region 05 below, and depositing polysilicon 14 in the gate trench 12 as a gate;

Specifically, firstly, the silicon dioxide 11 on the N-type second silicon carbide epitaxial layer 06 is removed by chemical mechanical polishing. Then, the gate trench 12 is etched by photolithography and etching to obtain the device structure shown in FIG. 6j; wherein, the gate trench 12 is located between the two source trenches 09, and the depth is less than the depth of the source trench 09. The width of the gate trench 12 can be 0.8-1.5 μm.

Then, a sacrificial oxide layer is grown in the gate trench 12, and the sacrificial oxide layer is removed within a certain period of time, and then a gate oxide layer 13 is grown on the inner wall and the bottom through a high-temperature furnace tube, and the temperature may be 1100-1200° C. The material of the gate oxide layer 13 may be silicon dioxide, a combination of silicon dioxide and silicon nitride, or a combination of silicon dioxide and hafnium dioxide.

After cleaning with RCA (standard cleaning solution) and annealing, polysilicon 14 is deposited in the gate trench 12, and the remaining polysilicon 14 on the N-type second silicon carbide epitaxial layer 06 is removed to obtain the device structure shown in Figure 6k. Among them, the gate oxide layer 13 on one side of the gate trench 12 is in contact with the N+ type second source region 08, and the right side and lower part of the gate oxide layer 13 are in contact with the N+ type first source region 05.

S7, depositing an interlayer insulating dielectric 15 on the upper surface of the current structure, and removing the interlayer insulating dielectric 15 inside the source trench 09 and above a portion of the P-type body region 07 and the N+-type second source region 08;

An interlayer insulating dielectric 15 is deposited on the upper surface of the device structure shown in FIG. 6k.

Specifically, the interlayer insulating dielectric 15 can be silicon dioxide, silicon nitride, silicon oxynitride, or any combination thereof. The device structure after the interlayer insulating dielectric 15 is deposited is shown in FIG. 61 .

Afterwards, the interlayer insulating dielectric 15 in the source trench 09, part of the P-type body region 07 and the interlayer insulating dielectric 15 above the N+-type second source region 08 are etched cleanly by selective etching using the mask layer. Please refer to FIG. 6m for the obtained device structure.

S8 , forming a source metal 16 inside the source trench 09 and on the interlayer insulating dielectric 15 , and forming a drain metal 17 below the N+ type silicon carbide substrate 01 .

Specifically, a source metal 16 is formed inside the source trench 09 and on the interlayer insulating medium 15, so that the source metal 16 contacts a portion of the P-type body region (07) and the upper surface of the N+-type second source region (08), and fills the source trench 09. A back metal is then deposited to form a drain metal 17.

The source metal 16 may be an aluminum-silicon combination, an aluminum-copper combination, or pure aluminum, and may have a thickness of 3 to 5 μm, and the drain metal 17 may be a titanium-nickel-silver combination, and may have a thickness of 0.2 to 0.8 μm. The obtained device structure is shown in FIG6n .

At this point, the device is completed.

The method for preparing a silicon carbide MOSFET device with a gate oxide protection structure provided by an embodiment of the present invention solves the technical problem in the prior art that the electric field protection of the gate oxide layer of the trench-type silicon carbide MOSFET is insufficient, especially the gate oxide layer at the corner is easily broken down by the electric field. The structure of the present invention not only solves the problem of the gate oxide layer having an excessively high electric field, but also innovatively proposes two conduction channels, longitudinal and transverse, to increase the current density, solve the problem of increasing the on-resistance due to the introduction of the gate oxide protection structure, and the structure of the present invention can maximize the use of the chip area.

The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims (10)

1. A silicon carbide MOSFET device having a gate oxide protection structure, comprising:

the device comprises drain metal (17), an N+ type silicon carbide substrate (01), an N-type first silicon carbide epitaxial layer (02), an N-type second silicon carbide epitaxial layer (06), an interlayer insulating medium (15) and source metal (16) which are sequentially arranged from bottom to top; wherein,

P-type first doped regions (03) are arranged at two sides in a top layer region in the N-type first silicon carbide epitaxial layer (02), and N-type first doped regions (04) are arranged between the P-type first doped regions (03) at two sides; an N+ type first source region (05) is arranged in a part of the top layer region of the P type first doped region (03) at one side;

a P-type body region (07) is arranged in a part of the top layer region of the N-type second silicon carbide epitaxial layer (06), and an N+ type second source region (08) is arranged on one side of the P-type body region (07);

in the N-type second silicon carbide epitaxial layer (06), source grooves (09) are formed in two sides of the second silicon carbide epitaxial layer, and a grid groove (12) is formed between the two source grooves (09); the source electrode groove (09) penetrates through the N-type second silicon carbide epitaxial layer (06) and the P-type first doping region (03), and the lower end of the source electrode groove extends into the N-type first silicon carbide epitaxial layer (02); a P+ type source region (10) is arranged outside the source electrode groove (09);

The source metal (16) is arranged in the source groove (09) and above the interlayer insulating medium (15) and contacts the upper surfaces of the part P-type body region (07) and the N+ type second source region (08) through the gap of the interlayer insulating medium (15); one side of the P-type body region (07) far away from the N+ type second source region (08) is in contact with a P+ type source region (10) of one source trench (09);

A gate oxide layer (13) is arranged in the gate trench (12), polysilicon (14) is deposited as a gate, the gate oxide layer (13) on one side of the gate trench (12) is contacted with the N+ type second source region (08), and the gate oxide layer (13) on the bottom side is contacted with the N+ type first source region (05); the side of the N+ type first source region (05) far away from the gate oxide layer (13) is overlapped with the P+ type source region (10) of the other source trench (09) and contacts the internal source metal (16).

2. The silicon carbide MOSFET device with a gate oxide protection structure of claim 1, wherein the n+ -type second source region (08) is disposed in a top layer region on one side of the P-type body region (07).

3. The silicon carbide MOSFET device with a gate oxide protection structure of claim 1, wherein the depth of the source trench (09) is greater than or equal to the depth of the gate trench (12).

4. The silicon carbide MOSFET device with the gate oxide protection structure of claim 1, wherein the gate of the silicon carbide MOSFET device with the gate oxide protection structure simultaneously controls the turn-on of both the lateral and longitudinal channels.

5. The silicon carbide MOSFET device with a gate oxide protection structure of claim 1, wherein the gate trench (12) has a width of 0.8-1.5 μm.

6. The silicon carbide MOSFET device with the gate oxide protection structure of claim 1, wherein the source trench (09) has a depth of 1.4-2.6 μm.

7. The silicon carbide MOSFET device with the gate oxide protection structure of claim 1, wherein the dopant ions of the P-type first doped region (03) comprise aluminum ions with a dopant concentration of 4e16cm ^-3~9e16cm^-3.

8. The silicon carbide MOSFET device with the gate oxide protection structure of claim 1, wherein the dopant ions of the N-type first doped region (04) comprise nitrogen ions with a dopant concentration of 1e15cm ^-3~6e15cm^-3.

9. The silicon carbide MOSFET device with a gate oxide protection structure of claim 1, wherein the dopant ions of the P-type body region (07) comprise aluminum ions with a dopant concentration of 2e16cm ^-3~8e16cm^-3.

10. A method for preparing a silicon carbide MOSFET device having a gate oxide protection structure, for preparing a silicon carbide MOSFET device having a gate oxide protection structure according to any one of claims 1-9, the method comprising:

selecting an N+ type silicon carbide substrate (01), and growing an N-type first silicon carbide epitaxial layer (02) on the upper surface of the N+ type silicon carbide substrate (01);

Forming P-type first doped regions (03) on two sides in a top layer region in the N-type first silicon carbide epitaxial layer (02) by utilizing a mode of selectively implanting ions into a mask layer, forming N-type first doped regions (04) between the P-type first doped regions (03) on two sides, and forming N+ type first source regions (05) in part of the top layer region in the P-type first doped regions (03) on one side;

growing an N-type second silicon carbide epitaxial layer (06) on the upper surface of the current structure;

Forming a P-type body region (07) in a preset top layer region in the N-type second silicon carbide epitaxial layer (06) by utilizing a mode of selectively implanting ions into a mask layer, and forming an N+ type second source region (08) on one side of the P-type body region (07);

forming source grooves (09) in two side areas in the N-type second silicon carbide epitaxial layer (06) by utilizing a dry plasma etching process, wherein the source grooves (09) penetrate through the N-type second silicon carbide epitaxial layer (06) and the P-type first doping area (03), and the lower ends of the source grooves extend into the N-type first silicon carbide epitaxial layer (02); forming a P+ type source region (10) at the outer side and the bottom of the source groove (09) through ion implantation, so that the P+ type source region (10) at one side of one source groove (09) is overlapped with the N+ type first source region (05), and the P+ type source region (10) at one side of the other source groove (09) is contacted with the P type body region (07);

Etching a gate groove (12) at a position between two source grooves (09) in the N-type second silicon carbide epitaxial layer (06), growing a gate oxide layer (13) on the inner wall of the gate groove (12) so that the gate oxide layer (13) on one side of the gate groove (12) is contacted with the N+ type second source region (08), contacting the gate oxide layer (13) on the bottom side with an N+ type first source region (05) below, and depositing polysilicon (14) in the gate groove (12) as a gate;

depositing an interlayer insulating medium (15) on the upper surface of the current structure, and removing the interlayer insulating medium (15) inside the source electrode groove (09) and above part of the P-type body region (07) and the N+ type second source region (08);

A source metal (16) is formed inside the source trench (09) and on the interlayer insulating medium (15), and a drain metal (17) is formed on the lower surface of the N+ type silicon carbide substrate (01).