CN119480817A - Package structure - Google Patents
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- Publication number
- CN119480817A CN119480817A CN202510058551.1A CN202510058551A CN119480817A CN 119480817 A CN119480817 A CN 119480817A CN 202510058551 A CN202510058551 A CN 202510058551A CN 119480817 A CN119480817 A CN 119480817A
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- Prior art keywords
- substrate
- chip
- heat dissipation
- package structure
- packaging structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 230000017525 heat dissipation Effects 0.000 claims abstract description 41
- 238000004806 packaging method and process Methods 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 40
- 239000000853 adhesive Substances 0.000 claims description 12
- 230000001070 adhesive effect Effects 0.000 claims description 12
- 239000005022 packaging material Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 11
- 238000005538 encapsulation Methods 0.000 description 6
- 238000005336 cracking Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 125000004122 cyclic group Chemical group 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
本公开提供一种封装结构，包括：基板；芯片，所述芯片设置于所述基板上；散热组件，所述散热组件覆盖所述芯片，所述散热组件有引脚，所述引脚设置于所述基板上。这样，散热组件通过引脚和基板连接，散热组件的刚性可以有效抑制基板边缘的翘曲。
The present disclosure provides a packaging structure, comprising: a substrate; a chip, the chip is arranged on the substrate; a heat dissipation component, the heat dissipation component covers the chip, the heat dissipation component has pins, and the pins are arranged on the substrate. In this way, the heat dissipation component is connected to the substrate through the pins, and the rigidity of the heat dissipation component can effectively suppress the warping of the edge of the substrate.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductor packaging, in particular to a packaging structure.
Background
In most packaging structures, signal I/O (input/output) is typically laid out on the chip surface using bumps. In order to realize interconnection between the chip and the substrate, the chip with the bump is generally subjected to mirror-image flip by 180 degrees, so that the active area of the chip faces the substrate, and the welding process is completed.
However, it is noted that the high temperature environment may cause warpage of the substrate. When the temperature returns to room temperature, the substrate will attempt to recover its original form, but the substrate may crack due to the stress caused by the warpage of the substrate and the mismatch of the thermal expansion coefficients of the materials of the respective parts. In addition, the warpage stress may act on the Bump (Bump) and the chip, so as to cause problems such as Bump cracking, bridging short circuit, cold joint, and cracking of an electrical layer in the chip, and adversely affect the overall quality of the circuit.
Disclosure of Invention
Embodiments of the present disclosure provide a package structure.
In a first aspect, embodiments of the present disclosure provide a package structure, including:
A substrate;
the chip is arranged on the substrate;
The heat dissipation assembly covers the chip, and is provided with pins, and the pins are arranged on the substrate.
In some alternative embodiments, the heat dissipation assembly is provided with a metal support block, one end of which is connected to the substrate.
In some alternative embodiments, the metal support block is a ring-shaped structure or a columnar structure.
In some alternative embodiments, the heat dissipating component is hat-shaped or in a zigzag shape.
In some alternative embodiments, the package structure further includes:
And the packaging material is filled between the chip and the substrate.
In some alternative embodiments, the package structure further includes:
and the first adhesive is filled between the chip and the heat dissipation component.
In some alternative embodiments, the package structure further includes:
And the second adhesive is filled between the pins and the substrate and/or between the metal supporting block and the substrate.
In some alternative embodiments, the package structure further includes:
and the passive element is arranged on the substrate and is covered by the heat dissipation component.
In some alternative embodiments, the chip is provided with metal bumps, and the metal bumps are electrically connected with the substrate.
In some alternative embodiments, the package structure further includes:
and the metal balls are arranged on the bottom surface of the substrate far away from the chip.
In order to solve the problem of substrate warpage, the package structure provided by the embodiment of the disclosure effectively suppresses warpage of the edge of the substrate by arranging the pins (slots) of the heat dissipation assembly on the substrate and utilizing the rigidity of the heat dissipation assembly.
Drawings
Other features, objects and advantages of the present disclosure will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings. The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the disclosure. In the drawings:
FIG. 1 is a schematic diagram of a prior art package structure;
FIG. 2 is a schematic diagram of a package structure 100 according to one embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a package structure 200 according to one embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a package structure 300 according to one embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a package structure 400 according to one embodiment of the present disclosure;
FIG. 6 is a transverse cross-sectional view of a package structure along AA' according to one embodiment of the present disclosure;
FIG. 7 is another lateral cross-sectional view of a package structure along AA' according to one embodiment of the present disclosure;
FIG. 8 is a schematic diagram of a package structure 500 according to one embodiment of the present disclosure;
FIG. 9 is a schematic diagram of a package structure 600 according to one embodiment of the present disclosure;
fig. 10 is a side view of the heat sink assembly 103 of the package structure 500 according to one embodiment of the present disclosure;
fig. 11 is a side view of the heat sink assembly 103 of the package structure 600 according to one embodiment of the present disclosure.
Reference numerals/symbol description:
01-substrate, 02-chip, 021-bump, 022-underfill, 03-passive element, 101-substrate, 102-chip, 1021-metal bump, 103-heat dissipation component, 1031-pin, 1032-metal supporting block, 104-packaging material, 105-first adhesive, 106-second adhesive, 107-passive element and 108-metal ball.
Detailed Description
With the vigorous development of high performance computing, internet, and big data industries, the process technology of integrated circuits is advancing, so that it is possible to lead out more I/O (input/output) signals on a limited chip area, but this also presents a higher challenge for the design of chips and package substrates.
To address this challenge, the industry has commonly adopted an efficient form of packaging, bump Flip Chip-Ball GRID ARRAY (FC-BGA) packaging. Referring specifically to FIG. 1, bumps 021 distribute the signal I/O over the surface of chip 02. Then, the chip 02 with the bumps 021 is mirror-inverted by 180 ° so that the active area of the chip 02 directly faces the substrate 01, and interconnection of the chip 02 and the substrate 01 is achieved by soldering. Meanwhile, underfill 022 is filled in the bump array to protect the chip and the bumps. In some package structures, the substrate 01 may further be provided with a passive element 03, such as a capacitor, a resistor, and an inductor. The packaging mode not only greatly improves the integration level of the I/O signals, but also effectively reduces the delay and loss of signal transmission, thereby obviously improving the performance of the chip 02. However, with the increasing package size (such as the package sizes of 70mm×70mm and above that already achieved in the industry), the problem of warpage of the substrate 01 is also becoming increasingly prominent.
In particular, the packaging process of the package structure requires high/low temperature cycle variation. The substrate 01 will warp due to high temperature, but when the temperature is reduced to room temperature, the substrate 01 needs to return to its original position, and the warp stress will be applied to the bump 021 and the chip 02, so as to cause problems of cracking of the bump 021, bridging short circuit, cold joint, cracking of the electrical layer in the chip 02, etc. Meanwhile, in the temperature change process, the problems of fracture of the lamination holes in the substrate 01, delamination of the bonding surface of the underfill 022, failure of connection between the bump 021 and the substrate 01, cracking of the low-dielectric-constant dielectric layer of the chip 02 and the like are caused by stress generated by the warpage of the substrate 01 and mismatching of the thermal expansion coefficients of the materials of all parts. Further, the flatness of the bumps 021 is affected, resulting in poor adhesion, poor dummy solder, reduced circuit performance of short circuit and the like, and even failure.
In order to solve the above problems, the following description of the embodiments of the present disclosure will be given with reference to the accompanying drawings and examples, and those skilled in the art will readily understand the technical problems and effects solved by the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. In addition, for convenience of description, only a portion related to the related invention is shown in the drawings.
It should be readily understood that the meanings of "on," "over," and "above" in this disclosure should be interpreted in the broadest sense so that "on" means not only "directly on" but also "on" including intermediate components or layers that exist therebetween.
Further, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The term "layer" as used herein refers to a portion of material that includes regions having a certain thickness. The layers may extend over the entire underlying or overlying structure, or may have a degree less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontally oriented planes therebetween. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate (substrate) may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or thereon. One layer may comprise multiple layers. For example, the semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.
The term "substrate" as used herein refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer, or the like. Further alternatively, the substrate may have a semiconductor device or a circuit formed therein.
It should be noted that, the structures, proportions, sizes, etc. shown in the drawings are merely used in conjunction with the descriptions of the structures, proportions, sizes, etc. for the understanding and reading of the disclosure, and are not intended to limit the applicable limitations of the disclosure, so that any structural modifications, proportional changes, or adjustments of sizes are not technically essential, and thus, any structural modifications, proportional changes, or adjustments of sizes may fall within the scope of the disclosure without affecting the efficacy or achievement of the present disclosure. Also, the terms "upper", "first", "second", and "a" and the like recited in the present specification are also for descriptive purposes only and are not intended to limit the scope of the disclosure in which the present disclosure may be practiced, but rather the relative relationship of the terms is modified or adapted to be within the scope of the disclosure without substantial modification to the technical content.
It should be further noted that, the longitudinal section corresponding to the embodiment of the present disclosure may be a section corresponding to a front view direction, the transverse section may be a section corresponding to a right view direction, and the horizontal section may be a section corresponding to an upper view direction.
In addition, embodiments of the present disclosure and features of embodiments may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Referring to fig. 2, fig. 2 is a schematic diagram of a package structure 100 according to one embodiment of the present disclosure. The package structure 100 shown in fig. 2 includes:
a substrate 101;
A chip 102, wherein the chip 102 is disposed on the substrate 101;
and a heat dissipation assembly 103, wherein the heat dissipation assembly 103 covers the chip 102, and the heat dissipation assembly 103 is provided with a pin 1031, and the pin 1031 is disposed on the substrate 101.
In this way, when the substrate 101 may deform under the influence of temperature, the pins 1031 on the heat dissipation assembly 103 are tightly connected with the substrate 101, so that the deformation is effectively balanced, and the warpage phenomenon of the substrate 101 is restrained by utilizing the characteristic of the firmness of the heat dissipation assembly 103, so as to ensure the stability of the electronic element. Meanwhile, the heat dissipation assembly 103 is in contact with the chip 102, so that heat generated by the chip 102 can be timely conducted to the heat dissipation assembly 103 and dissipated, and potential problems possibly caused by heat accumulation are avoided.
As a possible implementation, the chip 102 may be disposed above the substrate 101 by flip-chip bonding (the active region directly faces the substrate 101), and the encapsulation material 104 is filled between the two, so that the connection between the chip 102 and the substrate 101 is more stable. In addition, the active surface of the chip 102 may be further provided with a metal bump 1021 for electrically connecting with the substrate 101, and at this time, the metal bump 1021 is smaller in size and weaker, and the filled packaging material 104 may protect the metal bump 1021 disposed on the chip 102. As an example, the encapsulation material 104 may be various Underfill (Underfill).
As one possible embodiment, a portion of the lower surface of the heat sink member 103 that does not contact the substrate may be connected to the upper surface of the chip 102 by the first adhesive 105, that is, the first adhesive 105 is filled between the chip 102 and the heat sink member 103. Thus, seamless contact between the two is ensured, and heat conduction efficiency is greatly optimized. As an example, the first adhesive 105 may be a heat conductive glue, in particular TIM (Thermal Interface Material) glue.
As one possible implementation, the pins 1031 of the heat dissipation assembly 103 may be connected to the substrate 101 by the second adhesive 106, that is, the second adhesive 106 is filled between the pins 1031 and the substrate 101. In this way, the connection between the pins 1031 and the substrate 101 is more secure, helping to resist deformation of the substrate 101 that may occur during temperature changes.
As a possible implementation, the substrate 101 may further be provided with passive elements 107, such as a capacitor, a resistor, an inductor, etc., to perform its electrical function. Wherein the passive elements 107 may be covered by the heat sink assembly 103, but not in contact. The number and positions of the passive elements 107 may be set as needed, and are not limited herein.
As one possible implementation, the bottom surface of the substrate 101 remote from the chip 101 may be provided with metal balls 108 for electrical connection with other circuits or devices. The metal balls 108 may be conductive spheres that may be secured to the bottom surface of the substrate 101 by soldering or other suitable connection means to form reliable electrical connection points. The connection mode is convenient for installing the circuit board and ensures the stability and the transmission reliability of signals.
As one possible implementation, with further reference to fig. 3, fig. 3 is a schematic diagram of a package structure 200 according to one embodiment of the present disclosure, the package structure 200 being similar to the package structure 100, except that:
The heat dissipation member 103 of the package structure 100 is hat-shaped, and the heat dissipation member 103 of the package structure 200 is zigzag-shaped. The design of the Chinese character 'Hui' shape is adopted, so that the heat dissipation effect is optimized, and the overall strength of the packaging structure is improved. The periphery of the heat dissipation assembly surrounds the chip 102, so that heat generated by the chip can be effectively guided to the periphery and dissipated, and the accumulation of the heat around the chip is reduced, so that the normal operation of the chip is ensured. At the same time, this design also allows for additional circuit elements or connection lines to be placed in the void, making the package more compact and flexible.
On the basis of the package structure 100 and the package structure 200, when the substrate 101 is large in size, the heat dissipation assembly 103 can effectively suppress warpage of the edge of the substrate 101, but the improvement of warpage of the inner edge of the leads 1031 to the large area of the outer edge of the package material 104 may not be very desirable. In particular, in the area near the encapsulation material 104, the stress generating point may be closer to the chip 102 in the case of cyclic variation of high and low temperatures due to the mismatch of thermal expansion coefficients of the chip 102, the metal bump 1021, the encapsulation material 104 and the substrate 101, and the portion may also generate warpage, which may be specifically referred to as the encapsulation structure 300 shown in fig. 4 and the encapsulation structure 400 shown in fig. 5.
To further solve the warpage problem, as shown in fig. 8 and 9, a metal support block 1032 may be provided on the heat sink 103, and one end of the metal support block 1032 is connected to the substrate 101. In this way, the rigidity of the metal supporting block 1032 is utilized to suppress the warpage of the substrate near the chip 102 in a segmented manner, further suppress the warpage of the substrate in the range of the air cavity (i.e. the cavity between the heat dissipation assembly and the substrate), reduce the impact of the stress generated by deformation on the chip 102, the metal bump 1021, the packaging material 104 and the substrate 101, and increase the bearing capacity of the packaging structure on the high-low temperature cyclic variation scene. Meanwhile, the flatness of the metal balls 108 can be improved, and particularly, the effect of improving a large-size packaging structure is more obvious, and the surface mounting of the printed circuit board is facilitated.
Specifically, as one possible implementation, with further reference to fig. 8, fig. 8 is a schematic diagram of a package structure 500 according to one embodiment of the present disclosure, the package structure 500 being similar to the package structure 100, except that:
The heat dissipation assembly 103 of the package structure 100 is not provided with the metal supporting blocks 1032, while the heat dissipation assembly 103 of the package structure 500 is provided with the metal supporting blocks 1032, so that the effect of suppressing the warpage of the substrate in the air range is further enhanced by utilizing the solid characteristics of the metal supporting blocks 1032, thereby significantly reducing the stress caused by deformation.
As one possible implementation, with further reference to fig. 9, fig. 9 is a schematic diagram of a package structure 600 according to one embodiment of the present disclosure, the package structure 600 being similar to the package structure 200, except that:
The heat dissipation component 103 of the package structure 200 is not provided with the metal supporting blocks 1032, while the heat dissipation component 103 of the package structure 600 is provided with the metal supporting blocks 1032, so that by utilizing the solid characteristic of the metal supporting blocks 1032, more effective suppression of the warpage of the substrate in the air cavity range is realized, and the stress level caused by deformation is remarkably reduced.
Optionally, a second adhesive 106 may be filled between the metal support block 1032 and the substrate 101 to increase the stability of the metal support block 1032. The number and location of the metal support blocks 1032 may be set according to specific needs and are not limited herein.
For example, the heat dissipation member 103 may be disposed in an air chamber so long as the mounting of other components on the surface of the substrate 101 is not affected. The cross section along AA' of the package structure shown in fig. 8 and 9 may be as shown in fig. 6, where the metal supporting blocks 1032 are a plurality of columnar structures arranged in a dispersed manner. The size and number of the columnar structures may be set according to actual needs, and are not limited herein. Meanwhile, the cross section of the pin 1031 constitutes a ring structure, and the size (each side length) of the ring structure may be set as needed, without limitation.
Or the cross section along AA' of the package structure in fig. 8 and 9 may be as shown in fig. 7, and the metal supporting block 1032 also forms a ring structure as the pins 1031 of the heat dissipation assembly 103. The dimensions (length of each side) of the annular structure formed by the metal support block 1032 may be set as desired, and are not limited herein. The number of the annular structures can also be set according to actual needs, and is not limited herein.
It should be noted that, the heat dissipation assembly 103 and the metal supporting block 1032 may be integrally formed, so that a side view of the heat dissipation assembly 103 in the package structure 500 shown in fig. 8 may be shown in fig. 10, and a side view of the heat dissipation assembly 103 in the package structure 600 shown in fig. 9 may be shown in fig. 11.
As used herein, the terms "substantially," "about," and "approximately" are used to indicate and explain minor variations. For example, when used in connection with a numerical value, the term may refer to a range of variation of less than or equal to the corresponding numerical value of + -10%, such as a range of variation of less than or equal to + -5%, less than or equal to + -4%, less than or equal to + -3%, less than or equal to + -2%, less than or equal to + -1%, less than or equal to + -0.5%, less than or equal to + -0.1%, or less than or equal to + -0.05%. As another example, the thickness of a film or layer may be "substantially uniform" to refer to an average thickness of the film or layer that is less than or equal to a standard deviation of ± 10%, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1% or less than or equal to ± 0.05% standard deviation. The term "substantially coplanar" may refer to two surfaces lying within 50 μm along the same plane (such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm along the same plane). Two components may be considered to be "substantially aligned" if, for example, the two components overlap or overlap within 200 μm, 150 μm, 100 μm, 50 μm, 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm. Two surfaces or components may be considered "substantially perpendicular" if the angle between them is, for example, 90 ° ± 10 ° (such as ± 5 °, ±4 °, ±3°, ±2°, ±1°, ±0.5 °, ±0.1°, or ± 0.05 °). When used in connection with an event or circumstance, the terms "substantially," "substantial," "about," and "approximately" can refer to the precise occurrence of the event or circumstance and the very close proximity of the event or circumstance.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202510058551.1A CN119480817A (en) | 2025-01-15 | 2025-01-15 | Package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202510058551.1A CN119480817A (en) | 2025-01-15 | 2025-01-15 | Package structure |
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| Publication Number | Publication Date |
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| CN119480817A true CN119480817A (en) | 2025-02-18 |
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| CN202510058551.1A Pending CN119480817A (en) | 2025-01-15 | 2025-01-15 | Package structure |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN209843689U (en) * | 2019-06-17 | 2019-12-24 | 星科金朋半导体（江阴）有限公司 | Chip packaging structure |
| CN210668340U (en) * | 2019-12-03 | 2020-06-02 | 星科金朋半导体（江阴）有限公司 | Heat radiation structure of base plate |
| CN113380725A (en) * | 2021-04-29 | 2021-09-10 | 苏州通富超威半导体有限公司 | Chip packaging structure and packaging method |
| CN217485436U (en) * | 2022-06-17 | 2022-09-23 | 盛合晶微半导体(江阴)有限公司 | Chip packaging structure |
-
2025
- 2025-01-15 CN CN202510058551.1A patent/CN119480817A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN209843689U (en) * | 2019-06-17 | 2019-12-24 | 星科金朋半导体（江阴）有限公司 | Chip packaging structure |
| CN210668340U (en) * | 2019-12-03 | 2020-06-02 | 星科金朋半导体（江阴）有限公司 | Heat radiation structure of base plate |
| CN113380725A (en) * | 2021-04-29 | 2021-09-10 | 苏州通富超威半导体有限公司 | Chip packaging structure and packaging method |
| CN217485436U (en) * | 2022-06-17 | 2022-09-23 | 盛合晶微半导体(江阴)有限公司 | Chip packaging structure |
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