CN119420348A

CN119420348A - Fully digital delay phase-locked loop circuit and calibration method

Info

Publication number: CN119420348A
Application number: CN202510012678.XA
Authority: CN
Inventors: 王天宇; 李健剑; 尹平; 王天石; 刁进科
Original assignee: Suzhou Poweron IC Design Co Ltd
Current assignee: Suzhou Poweron IC Design Co Ltd
Priority date: 2025-01-06
Filing date: 2025-01-06
Publication date: 2025-02-11
Anticipated expiration: 2045-01-06
Also published as: CN119420348B

Abstract

The present application provides a fully digital delay phase-locked loop circuit and a calibration method, and relates to the technical field of integrated circuits. The fully digital delay phase-locked loop circuit includes: a frequency divider, a phase detector, a calibration logic circuit and a digitally controlled delay line; the input end of the frequency divider receives a reference clock signal, the first output end of the frequency divider is connected to the input end of the digitally controlled delay line, and provides a reference pulse signal; the second output end of the frequency divider is connected to the first input end of the phase detector, and provides a phase detection sampling pulse signal; the second input end of the phase detector is connected to the output end of the digitally controlled delay line, and receives a delayed pulse signal after the digitally controlled delay line delays the reference pulse signal; the output end of the phase detector is connected to the input end of the calibration logic circuit, and provides a phase detection result; the output end of the calibration logic circuit is connected to the control end of the digitally controlled delay line, and the delay step of the digitally controlled delay line is calibrated according to the phase detection result, so as to calibrate the delay of the delayed pulse signal. The present application can reduce the phase detection error and improve the calibration accuracy.

Description

All-digital delay phase-locked loop circuit and calibration method

Technical Field

The application relates to the technical field of integrated circuits, in particular to an all-digital delay phase-locked loop circuit and a calibration method.

Background

An all-digital delay phase-Locked Loop (ALL DIGITAL DELAY Locked Loop, ADDLL) is widely applied to the design of modern micro-controller chips and systems on chip, and is used for realizing functions such as clock compensation and phase adjustment. Compared with an analog delay locked loop, the all-digital delay locked loop is insensitive to the working environment, such as temperature, voltage change and the like, and is increasingly applied in the digital timing field.

With the gradual improvement of the working precision requirement of the full digital delay phase-locked loop, the length of the digital control delay line is increased continuously, and the deviation of the phase discrimination result is caused due to the fact that the reference clock and the delay clock have errors when reaching the phase discriminator, so that the calibration effect is poor, and the stability of the full digital delay phase-locked loop is affected.

Disclosure of Invention

The application aims to provide an all-digital delay phase-locked loop circuit and a calibration method aiming at the defects in the prior art so as to reduce phase discrimination errors and improve calibration precision.

In order to achieve the above purpose, the technical scheme adopted by the embodiment of the application is as follows:

In a first aspect, an embodiment of the present application provides an all-digital delay locked loop circuit, the circuit including a frequency divider, a phase detector, a calibration logic circuit, and a digital delay line;

The input end of the frequency divider is used for receiving a reference clock signal, and the first output end of the frequency divider is connected with the input end of the numerical control delay line and is used for providing a reference pulse signal for the numerical control delay line;

the second output end of the frequency divider is connected with the first input end of the phase discriminator and is used for providing a phase discrimination sampling pulse signal for the phase discriminator, and the phase discrimination sampling pulse signal and the reference pulse signal are two frequency division signals of the reference clock signal;

The second input end of the phase discriminator is connected with the output end of the numerical control delay line and is used for receiving a delayed pulse signal after the numerical control delay line delays the reference pulse signal;

The output end of the phase discriminator is connected with the input end of the calibration logic circuit and is used for providing the phase discrimination results of the reference pulse signal and the delay pulse signal for the calibration logic circuit;

the output end of the calibration logic circuit is connected with the control end of the numerical control delay line and is used for calibrating the delay step length of the numerical control delay line according to the phase discrimination result so as to calibrate the delay of the delay pulse signal, and the delay step length indicates the number of effective delay units in the numerical control delay line.

Optionally, the third output end of the frequency divider is connected to the first control end of the calibration logic circuit, and is configured to provide a state machine update pulse signal for the calibration logic circuit, so that the calibration logic circuit updates a step direction and a step size based on the state machine update pulse signal, where the step direction is used to instruct to increase or decrease the delay step size, and the step size is used to instruct to increase or decrease the length of the delay step size;

The fourth output end of the frequency divider is connected with the second control end of the calibration logic circuit and is used for providing a step updating pulse signal for the calibration logic circuit so that the calibration logic circuit calibrates the delay step length of the numerical control delay line according to the step direction and the step length based on the step updating pulse signal.

Optionally, the circuit further comprises a result register, wherein the numerical control delay line comprises a reference numerical control delay line and an application numerical control delay line;

the output end of the calibration logic circuit is connected with the reference numerical control delay line;

the input end of the result register is connected with the output end of the phase discriminator and is used for storing the phase discrimination result so that preset calibration software reads the phase discrimination result from the result register and provides a calibration step length for the calibration logic circuit according to the phase discrimination result to calibrate the delay step length of the reference numerical control delay line according to the calibration step length;

And the preset calibration software is also used for calibrating the applied numerical control delay line according to the calibration step length when the phase discrimination result after the step length calibration is correct.

Optionally, the phase detector comprises a first trigger, a second trigger and a selector;

The input end of the first trigger is used as the second input end of the phase discriminator, the output end of the first trigger is connected with the first input end of the selector, the second input end of the selector is connected with the output end of the second trigger, the selection input end of the selector is used as the first input end of the phase discriminator, the output end of the selector is connected with the input end of the second trigger, and the output end of the second trigger is used as the output end of the phase discriminator.

The selection input end of the selector is used as a first input end of the phase discriminator, the first input end of the selector is used as a second input end of the phase discriminator, the second input end of the selector is connected with the output end of the first trigger, the output end of the selector is connected with the input end of the first trigger, the output end of the first trigger is also connected with the input end of the second trigger, and the output end of the second trigger is used as the output end of the phase discriminator.

Optionally, the digitally controlled delay line includes a first delay unit and a plurality of second delay units;

the first delay unit comprises a first buffer, a first NAND gate and second NAND gates, and each second delay unit comprises a second buffer, a third NAND gate and an AND gate;

the input end of the first buffer is used as the input end of the numerical control delay line, and the first buffer and the second buffers in the plurality of second delay units are sequentially connected in series;

the output end of the first buffer is connected with the first input end of the first NAND gate, the output end of the first NAND gate is connected with the first input end of the second NAND gate, and the output end of the second NAND gate is used as the output end of the numerical control delay line;

The second buffer in each second delay unit is connected with the first input end of a corresponding third NAND gate, and the output end of the third NAND gate is connected with the first input end of the corresponding AND gate;

The second input end of each AND gate is connected with the output end of the next AND gate, the second input end of the last AND gate is at a preset high level, and the output end of the first AND gate is connected with the second input end of the second NAND gate;

the second input end of the first NAND gate and the second input end of the third NAND gate are used as control ends of the numerical control delay line.

In a second aspect, an embodiment of the present application further provides a calibration method of an all-digital delay locked loop circuit, which is applied to the all-digital delay locked loop circuit according to any one of the first aspect, where the method includes:

sampling the delay pulse signal when the phase discrimination sampling pulse signal is effective to obtain a reference pulse signal and a phase discrimination result of the delay pulse signal;

Determining a delay step length of a numerical control delay line according to the phase discrimination result, the stepping direction and the stepping step length, wherein the stepping direction is used for indicating to increase or decrease the delay step length, and the stepping step length is used for indicating to increase or decrease the length of the delay step length;

And calibrating the numerical control delay line according to the delay step length so as to calibrate the delay of the delay pulse signal of the numerical control delay line, wherein the delay step length indicates the number of effective delay units in the numerical control delay line.

Optionally, the determining the delay step length of the numerical control delay line according to the phase discrimination result, the step direction and the step length includes:

judging whether the step change direction indicated by the phase discrimination result is consistent with the step direction or not;

Updating the stepping direction and the stepping step length according to the judging result;

And determining the delay step length according to the updated step direction and the target step length, wherein the target step length is the step length before updating or the step length after updating.

Optionally, the updating the step direction and the step size according to the determination result includes:

if the step change direction is consistent with the step direction, determining that the step direction and the step length are unchanged;

if the step change direction is inconsistent with the step direction, updating the step direction to be the opposite direction, reducing the step length, and determining the updated step length.

Optionally, the method further comprises:

Repeating updating the step direction and the step length for a plurality of times until the step length is equal to 1, updating the delay step length based on the step direction and the step length 1 updated last time until the step length change direction indicated by the phase discrimination result is overturned, and ending the calibration process.

Optionally, the method further comprises:

And adding a bias step length on the basis of the delay step length to serve as the delay step length.

The beneficial effects of the application are as follows:

the full digital delay phase-locked loop circuit and the calibration method provided by the application are characterized in that the frequency divider is used for dividing the frequency of the reference clock signal to generate the reference pulse signal and the phase-discrimination sampling pulse signal, the reference pulse signal is used as the input signal of the numerical control delay line, and the phase-discrimination sampling pulse signal is used for selecting the phase-discrimination sampling time of the delay pulse signal by the phase discriminator.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of an all-digital delay locked loop circuit according to an embodiment of the present application;

Fig. 2 is a schematic diagram two of an all-digital delay locked loop circuit according to an embodiment of the present application;

fig. 3 is a schematic diagram of a phase detector according to an embodiment of the present application;

Fig. 4 is a waveform diagram illustrating the operation of the phase detector according to the embodiment of the present application;

Fig. 5 is a schematic diagram ii of a phase detector according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a numerical control delay line according to an embodiment of the present application;

Fig. 7 is a flowchart illustrating a calibration method of an all-digital delay locked loop circuit according to an embodiment of the present application;

fig. 8 is a second flowchart of a calibration method of an all-digital delay locked loop circuit according to an embodiment of the present application;

FIG. 9 is an update schematic diagram of a state machine according to an embodiment of the present application;

fig. 10 is a waveform diagram of the calibration logic according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application.

Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Furthermore, the terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.

Fig. 1 is a schematic diagram of an all-digital delay locked loop circuit according to an embodiment of the present application, as shown in fig. 1, the all-digital delay locked loop circuit may include a frequency divider 10, a phase detector 20, a calibration logic 30, and a digital delay line 40.

The input end of the frequency divider 10 is used for receiving a reference clock signal, the first output end of the frequency divider 10 is connected with the input end of the numerical control delay line 40 and is used for providing a reference pulse signal for the numerical control delay line 40, the second output end of the frequency divider 10 is connected with the first input end of the phase detector 20 and is used for providing a phase detection sampling pulse signal for the phase detector 20, the phase detection sampling pulse signal and the reference pulse signal are two frequency division signals of the reference clock signal, the second input end of the phase detector 20 is connected with the output end of the numerical control delay line 40 and is used for receiving a delay pulse signal after the numerical control delay line 40 delays the reference pulse signal, the output end of the phase detector 20 is connected with the input end of the calibration logic circuit 30 and is used for providing a phase detection result of the reference pulse signal and the delay pulse signal for the calibration logic circuit 30, and the output end of the calibration logic circuit 30 is connected with the control end of the numerical control delay line 40 and is used for calibrating the delay step length of the numerical control delay line 40 according to the phase detection result so as to calibrate the delay of the delay pulse signal and the delay step length indicates the number of effective delay units in the numerical control delay line.

In this embodiment, the frequency divider 10 divides the reference clock signal to generate the reference pulse signal ref_tick and the phase-discrimination sampling pulse signal pd_upd, where the phase-discrimination sampling pulse signal pd_upd is behind the reference pulse signal ref_tick by a preset delay, and the preset delay is an effective delay of the digital delay line after the calibration of the all-digital delay phase-locked loop, that is, a delay length between the reference pulse signal ref_tick and the delayed pulse signal dll_tick obtained by the delay of the digital delay line by the reference pulse signal ref_tick, which is described by taking one clock cycle as an example in this embodiment.

The nc delay line 40 includes a plurality of delay units, and determines the delay units that are turned on in the data delay line 40 according to the delay step length of the nc delay line 40, wherein the number of effective delay units from the first delay unit of the nc delay line 40 to the turned on delay unit is equal to the delay step length of the nc delay line 40, and after the reference pulse signal ref_tic generated by the frequency divider 10 is delayed by the effective delay units in the nc delay line 40, the delayed reference pulse signal dll_tic is output.

The phase discriminator 20 is respectively input with a phase discrimination sampling pulse signal pd_upd and a delay pulse signal dll_tick, the phase discrimination sampling pulse signal pd_upd is used as the time sequence control of the phase discriminator 20, when the phase discrimination sampling pulse signal pd_upd is effective, the delay pulse signal dll_tick is sampled to obtain a synchronous signal pd_ rslt related to a reference pulse signal ref_tick and the delay pulse signal dll_tick, and the synchronous signal pd_ rslt is used as a phase discrimination result obtained by the phase discriminator 20 for phase discrimination of the reference pulse signal ref_tick and the delay pulse signal dll_tick.

The calibration logic 30 calibrates the delay steps of the digital control delay line 40 according to the synchronization signal pd_ rslt, generates a single thermal code according to the calibrated delay steps, and controls one delay unit in the digital control delay line 40 to be turned on according to the single thermal code to select the delay unit from the first delay unit to the turned on as a delay path.

In some embodiments, the calibration logic 30 needs to increase the delay step of the digitally controlled delay line 40 when the synchronization signal pd_ rslt indicates that the delay between the reference pulse signal ref_tick and the delay pulse signal dll_tick is small, and the calibration logic 30 needs to decrease the delay step of the digitally controlled delay line 40 when the synchronization signal pd_ rslt indicates that the delay between the reference pulse signal ref_tick and the delay pulse signal dll_tick is large.

According to the full-digital delay phase-locked loop circuit provided by the embodiment, the reference clock signal is divided by the frequency divider to generate the reference pulse signal and the phase-discrimination sampling pulse signal, the reference pulse signal is used as the input signal of the numerical control delay line, and the phase-discrimination sampling pulse signal is used for selecting the phase-discrimination sampling time of the delay pulse signal by the phase discriminator.

In one possible implementation, as shown in fig. 1, the third output terminal of the frequency divider 10 is connected to the first control terminal of the calibration logic 30, and is configured to provide a state machine update pulse signal to the calibration logic 30, so that the calibration logic 30 updates a step direction and a step size based on the state machine update pulse signal, the step direction is used to indicate increasing or decreasing the delay step size, the step size is used to indicate increasing or decreasing the length of the delay step size, and the fourth output terminal of the frequency divider 10 is connected to the second control terminal of the calibration logic 30, and is configured to provide a step size update pulse signal to the calibration logic 30, so that the calibration logic 30 calibrates the delay step size of the digitally controlled delay line 40 according to the step direction and the step size based on the step size update pulse signal.

In order to achieve high-precision PWM, since the frequency of the digital clock cannot be arbitrarily increased, it is necessary to adjust the high-level time of the original PWM using a digitally controlled delay line in order to improve the resolution of the PWM at high frequencies. The digital delay line is calibrated by using the full digital delay phase-locked loop circuit to obtain an operation code corresponding to the digital delay line in the current working environment, then the high-level time and the delay time of the digital delay line are calculated according to the duty ratio requirement of PWM, and the operation code of the digital delay line is adjusted, so that the controllable delay of the original PWM can be realized, and further the high-precision PWM is obtained.

Under high frequency working conditions, if the extension of the numerical control delay line is changed when the input signal is still transmitted in the numerical control delay line, unpredictable burrs are generated on the output delay signal, and the robustness of the circuit is weakened.

In this embodiment, in order to solve the problem that the extension of the digitally controlled delay line is changed while the input signal is still propagating in the digitally controlled delay line, the reference clock signal is divided by the frequency divider 10 to generate the state machine update pulse signal state_upd and the step update pulse signal step_upd.

The state machine of the calibration logic 30 has different operating states, representing different step directions and step sizes, and when the state machine update pulse signal state_upd is valid, the synchronization signal pd_ rslt output by the phase detector 20 is obtained, so that the step directions and step sizes of the state machine are updated according to the synchronization signal pd_ rslt. When the step update pulse signal step_upd is active, the delay step of the numerical control delay line 40 is updated according to the step direction and the step size.

In some embodiments, the timing relationship between the state machine update pulse signal state_upd and the step update pulse signal step_upd may be determined according to a predetermined step direction and step size, and the update sequence of the delay step size.

If the step direction and the step length are updated after each phase discrimination, and then the delay step length is updated according to the updated step direction and the step length, the time sequence of the state machine updating pulse signal state_upd is before the step length updating pulse signal step_upd, if the step direction is updated after each phase discrimination, the delay step length is updated according to the updated step direction and the original step length, the step length is updated again, the updated step length is updated after the next phase discrimination, the time sequence of the step length updating pulse signal step_upd is between the two time sequences of the state machine updating pulse signal state_upd, and if the step direction, the step length and the delay step length are updated synchronously after each phase discrimination, the state machine updating pulse signal state_upd and the step length updating pulse signal step_upd have the same time sequence.

In some embodiments, if the step direction indicates to increase the step size, the step size is increased on the basis of the current delay step size to obtain the calibrated delay step size, and if the step direction indicates to decrease the step size, the step size is subtracted on the basis of the current delay step size to obtain the calibrated delay step size.

In some embodiments, the frequency divider 10 counts eight frequency division clocks, which can be modified to any frequency division, and the clock of the state machine update pulse signal state_upd and the step update pulse signal step_upd may be set arbitrarily after the phase discrimination sampling pulse signal pd_upd and the reference pulse signal ref_tick are one clock period later than the reference pulse signal ref_tick, which only needs to be ensured in the inactive time of the phase discrimination sampling pulse signal pd_upd and the reference pulse signal ref_tick.

According to the all-digital delay phase-locked loop circuit provided by the embodiment, the state machine updating pulse signals and the step length updating pulse signals generated by the frequency divider control the calibration logic circuit to update the step direction, the step length and the delay step length, so that the delay step length of the digital delay line is calibrated when the digital delay line is not provided with the transmission of the reference pulse signals, the phenomenon of burrs is avoided, and the robustness of the all-digital delay phase-locked loop circuit is improved.

In one possible implementation, fig. 2 is a schematic diagram of an all-digital delay locked loop circuit according to an embodiment of the present application, and as shown in fig. 2, the all-digital delay locked loop circuit may further include a result register 50, and the nc delay line 40 includes a reference nc delay line 411 and an application nc delay line 412.

The output end of the calibration logic 30 is connected to the reference nc delay line 411, the input end of the result register 50 is connected to the output end of the phase discriminator 20, and is used for storing the phase discrimination result, so that the preset calibration software reads the phase discrimination result from the result register 50, provides a calibration step length for the calibration logic 30 according to the phase discrimination result, so as to calibrate the delay step length of the reference nc delay line 411 according to the calibration step length, and is also used for applying the nc delay line 412 according to the calibration step length when the phase discrimination result after the step length calibration is correct.

In this embodiment, in order to enable the all-digital delay locked loop circuit to support the software calibration function, a result register 50 is added in the all-digital delay locked loop circuit, the result register 50 is connected with the output end of the phase discriminator 20, so that when the phase discriminator 20 outputs a phase discrimination result, the phase discrimination result is stored in the result register 50, the phase discrimination result is changed only when the phase discrimination sampling pulse signal pd_upd is valid, and is synchronous with the system clock, the synchronous signal remains unchanged after the calibration is completed, the preset calibration software can read the phase discrimination result from the result register 50, and directly configure the calibration step size sw_step at any moment, the calibration logic circuit 30 generates a unique hot code at a proper moment according to the calibration step size sw_step, controls a delay unit in the numerical control delay line according to the unique hot code, so as to update the delay step size of the numerical control delay line 40, no burr signal is generated, and then the preset calibration software reads the new phase discrimination result in the result register 50, and judges whether the delay step size of the numerical control delay line 40 is proper according to the phase discrimination result, thereby realizing the software calibration.

Further, the nc delay line 40 is set as the reference nc delay line 411 and the application nc delay line 412, after the calibration of the reference nc delay line 411 by the preset calibration software is completed, the calibration step length for calibrating the reference nc delay line 411 is used as the ideal step length for the application nc delay line 412, and the application nc delay line 412 after the calibration can be used for clock compensation, phase adjustment, and other functions without separately calibrating the application nc delay line 412.

In some embodiments, the number of the digitally controlled delay lines 412 may be set according to practical application requirements, which is not limited in this embodiment.

The full digital delay phase-locked loop circuit provided by the embodiment uses one full digital delay phase-locked loop and a plurality of digital control delay lines to form a minimum system, and each digital control delay line is not required to be calibrated by setting the full digital delay phase-locked loop for each digital control delay line, so that the circuit area is reduced, and the calibration efficiency is improved.

In one possible implementation, fig. 3 is a schematic diagram of a phase detector according to an embodiment of the present application, and as shown in fig. 3, the phase detector 20 includes a first flip-flop 211, a second flip-flop 212, and a selector 213.

The input end of the first trigger 211 is used as the second input end of the phase detector 20, the output end of the first trigger 211 is connected with the first input end of the selector 213, the second input end of the selector 213 is connected with the output end of the second trigger 212, the selection input end of the selector 213 is used as the first input end of the phase detector 20, the output end of the selector 213 is connected with the input end of the second trigger 212, and the output end of the second trigger 212 is used as the output end of the phase detector 20.

As shown in fig. 3 and 4, the clock end of the first flip-flop 211 and the clock end of the second flip-flop 212 are used for receiving the system clock signal sys_clk, the input end of the first flip-flop 211 inputs the delayed pulse signal dll_tick, the first flip-flop 211 continuously samples the delayed pulse signal dll_tick at the rising edge of each system clock signal sys_clk to obtain the asynchronous signal pd_ rslt _pre, one input end of the selector 213 is connected to the output end of the first flip-flop 211 and receives the asynchronous signal pd_ rslt _pre, the other input end of the selector 213 is connected to the output end of the second flip-flop 212 and receives the output signal, and the selection input end of the selector 213 receives the phase discrimination sampling pulse signal pd_upd and selects the sampling asynchronous signal pd_ rslt _pre or the output signal according to the phase discrimination sampling pulse signal pd_upd.

The second flip-flop 212 samples the output signal of the second flip-flop 21 when the phase-discriminating sampling pulse signal pd_upd is not valid, and samples the asynchronous signal pd_ rslt _pre when the phase-discriminating sampling pulse signal pd_upd is valid, i.e. the second flip-flop 212 samples the asynchronous signal pd_ rslt _pre only when the phase-discriminating sampling pulse signal pd_upd is valid, and keeps the current value unchanged at other moments, resulting in the synchronous signal pd_ rslt as a phase-discriminating result.

In another possible implementation manner, fig. 5 is a schematic diagram two of a phase detector according to an embodiment of the present application, and as shown in fig. 5, the phase detector 20 includes a first flip-flop 211, a second flip-flop 212, and a selector 213.

The selection input terminal of the selector 213 is used as the first input terminal of the phase detector 20, the first input terminal of the selector 213 is used as the second input terminal of the phase detector 20, the second input terminal of the selector 213 is connected with the output terminal of the first trigger 211, the output terminal of the selector 213 is connected with the input terminal of the first trigger 211, the output terminal of the first trigger 211 is also connected with the input terminal of the second trigger 212, and the output terminal of the second trigger 212 is used as the output terminal of the phase detector 20.

In this embodiment, one input terminal of the selector 213 is connected to the output terminal of the first flip-flop 211, receives the output signal of the first flip-flop 211, the other input terminal of the selector 213 receives the delayed pulse signal dll_tick, the selection input terminal of the selector 213 receives the phase discrimination sampling pulse signal pd_upd, and the output terminal of the selector 213 is connected to the input terminal of the first flip-flop 211, so that the first flip-flop 211 samples the delayed pulse signal dll_tick only when the phase discrimination sampling pulse signal pd_upd is valid, and keeps the current value unchanged at other moments, and the second flip-flop 212 is connected to the output terminal of the first flip-flop 211, and continuously samples the output signal of the first flip-flop 211 at the rising edge of each system clock signal sys_clk to obtain the synchronization signal pd_ rslt.

Furthermore, more flip-flops may be added to the phase detector according to timing requirements, which is not limited in this embodiment.

In one possible implementation, fig. 6 is a schematic diagram of a digitally controlled delay line according to an embodiment of the present application, and as shown in fig. 6, the digitally controlled delay line 40 includes a first delay unit 401 and a plurality of second delay units 402.

The first delay unit 401 comprises a first buffer buf_1, a first nand gate nand_1 and a second nand gate nand_2, each second delay unit 402 comprises a second buffer buf_2, a third nand gate nand_3 and an and gate, the input end of the first buffer buf_1 is used as the input end of the numerical control delay line 40, the first buffer buf_1 and the second buffers buf_2 in the plurality of second delay units 402 are sequentially connected in series, the output end of the first buffer buf_1 is connected with the first input end of the first nand gate nand_1, the output end of the first nand gate nand_1 is connected with the first input end of the second nand gate nand_2, the output end of the second nand gate nand_2 is used as the output end of the numerical control delay line 40, the second buffer buf_2 in each second delay unit 402 is connected with the first input end of the corresponding third nand gate nand_3, the output end of the third buffer buf_3 and the output end of the second buffer buf_2 in the corresponding second delay unit 402 is connected with the first input end of the first nand gate nand_2, the output end of the second nand gate nand_2 is connected with the first input end of the first nand gate nand_2, and the output end of the second nand gate nand_2 is connected with the first input end of the second nand gate.

In this embodiment, as shown in fig. 6, the specific connection relationship between the first delay unit 401 and the second delay unit 402 is that the second input terminal of the first nand gate nand_1 in the first delay unit 401 and the second input terminal of the third nand gate nand_3 in the second delay unit 402 are used for receiving the enable signal to control the conduction condition of the corresponding delay unit, and the unique thermal code generated by the calibration logic circuit 30 controls the conduction of one delay unit of the first delay unit 401 and the plurality of second delay units 402.

In the second delay unit 402, the third nand gate nand_3 is a fixed delay on the delay path, the second buffer buf_2 and the gate and is an effective delay on the delay path, and when the enable signal of one delay unit is 1 and the enable signals of other delay units are 0, the length of the digital control delay line 40 is the delay path from the first delay unit to the delay unit with the enable signal of 1.

The delay calculation formula of the numerical control delay line can be expressed as:

T = m × (t_{buf_2}+ t_and) + t_{buf_1}+ t_{nand_1}+ t_{nand_2}(m>0)

T = t_{buf_1}+ t_{nand_1}+ t_{nand_2}(m=0)

Wherein m is the number of effective delay units in the digitally controlled delay line.

In some embodiments, the sum of the delays of the first buffer buf_1, the first nand gate nand_1 and the second nand gate nand_2 is approximately equal to the sum of the second buffer buf_2 and the and gate nd, so that the linearity of the digital control delay line can be improved, and the delay calculation formula can be expressed as t= (m+1) x (T _{buf_2}+ t_and).

In some embodiments, the structure of the digital control delay line is not limited to the above structure, and the buffer, the nand gate and the and gate can be replaced by other devices without changing the logic, which only needs to ensure that the output logic is the same. The buffer has only a delay function and no logic function, so that a large change, such as replacement with two inverters, can be performed, which is not limited in this embodiment.

According to the all-digital delay phase-locked loop circuit provided by the embodiment, the delays of all delay units in the numerical control delay line are approximately equal, the linearity of the numerical control delay line is improved, and the thermal single-code control mechanism is adopted to facilitate the calibration of control logic and the setting of any delay time.

Based on the all-digital delay phase-locked loop circuit provided by the embodiment, the embodiment of the application also provides a calibration method applied to the all-digital delay phase-locked loop circuit. Fig. 7 is a flowchart of a calibration method of an all-digital delay locked loop circuit according to an embodiment of the present application, as shown in fig. 7, the method may include:

S101, when the phase discrimination sampling pulse signal is effective, sampling the delay pulse signal to obtain a reference pulse signal and a phase discrimination result of the delay pulse signal.

In this embodiment, the phase discriminator samples the delayed pulse signal dll_tick when the phase discriminating sampling pulse signal pd_upd is valid, so as to obtain a phase discriminating result which can characterize the phase delay relationship between the reference pulse signal ref_tick and the delayed pulse signal dll_tick.

In some embodiments, the phase discrimination result is 1, which indicates that the phase delays of the reference pulse signal ref_tick and the delayed pulse signal dll_tick are smaller than the preset delay, and the phase discrimination result is 0, which indicates that the phase delays of the reference pulse signal ref_tick and the delayed pulse signal dll_tick are larger than the preset delay.

S102, determining the delay step length of the numerical control delay line according to the phase discrimination result, the stepping direction and the stepping step length, wherein the stepping direction is used for indicating to increase or decrease the delay step length, and the stepping step length is used for indicating to increase or decrease the length of the delay step length.

In this embodiment, the calibration logic determines the step direction according to the phase discrimination result, and adjusts the current step length of the numerical control delay line according to the step length in the step direction on the basis of the current step length of the numerical control delay line, thereby obtaining the delay step length of the numerical control delay line.

In some embodiments, if the phase discrimination result is 1, the phase delay needs to be increased, the stepping direction is determined to be increased, the stepping step length is increased on the basis of the current step length of the numerical control delay line, so as to obtain the delay step length, if the phase discrimination result is 0, the phase delay needs to be reduced, the stepping direction is determined to be reduced, and the stepping step length is reduced on the basis of the current step length of the numerical control delay line, so as to obtain the delay step length.

And S103, calibrating the numerical control delay line according to the delay step length so as to calibrate the delay of the delay pulse signal of the numerical control delay line, wherein the delay step length indicates the number of effective delay units in the numerical control delay line.

In this embodiment, the calibration logic generates a single thermal code according to the calculated delay step length, and sends the single thermal code to the digital control delay line, so that one delay unit on the digital control delay line is turned on, the number of the effective delay units is equal to the delay step length from the first delay unit to the turned-on delay unit of the digital control delay line, and the digital control delay line delays the reference pulse signal ref_tick based on the effective delay unit, so as to obtain a delay pulse signal dll_tick after phase delay is calibrated.

According to the calibration method of the all-digital delay phase-locked loop circuit, which is provided by the embodiment, the delay step length of the digital delay line is calibrated based on the stepping direction and the stepping step length, so that the calibration time can be effectively shortened, and the calibration accuracy is improved.

In a possible implementation manner, fig. 8 is a second flowchart of a calibration method of an all-digital delay locked loop circuit according to an embodiment of the present application, as shown in fig. 8, a process of determining a delay step of a digital delay line according to a phase discrimination result, a step direction and a step size in S102 may include:

s201, judging whether the step change direction indicated by the phase discrimination result is consistent with the step direction.

S202, updating the stepping direction and the stepping step length according to the judging result.

S203, determining a delay step according to the updated step direction and a target step, wherein the target step is a step before update or a step after update.

In some embodiments, the step 202 updates the step direction and the step length according to the determination result, which may include determining that the step direction and the step length are unchanged if the step length change direction is consistent with the step direction, and updating the step direction to be the opposite direction if the step length change direction is inconsistent with the step length, reducing the step length, and determining the updated step length.

In this embodiment, it is determined whether the step change direction indicated by the phase discrimination result is consistent with the current step direction, if so, the step change direction and the step length are not required to be changed, if not, the step change direction is required to be changed, and the step length is reduced. In some embodiments, each time the step size is reduced, it may be reduced by a preset ratio.

For example, if the phase discrimination result is 1, that is, the delay is smaller, the step change direction is increased, if the current step direction is also increased, both the step direction and the step length remain unchanged, if the current step direction is decreased, the step direction is updated to be increased, and the step length is reduced by a preset proportion.

If the phase discrimination result is 0, namely the delay is larger, the step change direction is reduced, if the current step direction is also reduced, the step direction and the step length are both kept unchanged, if the current step direction is increased, the step direction is updated to be reduced, and the step length is reduced by a preset proportion.

After updating the step length, the delay step length of the numerical control delay line can be calibrated according to the updated step length, or the delay step length of the numerical control delay line can be calibrated according to the step length before updating, and the updated step length is used for calibrating the delay step length after the next phase discrimination result comes out.

In one possible implementation, the method may further include repeating updating the step direction and the step size a plurality of times until the step size is equal to 1, ending the calibration process.

In this embodiment, since the step length needs to be reduced when the step length change direction is inconsistent with the step length direction in each calibration process, when the step length is reduced to 1 in the process of repeated calibration, the delay step length is updated based on the step length 1 and the step length direction updated last time until the step length change direction indicated by the phase discrimination result is inverted, and the calibration is determined to be completed.

In this embodiment, after the step size is reduced to 1, calibration is continued based on the step direction and the step size 1 until the phase detection result is turned over, that is, when the step size change direction indicated by the phase detection result is inconsistent with the step direction, it is determined that calibration is completed. Specifically, if the step change direction indicated by the phase discrimination result is consistent with the step direction, calibrating the delay step based on the step direction and the step length 1 until the step change direction indicated by the phase discrimination result is inconsistent with the step direction, namely waiting for the phase discrimination result to overturn, so that the delay step length of the digital control delay line reaches a critical point, ending the calibration process, and adjusting the delay step length of the digital control delay line to be one delay unit smaller than the system clock period.

The following exemplarily describes a delay step of calibrating the numerical control delay line according to the updated step size.

Fig. 9 is an update schematic diagram of a state machine provided by an embodiment of the present application, and fig. 10 is a working waveform diagram of a calibration logic circuit provided by an embodiment of the present application, as shown in fig. 9 and fig. 10, a reference clock signal in the embodiment is 5ns, a digital control delay line contains 64 delay units, delay time of each delay unit is 150ps, an initial delay step length of the digital control delay line is set to 27 after the calibration logic circuit is reset, a step direction is set to increase, and a step length is set to 27, namely 27 delay units are added each time. Reasonable stepping step length is set according to the number of delay units in the numerical control delay line, so that deadlock phenomenon in the stepping search process can be avoided.

Wherein dll_en is an enable signal of the all-digital delay phase-locked loop circuit, when the enable signal is 0, the state opportunity in the calibration logic circuit is reset to an IDLE state, pd_ rslt is a synchronous signal corresponding to a phase discrimination result, state_upd is a state machine update pulse signal, cali_sts is a stepping state of the state machine and comprises a stepping direction and a stepping step length, step_upd is a step length update pulse signal, and cali_step is a delay step length of the digital control delay line.

When the phase discrimination result of the phase discriminator is valid, the calibration logic reads the phase discrimination result, and as shown in fig. 10, the step change direction indicated by the first phase discrimination result is identical to the step direction, the step direction and the step size are not changed, the step direction is still Increased (INC), the step size is still 27, the step size 27 is increased on the basis of the initial delay size 27, and the calibrated delay size is 54.

And if the step change direction indicated by the second phase discrimination result is inconsistent with the step direction, updating the step direction to be reduced (DEC), reducing the step size by one third, namely updating the step size to be 9, and subtracting the step size 9 on the basis of the delay step size 54 to obtain the calibrated delay step size 45.

The step change direction indicated by the third phase discrimination result is consistent with the step direction, the step direction is still reduced (DEC), the step size is still 9, and the step size 9 is subtracted on the basis of the delay step size 45, so as to obtain a calibrated delay step size 36.

And if the step change direction indicated by the fourth phase discrimination result is inconsistent with the step direction, updating the step direction to be Increased (INC), reducing the step size by one third, namely updating the step size to be 3, and adding the step size 3 on the basis of the delay step size 36 to obtain the calibrated delay step size 39.

The step change direction indicated by the fifth phase discrimination result is consistent with the step direction, the step direction is still Increased (INC), the step size is still 3, and the step size 3 is added on the basis of the delay step size 36, so as to obtain the calibrated delay step size 42.

And if the step change direction indicated by the sixth phase discrimination result is inconsistent with the step direction, updating the step direction to be reduced (DEC), reducing the step size by one third, namely updating the step size to be 1, and subtracting the step size 1 on the basis of the delay step size 42 to obtain the calibrated delay step size 41.

The step change direction indicated by the seventh phase discrimination result is consistent with the step direction, the step direction is still reduced (DEC), the step size is still 1, and the step size 1 is subtracted on the basis of the delay step size 41, so as to obtain the calibrated delay step size 40.

The step change direction indicated by the seventh phase discrimination result is inconsistent with the step direction, namely after the step length is equal to 1, the step length is reduced twice, the phase discrimination result is overturned, and the calibration process is finished (DONE).

It can be seen that when the delay step is equal to 41, the delay time is less than the preset delay, and when the step is equal to 40, the delay time is greater than the preset delay, and it is determined that the delay step of the numerical control delay line has reached the critical point, and the calibration process is ended.

It should be noted that, in order to avoid the situation that the value of the step size of the state machine increases, and the delay step size exceeds the number of delay units, it is necessary to change the step direction and the step size if the delay step size adjusted based on the current step direction and the step size exceeds the number of delay units.

In some embodiments, the state machine has a plurality of step states, each step state is composed of a step direction and a step size, the step directions are sequentially alternated, the step sizes are sequentially reduced, if the delay step size adjusted based on the current step direction and the step size exceeds the number of delay units, a step state which is consistent with the current step direction and is not exceeding the number of delay units is selected from the plurality of step states, or a step state which is opposite to the current step direction and is smaller than the current step size is selected from the plurality of step states.

And selecting a stepping state which is opposite to the current stepping direction and has a smaller stepping step length than the current stepping step length if the smaller stepping step length is not available in the current stepping direction.

As shown in fig. 9, the initial step state is INC27, when the step change direction indicated by the phase discrimination result is consistent with the step direction, the delay step needs to be continuously increased, the delay step is increased from 27 to 54, if the step change direction indicated by the phase discrimination result is still consistent with the step direction when the delay step is 54, the delay step cannot be increased from 54 to 81 (the number of delay units is 64), and the step state INC27 makes the delay step of the digital delay line reach the maximum value 54 (dll_length/32×27), so that the step state is skipped to INC3. When the stepping state is INC3, if the step change direction indicated by the phase discrimination result is still consistent with the stepping direction in the case that the delay step reaches 63 (DLL_Length-1), the stepping state is jumped to DEC1.

In one possible embodiment, the method may further comprise:

And adding a bias step length on the basis of the delay step length to serve as a delay step length.

In this embodiment, after the step size is equal to 1, the calibration is continued to wait for the phase discrimination result to overturn, so as to obtain a final delay step size, and the phase discrimination result of the phase discriminator has deviation due to the existence of the setup time, so that the obtained calibration result is actually smaller, and when the state machine jumps to the DONE stage, the delay step size cali_step is corrected by adopting the offset dll_ prd _ofst on the basis of the delay step size cali_step, so as to compensate the influence caused by the setup time of the trigger in the phase discriminator, and thus the final delay step size is obtained.

Compared with the calibration method directly adopting fixed step length, the calibration method of the full digital delay phase-locked loop circuit provided by the embodiment shortens the calibration time, ensures the calibration precision, increases the step length on the configurable initial step length relative to the successive approximation algorithm such as the dichotomy and the like, and can avoid the deadlock phenomenon. The adaptability of the step search and the numerical control delay line controlled by the single thermal code is good, the logic conversion problem in successive approximation is not needed to be considered, the step length of the step search algorithm can be flexibly configured, and the method is also suitable for different situations.

Furthermore, the offset step length is added as the final delay step length on the basis of the delay step length, which is equivalent to adding the offset in the phase discrimination result, reducing the error of the phase discriminator and improving the phase discrimination precision.

The foregoing is merely illustrative of embodiments of the present application, and the present application is not limited thereto, and any changes or substitutions can be easily made by those skilled in the art within the technical scope of the present application, and the present application is intended to be covered by the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims

1. The all-digital delay phase-locked loop circuit is characterized by comprising a frequency divider, a phase discriminator, a calibration logic circuit and a digital control delay line;

2. The all-digital delay locked loop circuit of claim 1, wherein a third output of the frequency divider is connected to a first control terminal of the calibration logic circuit, and is configured to provide a state machine update pulse signal to the calibration logic circuit, such that the calibration logic circuit updates a step direction and a step size based on the state machine update pulse signal, the step direction being used to indicate an increase or decrease in the delay size, and the step size being used to indicate an increase or decrease in the length of the delay size;

3. The all-digital delay locked loop circuit of claim 1, further comprising a result register, wherein the digital delay line comprises a reference digital delay line and an application digital delay line;

4. The all-digital delay locked loop circuit of claim 1, wherein the phase detector comprises a first flip-flop, a second flip-flop, and a selector;

5. The all-digital delay locked loop circuit of claim 1, wherein the phase detector comprises a first flip-flop, a second flip-flop, and a selector;

6. The all-digital delay locked loop circuit of claim 1, wherein the digitally controlled delay line comprises a first delay cell and a plurality of second delay cells;

7. A method for calibrating an all-digital delay locked loop circuit, applied to the all-digital delay locked loop circuit as claimed in any one of claims 1 to 6, the method comprising:

8. The method of calibrating according to claim 7, wherein determining the delay step of the numerical control delay line according to the phase discrimination result and the step direction and step size comprises:

9. The method of calibrating according to claim 8, wherein updating the step direction and the step size according to the determination result includes:

10. The method of calibrating according to claim 9, wherein the method further comprises:

11. The method of calibrating according to claim 8, wherein the method further comprises: