JP2012114716A - Tdc device and method of calibrating tdc - Google Patents

Abstract

Provided is a TDC capable of realizing linearity while maintaining constant conversion characteristics of TDC with respect to variations in delay time of delay elements.
A delay line having a plurality of stages of delay elements 11 _{1 to} 11 _N for sequentially delaying a first signal DATA, and a plurality of samples for sampling outputs of the plurality of stages of delay elements in response to a second signal CLK. Flip-flops 12 _{1 to} 12 _N and an edge detector 13 for detecting an edge position at which output results of adjacent flip-flops are switched as a phase difference of the first signal with respect to the second signal. A calibration control circuit 15 for generating a control code ICNT for bias control based on the detection result of the above, and a bias generation circuit 14 for supplying to a plurality of delay elements corresponding to the control code. performing the delay elements of the stages corresponding to the frequency range, the calibration of the delay time of the delay element 11 ₁ to 11 _N such that the edge of the first signal is located
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, and relates to a TDC (Time-to-Digital Converter) and a calibration method.

  A digital PLL (Phase Locked Loop) is a phase-locked loop that digitizes each block of the analog PLL and digitizes the processing. The digital PLL has advantages such as solving a problem such as a circuit area of the loop filter which has been a problem in the analog PLL, facilitating redesign when changing the parameters of the PLL, and suppressing circuit characteristic fluctuation.

  A digital PLL such as an ADPLL (All Digital PLL) is a TDC that measures a phase difference between a reference clock FREF and an output CKV of a Digitally Controlled Oscillator (DCO), and a phase difference measured by the TDC (usually a reference clock) A phase error calculation unit that calculates a phase error based on a phase difference of a fraction in one cycle) and a phase difference of an integer part (a phase difference of one or more cycles of the reference clock), and smoothes the phase error from the phase error calculation unit And a DCO whose frequency is variable by the output of the digital filter. For the digital PLL, for example, Patent Document 1 is referred to. FIG. 8 is a citation of FIG. 1 of the all-digital PLL disclosed in Patent Document 1. In FIG. 8, 100 is an all-digital PLL, 102 is an accumulator, 103 is a numerically controlled oscillator (NCO), 104 is a dVCO (digitally controlled voltage controlled oscillator), 105 is a gain (GAIN) element, and 106 is a Schmitt trigger. Waveform shaper such as a circuit (converts a sine wave of the dVCO 104 into a binary digital signal), 108 is a ceiling element, 110 is a reference crystal oscillator (FREF: reference clock), 112 is a frequency reference clock CKR, and 114 is a dVCO 104 Clock signal CKV, 116 is a frequency control word (FCW), 120 is a latch / register, 200 is a small phase detector / small phase detector system, and 201 is a TDC. The phase error of the reference clocks FREF and CKV (output of the waveform shaper 106) is detected by the TDC 201, smoothed by the digital filter, and input to the DCO. The small phase detector 200 corrects the quantization error of the integer phase locked loop (refer to Patent Document 1 for details).

  FIG. 9 is a diagram illustrating a configuration example of the TDC 201 illustrated in FIG. In addition, FIG. 9 quotes FIG. 5 of patent document 1. FIG. Referring to FIG. 9, the TDC receives the output CKV of the DCO and the reference clock FREF, the phase difference TDC_RISE with respect to the rising transition of FREF at the rising transition of CKV, and the phase difference with respect to the rising transition of FREF at the falling transition of CKV. TDC_FALL is output. As shown in FIG. 9, the TDC is composed of a delay element (buffer or inverter) and a flip-flop, and the delay elements are connected in series to form a delay line. The TDC outputs a minute phase difference between signals between CKV and FREF as a digital value. Since the TDC measures the phase difference within one period of the output clock CKV, the TDC only includes the number of delay elements and latch circuits (flip-flops) corresponding to the length capable of measuring one period of the CKV. It is enough.

  FIG. 10 is a diagram illustrating an example of the timing operation of the TDC in FIG. 9. In FIG. 9, the number of delay elements is 10 (L = 10). FIG. 10 is a quotation of FIG. In the TDC, the signals D (0) to D (9) obtained by gradually delaying the output CKV of the DCO with L delay elements are sampled simultaneously at the rising edge of the reference clock signal FREF at each time FF, and D For example, “0011110000” is obtained as 10-bit sampling data Q (0) to Q (9) (Q [0: 9]) of (0) to D (9). An edge detector (also referred to as an “encoder”) detects a location where the value changes from 0 to 1 and a location where the value changes from 1 to 0 in the sampling data Q (0) to Q (9). The phase difference between the rising edge and the falling edge of the output clock CKV with respect to the rising edge (timing t1) of the reference clock FREF can be expressed by the number of delay elements. In this case, a part Q [6] where the value changes from 1 to 0 in Q [0: 9] becomes the rising information (Q [2-5] is 1 and Q [6] is 0. Become). Further, the point Q [2] where the value changes from 1 to 0 becomes falling information (Q [6-9], Q [0-1] is 0, and Q [2] is 1). Are output as digital data TDC_RISE and TDC_FALL, respectively. That is, the rising edge of the output clock CKV by TDC is advanced in phase by six delay elements in the TDC with respect to the rising edge of FREF, and the falling edge of the output clock CKV is the delay element 2 in the TDC with respect to the rising edge of FREF. It is measured that the phase is advanced by the step. In FIG. 9, since the delay element is composed of an inverter (inversion buffer), CKV and D (0), outputs D (0) and D (1) of adjacent delay elements, D (1) and D ( 2),... Are out of phase with each other, but in FIG. 10, D (0), D (1), D (2),... D (9) are signals in phase with CKV for the sake of clarity. It is expressed as

  Recently, with the progress of semiconductor process miniaturization technology, PVT (process, voltage, temperature: process variation in manufacturing, power supply voltage, temperature at the time of product use) fluctuations, digital delay elements (buffers, inverters, etc.) The delay time varies. When the delay time of the delay element fluctuates, the characteristics such as the measurement accuracy of the TDC phase difference are degraded. For this reason, it is necessary to correct the delay time so that the TDC can operate normally under any condition.

  In Patent Document 2, a clock signal is input to a variable delay line and delayed, the phase difference between the clock signal input to the variable delay line and the output clock (delay signal) of the variable delay line is compared, and the phase difference is compared. When the delay time is large, a configuration is disclosed in which a control voltage corresponding to the phase difference is supplied to the delay element of the variable delay line to reduce the delay time so as to reduce the delay of the variable delay line. In this Patent Document 2, based on the phase difference between the input and output of the variable delay line, delay elements (current source transistors connected between the CMOS inverter and the high-side power supply and the low-side power supply, respectively) constituting each stage of the variable delay line. A configuration including a bias generation circuit for controlling a bias voltage supplied to a current source (having a power source) is disclosed.

Japanese Patent Laid-Open No. 2002-76886 (FIGS. 1, 5, and 6) JP 2007-221598 A

  An analysis of related technologies is given below.

  As described above, it is necessary to adjust the phase difference measurement range of the TDC by correcting the delay time of the delay element in the TDC so that the TDC can operate normally with respect to PVT fluctuation or the like.

  By the way, without correcting the delay time of the delay elements in the TDC, in the TDC, the delay elements having the number of stages corresponding to the delay time of one cycle or more of the signal to be measured are considered in advance in consideration of delay variation. There is also a method in which a phase difference can be normally measured even if the delay time of the delay element varies. However, by increasing the number of TDC delay elements in this way, the phase difference measurement range is expanded to cover a wide frequency range, resulting in an increase in circuit area and power consumption. For example, in TDC, when the signal frequency to be measured is twice the preset phase difference measurement range, delay elements having a number of stages more than twice the number of set stages are required.

  Furthermore, in a semiconductor device manufactured by a state-of-the-art process, due to fluctuations in transistor threshold, power supply voltage, and temperature, the amount of variation in delay time of the delay element of the TDC is at the upper and lower limits of the variation range, for example There may be several times as many screens.

  Due to variations in the delay time of the delay elements, there may be a case where the number of TDC delay elements is insufficient with respect to the phase difference to be measured, and in the worst case, the TDC may not operate. As an example, in FIG. 9, the delay time of the delay elements in the TDC is shortened (in FIG. 10, CKV and outputs D (0), D (0), D (1)... D ( 8) and the rise time interval of D (9) is shortened), the number of TDC delay elements is insufficient for the phase difference to be measured, and the phase difference between the rising edge of CKV and the rising edge of FREF When the total delay time of the delay elements exceeds the high pulses (rising and falling edges) of the delay outputs D (0) to D (9) in FIG. 10, all are positioned before the rising timing t1 of FREF. Therefore, the sample results Q (0) to Q (9) of each FF at the rising timing t1 of FREF are all zero.

  Therefore, it is necessary to control the delay time so that the phase difference can be normally measured even when the delay time of the delay element of the TDC varies. In addition, as a countermeasure against variations in delay time of delay elements in TDC, it is desired to suppress an increase in circuit area and power consumption.

  In order to solve at least one of the above-mentioned problems, the present invention has the following general configuration although it is not particularly limited.

According to the present invention, a delay line having a plurality of stages of delay elements that sequentially delay the first signal;
A plurality of flip-flops respectively arranged corresponding to the plurality of stages of delay elements and sampling the output of the plurality of stages of delay elements in response to an input second signal;
An edge detector for inputting an output of the plurality of flip-flops and detecting an edge position at which an output result of adjacent flip-flops is switched as a phase difference between the first signal and the second signal;
A TDC (Time-to-Digital Converter) device comprising:
The delay element includes a current source in a power supply path, and varies a delay time according to a bias applied to the current source,
A calibration control circuit that generates a control code for bias control based on the detection result of the edge position;
A bias generation circuit that generates a bias corresponding to the control code from the calibration control circuit and supplies the bias to the plurality of stages of delay elements;
With
At the time of calibration, in the calibration control circuit, the position of the edge detected by the edge detector corresponds to the number of stages of delay elements set in advance corresponding to the frequency range of the first signal. In addition, a TDC apparatus is provided that performs calibration of the delay time of the delay element by controlling the bias generation circuit.

According to the present invention, a delay line having a plurality of stages of delay elements that sequentially delay the first signal, and a second signal that is arranged corresponding to each of the plurality of stages of delay elements and is commonly input. A plurality of flip-flops that sample the outputs of the delay elements of the plurality of stages in response and the outputs of the plurality of flip-flops are input, and the edge position where the output results of adjacent flip-flops are switched is the first signal. A TDC (Time-to-Digital Converter) calibration method comprising: an edge detector that detects a phase difference with respect to the second signal of
The delay element includes a current source in a power supply path, and a delay time can be varied according to a bias applied to the current source.
A calibration control circuit generates a control code for bias control based on the edge detection result,
A bias corresponding to the control code is generated by a bias generation circuit, supplied to the plurality of stages of delay elements, and the edge position detected by the edge detector is in the frequency range of the first signal. Correspondingly, there is provided a TDC calibration method for calibrating the delay time of the delay element so as to correspond to a preset number of stages of delay elements.

  According to the present invention, even when the delay time of the delay element of the TDC varies, it is possible to achieve linearity by making the conversion characteristics of the TDC constant while suppressing an increase in circuit area and power consumption. .

It is a figure which shows the structure of one Embodiment of this invention. It is a timing chart of one embodiment of the present invention. Input phase difference vs. It is a figure which shows an example of a TDC output code. It is a figure which shows the structure of the delay element of one Embodiment of this invention. It is a figure explaining the delay time setting per stage in one embodiment of the present invention. It is a flowchart explaining the calibration procedure in one Embodiment of this invention. It is a figure explaining a frequency range and the setting stage number. It is a figure which shows ADPLL of patent document 1. FIG. It is a figure which shows the structural example of TDC of FIG. It is a figure explaining operation | movement of TDC of FIG.

  Embodiments of the present invention will be described below. According to the present invention, by controlling the bias applied to the current source of the delay element of the TDC, the phase difference of the predetermined frequency band can be set to the predetermined delay element with respect to the variation in delay of the delay element of the TDC. Control is performed so that measurement is performed within the range of the number of stages, and control is performed so that the conversion characteristics of the TDC are linear (constant) with respect to delay variations of the delay elements.

According to one of the preferred embodiments of the present invention, the delay line (10) including a plurality of delay elements (11 _{1 to} 11 _N ) for sequentially delaying the first signal (DATA) is provided, and the delay element of each stage Provides a current source in the power supply path and varies the delay time according to the bias applied to the current source. Wherein each disposed corresponding to the plurality of stages of delay elements ₍₁₁ 1 _{~11 N),} the delay element of the plurality of stages in response to a second signal input (CLK) of ₍₁₁ 1 _{~11 N)} a plurality of flip-flops for sampling the output ₍₁₂ 1 _{~12 N),} receiving the output of said plurality of flip-flops ₍₁₂ 1 _{~12 N),} the edge positions switched output of Aitonaru flip-flop, the An edge detector (13) that detects a phase difference between the first signal and the second signal, and a calibration control circuit (15) that generates a control code (ICNT) for bias control based on the detection result of the edge If, generates a bias corresponding to the control code from the calibration control circuit (15) (ICNT) said plurality of stages of delay elements ₍₁₁ 1 _{~11 N)} A bias generation circuit for supplying the current sources (14), and a. The delay element (11) so that the edge position detected by the edge detector (13) corresponds to the number of stages of delay elements set in advance corresponding to the frequency range of the first signal (DATA). Thus, even if the delay time of the TDC delay element (11) varies, the TDC conversion characteristics are normal and constant (linear). Hereinafter, embodiments will be described with reference to the accompanying drawings.

<Embodiment 1>
FIG. 1 is a diagram illustrating a configuration of a TDC according to an embodiment of the present invention. Although not particularly limited, the TDC of the present embodiment is preferably configured on a semiconductor integrated circuit device. In this case, FIG. 1 is an enlarged view of the circuit configuration of the TDC portion mounted on the PLL on the semiconductor integrated circuit device. Referring to FIG. 1, the TDC of the present embodiment includes a delay line 10 having a plurality of delay elements 11 and a flip-flop 12 ₁ that samples the outputs of the delay elements 11 _{1 to} 11 _N at each stage with a clock signal CLK. and to 12 _N, receives the outputs of the plurality of flip-flops ₁₂ 1 to 12 _N, includes an edge detector 13 which outputs a phase difference between DATA and CLK in digital code. The flip-flop 12 and the encoder 13 in FIG. 1 correspond to the flip-flop in FIG. 9 and an edge detector. However, although the edge detector of FIG. 9 outputs TDC_RISE and TDC_FALL, the encoder 13 may be configured to output only one of them. Similarly to the edge detection circuit of FIG. 9, the encoder 13 includes a gate circuit group that detects a mismatch between the outputs of the two adjacent flip-flops, and calculates the phase difference between DATA and CLK from the positions of the flip-flops in which the two adjacent outputs are different from each other. A value with the number of stages as a unit is encoded into a digital code and output. The edge detector 13 is also called an “encoder” because it encodes and outputs the detected edge. In FIG. 1, DATA may use CKV output from the DCO as a complementary signal, and CLK may be used as the reference clock FREF.

  In the present embodiment, the delay element 11 includes a current source in its power supply path. That is, as will be described later with reference to FIG. 4, first and second current sources are provided between the power supply VDD and the delay buffer (inverter), and between the buffer (inverter) and VSS, respectively. Yes.

  In the present embodiment, a bias generation circuit 14 that applies bias voltages Bias + and Bias− to the first and second current sources of the delay element 11, and the bias generation circuit 14 is controlled to control the delay time of the delay element 11. A calibration control circuit 15 that performs calibration is provided.

  Although not particularly limited, in this embodiment, each delay element 11 is inverted by inputting data (DATA +, DATA−) from its normal input terminal (+) and its inverting input terminal (−). And an inverting buffer for differential output from the inverting output terminal (−) and the normal output terminal (+). In FIG. 1, data (DATA +, DATA−) transmitted differentially is a signal whose phase is compared with the clock signal CLK, and corresponds to CKV in FIG. 9, where CLK is the reference clock signal in FIG. Corresponds to FREF. Needless to say, the delay element 11 may be composed of a single-ended input and single-ended output inverter (inverting buffer) as shown in FIG.

  Each stage flip-flop 12 inputs the output of the delay element 11 of the corresponding stage to the data terminal D, samples the data terminal signal at the rising edge of CLK input to the clock input terminal, and outputs the sampled value to the output terminal Q. Output from. Data (DATA +, DATA-) is differentially input to the delay line 10, data (DATA +, DATA-) is gradually delayed, delayed by the delay time per stage x the number of stages, and flip-flops at the rising edge of CLK 12

In this embodiment, the flip-flop 12 ₁ of the first stage, the first stage delay element 11 ₁ of the inverting output terminal (-) data terminal is connected to the (inverting output single-ended input to), the second-stage flip-flop 12 ₂ to the second-stage delay element 11 ₂ normal output terminal (+) data terminal connected (non-inverting output of the single-ended input), the flip-flop 12 ₃ of the third stage 3 stage delay element 11 ₃ The data terminal is connected to the inverting output terminal (−) (the inverting output is a single-ended input),..., And so on. The output is input. For this reason, for example, with respect to the rising transition of DATA + (DATA− which is a complementary signal of DATA + is a falling transition), the data terminal of the flip-flop 12 to which the output of the delay element 11 of each stage is input is in phase with DATA +. In addition, a rising edge that is delayed from the delay element 11 of the first stage by the total delay time of the delay element 11 of the stage is input. Similarly for the falling transition of DATA + (the rising transition of DATA−), the data terminal of the flip-flop 12 to which the output of the delay element 11 of each stage is input has the same phase as DATA + and the delay of the first stage. A falling waveform delayed from the element 11 by the total delay time of the delay element 11 of the stage is input. In FIG. 1, similar to FIG. 9, to a flip-flop for sampling the DATA + at the clock signal CLK may be provided to the flip flop 12 ₁ of the preceding stage (left neighboring in FIG. 1) is a matter of course.

FIG. 2 is a timing chart for explaining the operation of the TDC of FIG. In FIG. 2, DATA_D_1～DATA_D_5 is delayed by DATA + and phase is an output of the delay element ₁₁ 1 to 11 ₅ of the fifth stage from the first stage of FIG. In the example shown in FIG. 2, the case where the phase difference between the falling edge of DATA + and the rising edge of CLK is detected is illustrated. That is, the output of the encoder 13 in FIG. 2 corresponds to the output TDC_FALL of the edge detector in FIG. By utilizing the fact that the outputs of the flip-flops 12 before and after the point where the delay of DATA_D_1 to DATA_D_5 falls with respect to the rising edge of CLK and the advance relationship are reversed are different from each other (the output of the flip-flops 12 before and after the encoder 13). Is detected by a coincidence detection circuit (not shown), and the number of stages of delay elements corresponding to the phase difference between DATA + and CLK is detected and used as the output of the encoder 103. The number of stages requiring TDC is one period of the signal period (frequency) to be measured.

In the example of FIG. 2, the sample values in the first stage flip-flop 12 ₁ in response to first-stage delay element 11 ₁ of the output signal DATA_D_1 the rise of CLK, the 0,2-stage binary delay element 11 ₂ of The value sampled by the _second -stage flip-flop 122 in response to the rising edge of the CLK of the output signal DATA_D_2 is 1, and the timing of the falling edge of DATA + is the first and second stages of the delay element 11. You can see that it is between your eyes. Therefore, the output value of the encoder 103 is “2” (the delay time in the delay element 11 unit, the value is an integer), and the phase difference corresponds to the delay time (tdelay × 2) of the delay element 11 for two stages. Will do.

  FIG. 3 shows an example of TDC conversion characteristics (input / output characteristics). The horizontal axis represents the input phase difference (the phase difference between the rise or fall of DATA and the rise of CLK in FIG. 1), and the vertical axis represents the output code (digital code). FIG. 3 shows the magnitude of the delay of the delay element 11 of FIG. 1 and the normal case. As the phase difference increases, the characteristic that the output code of the TDC increases linearly (in steps of equal intervals) becomes an ideal state (normal). The width per step of the staircase characteristic corresponds to the delay time of one stage of the TDC delay element. When the delay time of the delay element 11 increases, the gradient (slope) of the input / output characteristics decreases, and conversely, when the delay time of the delay element 11 decreases, the gradient (slope) of the input / output characteristics increases.

  When the delay time of the delay element 11 varies, the delay element 11 becomes wider or narrower where there is one step of the TDC step characteristic. For this reason, an error in resolution for detecting the phase difference increases.

  According to this embodiment, the calibration of the delay time of the delay element 11 is performed by the calibration control circuit 15 and the bias generation circuit 14, and the conversion characteristic (step characteristic) of the TDC in FIG. 3 is made constant.

  FIG. 4 is a diagram illustrating a configuration example of the delay element 11 of FIG. An NMOS transistor 11-1 and a PMOS transistor 11-3 whose drains are connected in common and connected to an output node (inverted output node) OUT-, and whose gates are connected in common and connected to an input node (normal input node) IN +. Constitutes a first CMOS inverter. The NMOS transistors 11-2 and 11-4 have drains connected in common and connected to an output node (normal output node) OUT +, and gates connected in common to an input node (inverted input node) IN−. Constitutes a second CMOS inverter. The sources of the NMOS transistors 11-1 and 11-2 are connected in common and connected to one end of the current source 11-5, and the other end of the current source 11-5 is connected to VSS (GND). The sources of the PMOS transistors 11-3 and 11-4 are commonly connected and connected to one end of the current source 11-6, and the other end of the current source 11-6 is connected to the power supply VDD. The output (inverted output node) OUT− of the second CMOS inverter is connected to the input (normal input node) IN + of the first CMOS inverter via a resistor, and the output (normal output node) of the first CMOS inverter. ) OUT + is connected to the input (inverted input node) IN− of the second CMOS inverter through a resistor, and constitutes a differential latch in which the inputs and outputs of the first and second CMOS inverters are connected to each other. . When the IN + signal is High, the IN− signal is Low, the NMOS transistor 11-1 is on, the PMOS transistor 11-4 is on, OUT + is Low, and OUT− is High. When the IN + signal is low, the IN− signal is high, the NMOS transistor 11-2 is on, the PMOS transistor 11-3 is on, OUT + is high, and OUT− is low.

  Bias voltages Bias + and Bias− are respectively supplied from the bias generation circuit 14 to the current sources 11-5 and 11-6. The current source 11-5 is configured by an NMOS transistor having a source connected to VSS (GND), a gate receiving Bias-, and a drain connected to a commonly connected source of the NMOS transistors 11-1 and 11-2. May be. The current source 11-6 may be configured by a PMOS transistor having a source connected to VDD, a gate receiving Bias +, and a drain connected to a commonly connected source of the PMOS transistors 11-3 and 11-4. Good.

  According to the present embodiment, the delay time of the delay element 11 is corrected by changing the bias voltages Bias + and Bias− from the bias generation circuit 14 according to the control code from the calibration control circuit 15. When the current sources 11-5 and 11-6 are respectively composed of a PMOS transistor and an NMOS transistor, the bias generation circuit 14 raises Bias + and lowers Bias− so that the current sources 11-5 and 11-6 of the delay element 11 are increased. Both current values increase. When the current values of the current sources 11-5 and 11-6 increase, the charging time (rise time) of OUT + and OUT− to the High potential by the PMOS transistors 11-3 and 11-4, and the NMOS transistors 11-1 and 11-11 are increased. The discharge time (fall time) of OUT + and OUT− to Low potential due to −2 is shortened, and the delay time per stage of the delay element 11 (propagation delay time: propagation delay from the rise of the input to the fall of the output) The time (propagation delay time) and the propagation delay time from the falling edge of the input to the rising edge of the output are shortened. On the other hand, when the bias generation circuit 14 decreases Bias + and increases Bias−, the current values of the current sources 11-5 and 11-6 of the delay element 11 decrease, and OUT + and OUT by the PMOS transistors 11-3 and 11-4. The charging time (rising time) of − to the high potential and the discharging time (falling time) of OUT + and OUT− to the low potential by the NMOS transistors 11-1 and 11-2 are increased. The hit delay time (propagation delay time) increases.

  The bias generation circuit 14 has an arbitrary circuit configuration that generates bias voltages Bias + and Bias− having values corresponding to the control codes from the calibration control circuit 15. Although not particularly limited, when the current sources 11-6 and 11-5 are configured by PMOS transistors and NMOS transistors, the bias generation circuit 14 outputs a current having a value corresponding to the control code from the calibration control circuit 15. An analog converter (current mode DAC), a first PMOS transistor having a source connected to the power supply VDD, a diode connection (gate and drain connected) receiving the output current of the digital analog converter at the drain, and a source being the power supply Connected to VDD, the first PMOS transistor and the gate are connected in common, the second PMOS transistor constituting the current mirror, the source is connected to VSS, the drain is the output of the current mirror circuit (the second PMOS transistor of the second PMOS transistor) Connected to the drain) and diode connected With an NMOS transistor, the voltage of the gate of the first PMOS transistor and the NMOS transistor Bias +, may be Bias-.

  When the threshold value of the transistor, the power supply voltage, and the temperature change, the variation in delay time is about three times at the maximum and the minimum. It is necessary to prepare about three times the number of stages in the normal case. On the other hand, according to the present embodiment, the delay time of the delay element 11 is calibrated (calibrated) so that the operation can be performed without increasing the number of stages of the delay element 11.

  Further, according to the present embodiment, by adding the current sources 11-5 and 11-6 to the delay element 11, the influence on the delay time of the delay line 10 when the power supply voltage VDD / VSS fluctuates can be suppressed. . This is because the current sources 11-5 and 11-6 biased by the bias voltage function as constant current sources, and the CMOS inverter of the delay element 11 responds to fluctuations in the power supply voltage VDD / VSS. This is because the load can be charged and discharged with current.

  FIG. 5 schematically shows the relationship between the number of stages of TDC delay elements and the waveform of an input signal (DATA signal) having a different period in the time domain. With reference to FIG. 5, the setting of the delay time per stage of the delay element 11 in the present embodiment will be described. The duty of the DATA signal is 50%.

  The number of delay elements 11 of the TDC used is 128 (N = 128 in FIG. 1), and the frequency range of the DATA signal to be measured is 400-800 MHz. The center is 128/2 = 64 stages of the number of delay elements 128.

In this example, the frequency range of the DATA signal is 400 MHz to 800 MHz, that is, the TDC measures twice the frequency range. Therefore, the number of stages obtained by multiplying √2 times and 1 / (√2) times on one side around the 64 stages of the delay element 11 is obtained. This range is the range of the number of stages used in TDC. That is,
64x√2 = 90,
64x1 / (√2) = 45
(However, the fraction is rounded down).

  As shown in FIG. 5A, the range of the number of stages of the delay elements 11 used in the delay line 10 is 45-90. Therefore, in the TDC, a double frequency range can be measured by a double number range (0 to 90 steps) of 45 to 90 steps.

  TDC measures 400-800 MHz in this range. If the frequency range of 400-800 MHz is converted to a time period, the time range is 1250-2500 ps. The change in the period is measured in the range of 45 to 90 stages of delay elements 11 constituting the delay line 10. That is, as shown in FIG. 5B, there is one cycle of an 800 MHz signal in the 0-45 stage range of the delay element 11. Further, as shown in FIG. 5C, there is one cycle of a 400 MHz signal in the range of 0 to 90 stages of the delay element 11, and a signal having a frequency between 400 and 800 MHz is transmitted to the delay line 10. The delay element 11 is between 45 and 90 stages.

Therefore, the delay time per stage of the delay element is
2500/90 = 1250/45 = 27.8 ps
In this case, the 400 MHz signal is included in one cycle in the 0-90 stage range of the delay element 11. Then, the calibration control circuit 15 and the bias generation circuit 14 correct the delay time of the delay element 11 to 27.8 ps so that the signal in the frequency range 400-800 MHz is 45-90 of the delay element 11 of the delay line 10. It will be in the range of steps.

  When measuring a signal in the vicinity of 400 MHz, even if there is a process variation (variation in the manufacturing process of a semiconductor chip on which a TDC is mounted), the edge position (the edge of the delayed measurement target signal) at the 45th stage of the delay element 11 The position where the output result of the flip-flop is switched in correspondence with

  According to the present embodiment, the output of the flip-flop 12 is monitored, and calibration control is performed so that the output is switched by the flip-flop 12 connected to the delay elements 11 of the set number of stages (for example, 45th stage) in the initial calibration. The circuit 15 generates a control code (Control Code) ICNT for bias generation and supplies it to the bias generation circuit 14.

  The bias generation circuit 14 generates bias voltages (also simply referred to as “bias”) Bias + and Bias− corresponding to the value of the control code ICNT of the digital signal, and supplies the bias voltages to the current sources 11-6 and 11-5 of the delay element 11. Then, the delay of the delay element 11 is corrected.

  The calibration control circuit 15 determines the initial position (the number of stages of the delay element 11) according to the frequency of the signal to be measured (45 to 90 stages for signals in the frequency range 400 to 800 MHz), and then the frequency fluctuates. Even in such a case, the phase difference measurement range at the TDC falls within the 45-90 stage range of the delay element 11.

  The frequency range of the measurement target signal (DATA + / DATA−) is set in advance in a storage device (not shown) of the calibration control circuit 15.

  FIG. 7 shows an example of a correspondence relationship between the frequency range of the signal to be measured and the set number of stages (the number of stages of the delay element 11 in FIG. 1). In FIG. 7, the frequency range 400-800 MHz is divided into 16 (1 division = 25 MHz), and the number of setting stages of the delay element 11 is determined according to each division. The calibration control circuit 15 holds the setting contents (frequency range and setting number of delay elements) in the table format of FIG. 7 in a storage device (not shown), and delay elements corresponding to the frequency range of the signal to be measured. Get the set number of steps.

  The range other than the 45-90 stage range of the delay element 11 of the delay line 10 is a margin for power supply voltage and temperature fluctuation after calibration by the calibration control circuit 15. In TDC, for example, when measuring a signal having a frequency of 400 MHz, it is assumed that 90 stages of delay elements 11 are used in the delay line 10. At this time, if the delay time per delay element becomes slow (long) due to power supply voltage, temperature fluctuation, etc., the edge position is measured using the delay element 11 in the range of 90 to 128 stages of the delay line 10. To do.

  In TDC, when measuring a signal having a frequency of 800 MHz, the delay line 10 is calibrated by using 45 stages of delay elements 11, and then the delay per stage of the delay elements 11 is changed due to power supply voltage and temperature fluctuations. If it is faster (shorter), 45 stages or less of the delay element 11 are used, but if the number of stages is too small, the accuracy of the TDC is affected. In that case, a fail-safe function described later as the second embodiment of the present invention is used.

  FIG. 6 is a flowchart for explaining the procedure of the calibration control circuit 15 of the present embodiment. A calibration procedure will be described with reference to FIG.

<Procedure 1>
Calibration is started (S1). When calibration is performed, a signal in a predetermined frequency range (for example, 400 MHz) is input as the signal DATA + / DATA− input to the delay line 10.

<Procedure 2>
The calibration control circuit 15 controls the control code (ICNT) supplied to the bias generation circuit 14 to change Bias + and Bias− from the bias generation circuit 14, and the current sources 11-5 and 11-6 of the delay element 11. The current of the delay element 11 is decreased step by step from the maximum state (the delay time of the delay element 11 is minimum) (S2), and the delay of the delay element 11 is delayed by one step unit to correspond to the set delay time. Match the number of output stages of the delay line 10 of the TDC. In FIG. 1, the delay element 11 is set so that the edge position of the calibration target signal (DATA + / DATA−) having a delay (phase difference) set with respect to CLK corresponds to the set number of stages of the delay element 11. Adjust the delay time. The calibration control circuit 15 changes the value (digital value) of the control code (ICNT) supplied to the bias generation circuit 14 by one, and the bias generation circuit 14 changes to Bias +, in response to the change in the value of the control code. A change in the delay amount of the delay element 11 by changing Vias is defined as one step of the delay time of the delay element 11.

The calibration control circuit 15 measures the number of stages of the delay element 11 corresponding to the set delay time from the output of the flip-flop 12 (output of the edge detector 13) (S3). The calibration control circuit 15 acquires the edge position of the measurement target signal DATA from the edge detector 13, and acquires the number of stages of the delay element 11 corresponding to the set delay time (information about what stage). In FIG. 1, the calibration control circuit 15 inputs the edge position output from the edge detector 13 (the position at which the output of the flip-flop 12 switches), but the present invention is limited to such a configuration. Instead, the calibration control circuit 15 may be configured to directly input the outputs of the flip-flops 12 _{1 to} 12 _N.

  When the acquired number of stages of the delay element 11 is equal to or greater than the set number of stages from the beginning, the current of the current sources 11-5 and 11-6 (FIG. 4) of the delay element 11 is maximized (the delay time of the delay element 11 is increased). Calibration) is finished. The PMOS transistors 11-3 and 11-4 and the NMOS transistors 11-1 and 11-2 constituting the delay element 11 are preferably arranged so that an appropriate delay time is obtained within the current value setting range of the current source (see FIG. The size of 4) is optimized in advance.

<Procedure 3>
Even if the currents of the current sources 11-5 and 11-6 (FIG. 4) of the delay element 11 are reduced by one step, the desired number of stages (threshold value of the number of stages in the table of the calibration control circuit 15 (FIG. 7)) is reached. If not (NO branch of S4), the current of the current sources 11-5 and 11-6 is further reduced by another step. This loop processing is repeated several times to bring it closer to the set number of delay elements 11 corresponding to the set delay time.

<Procedure 4>
When the number of stages of delay elements 11 set in the table (holding the contents of FIG. 7) in the calibration control circuit 15 (the number of stages set corresponding to the frequency range of the measurement target signal) is exceeded, the calibration is terminated. (YES branch of step S4).

  The calibration control circuit 15 controls the control code (ICNT) supplied to the bias generation circuit 14 to change Bias + and Bias− from the bias generation circuit 14, thereby changing the current sources 11-5 and 11 of the delay element 11. The current of −6 (FIG. 4) may be controlled to be increased step by step from the minimum state (the delay time of the delay element 11 is maximum).

  In FIG. 6, when the number of stages of the delay element 1 is 128 or more or 16 or less after calibration is completed, a fail-safe function described below is executed (S5).

<Second Embodiment>
The Fail-Safe function is a function that automatically and automatically performs calibration even during the TDC operation after the end of the initial calibration. In the present embodiment, this Fail-Safe function is added to the calibration control circuit 15. Hereinafter, the operation of the Fail-Safe function will be described.

  After the calibration is completed, the delay time per stage of the delay element 11 of the delay line 10 of the TDC changes due to power supply voltage, temperature fluctuation, etc. during normal operation, and the number of stages used by the delay element 11 of the TDC is excessive or insufficient. If it occurs, the calibration control circuit 15 detects this and controls the delay time of the delay element 11 of the TDC.

  In S5 of FIG. 6, in the calibration control circuit 15 that inputs the output of the flip-flop 12, the number of stages of the delay element 11 equivalent to the set delay time is 128 or more, or 16 or less is detected. This corresponds to a case where the number of stages used in the delay element 11 of the TDC delay line 10 is excessive or insufficient.

  That is, the case where the number of use stages of the delay elements 11 of the delay line 10 of the TDC is insufficient means that the delay time per stage of the delay elements becomes extremely fast due to power supply voltage and temperature fluctuations, and the number of stages of the delay elements in the TDC. Is lacking. For example, if the delay time of the delay element is ½ of the original, the phase difference with respect to CLK can be measured only for a signal having a period of ½ of the previously measured period. As a result, one cycle of the input signal is not included in the number of stages of the delay elements 11 of the TDC delay line 10 prepared in advance, and there is no rise of the measurement target signal, and the TDC does not function.

  Further, the case where the number of stages of the delay elements 11 used in the delay line 10 of the TDC is excessive means that the number of stages of the delay elements is excessive when the delay time per delay element becomes extremely slow due to power supply voltage and temperature fluctuations. It becomes. In this case, since the delay time per stage of the delay element is increased, the resolution of TDC is increased and one step is roughened. As a result, in TDC, the phase difference that should be measured cannot be measured.

  To avoid this situation, when the edge position of the measurement target signal comes near the set number of stages, the calibration control circuit 15 performs control to increase the delay of the delay element 11 based on the detection result of the edge position. The bias generation circuit 14 reduces the current of the current source of the delay element 11 by one step and increases the delay. On the other hand, when the number of stages of the delay elements 11 is insufficient, the delay by one step is further increased. For example, if a 128-stage delay element is prepared, the calibration control circuit 15 determines that there is a delay near 127 stages based on the detection result of the edge position based on the output of the flip-flop 12. The control circuit 15 transmits a control code (ICNT) for setting the current to be lowered by one step to the bias generation circuit 14. The bias generation circuit 14 changes Bias + and Bias− based on the control code (ICNT), and delays the delay of the delay element 11 by the amount of decrease in the current of one step of the current source of the delay element 11. When the edge position becomes 126 steps or less, the code change is stopped and this control is repeated.

  Further, when the delay time of the delay element 11 is delayed, for example, when the edge position comes to 32 stages or less of the 128 stages of the delay element 11, the calibration control circuit 15 sets a control code for setting the current one step higher ( ICNT) to the bias generation circuit 14. The bias generation circuit 14 changes Bias + and Bias− based on the control code (ICNT), and shortens the delay of the delay element 11 by a current increase of one step of the current source of the delay element 11.

  Thus, according to the present embodiment, the control code is controlled by the Fail-Safe function so that the control code functions normally even when the delay time of the delay element 11 greatly changes during the operation of the TDC.

  The fail-safe function makes it possible to return to the normal delay time even when the number of stages of the delay elements is insufficient during the normal operation of the TDC, and as a result, prevents the deterioration of the linearity of the input / output of the TDC. be able to.

  The present invention applies to TDC in any digital PLL (including all digital PLL (ADPLL)). In ADPLL, a small phase difference between the reference signal and the feedback signal is obtained by TDC. The calibration control circuit 15 and the bias generation circuit 14 control the TDC conversion characteristics to be constant (normal linear characteristics) with respect to variations in delay of the delay elements. The digital PLL is not limited to the configuration shown in FIG. 8 and can be applied to any ADPLL TDC.

  According to the present invention, the semiconductor device (digital device) is configured to control the conversion characteristics of the TDC to be constant with respect to variations in the delay time of the delay element due to manufacturing process variations, power supply, temperature variations, and the like. It is preferable to be mounted on an integrated circuit).

  It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiment can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

10 the delay line 11, 11 ₁ to 11 _N delay elements 11 - 1 and 11 - 2 NMOS transistors 11-3 and 11-4 PMOS transistor 11 - 5 and 11 - 6 current sources 12, 12 ₁ to 12 _N flip-flop 13 edge Detector (encoder)
14 Bias Generation Circuit 15 Calibration Control Circuit 100 All Digital PLL (All Digital PLL: ADPLL)
102 Accumulator
103 Numerically controlled oscillator (NCO)
104 DCO (Digitally Controlled Oscillator)
105 Gain (GAIN) Element 106 Wave Shaper 108 Ceiling Element 110 Reference Crystal Oscillator (FREF: Reference Clock)
112 Frequency reference clock CKR
114 Clock signal CKV
116 Frequency control word (FCW)
120 Latch / Register 200 Small Phase Detector / Small Phase Detector System 201 TDC

Claims (9)

A delay line having a plurality of delay elements for sequentially delaying the first signal;
A plurality of flip-flops arranged corresponding to the plurality of stages of delay elements and sampling the outputs of the plurality of stages of delay elements in response to a commonly input second signal;
An edge detector that receives outputs of the plurality of flip-flops and detects an edge position at which output results of adjacent flip-flops are switched as a phase difference of the first signal with respect to the second signal;
A TDC (Time-to-Digital Converter) device comprising:
The delay element includes a current source in a power supply path, and varies a delay time according to a bias applied to the current source,
A calibration control circuit that generates a control code for bias control based on the detection result of the edge position;
A bias generation circuit that generates a bias corresponding to the control code from the calibration control circuit and supplies the bias to the plurality of stages of delay elements;
With
At the time of calibration, in the calibration control circuit, the edge position detected by the edge detector corresponds to the number of stages of delay elements set in advance corresponding to the frequency range of the first signal. A TDC device that controls the bias generation circuit to calibrate the delay time of the delay element.   The TDC apparatus according to claim 1, wherein the calibration control circuit stores and holds the frequency range of the first signal to be measured and the set stage number information of the delay element corresponding to the frequency range in association with each other.   At the time of calibration, a first signal having a predetermined phase difference in a predetermined frequency range is input to the delay line, and the calibration control circuit controls the bias generation circuit to control the delay element. Starting from the maximum or minimum value, the current source is decreased or increased by a predetermined step unit, and the edge position detected by the edge detector is controlled to be a predetermined number of stages of delay elements corresponding to the phase difference. The TDC device according to claim 1 or 2.   In the calibration control circuit, the edge position detected by the edge detector is greater than or equal to a predetermined first number of stages with respect to the number of stages of delay elements, or smaller than the first number of stages. 2. A fail-safe function for controlling the bias generation circuit to shorten or lengthen the delay time of the delay element when the number of stages is two or less is provided. 4. The TDC device according to any one of items 1 to 3.   A semiconductor device comprising the TDC device according to claim 1. A delay line having a plurality of delay elements for sequentially delaying the first signal;
A plurality of flip-flops arranged corresponding to the plurality of stages of delay elements and sampling the outputs of the plurality of stages of delay elements in response to a commonly input second signal;
An edge detector for inputting an output of the plurality of flip-flops and detecting an edge position at which an output result of adjacent flip-flops is switched as a phase difference between the first signal and the second signal;
A TDC (Time-to-Digital Converter) calibration method comprising:
The delay element includes a current source in a power supply path, and a delay time can be varied according to a bias applied to the current source.
A calibration control circuit generates a control code for bias control based on the detection result of the edge position,
A bias corresponding to the control code is generated by a bias generation circuit, supplied to the plurality of stages of delay elements, and the edge position detected by the edge detector is in the frequency range of the first signal. A TDC calibration method for calibrating the delay time of the delay element so as to correspond to a preset number of stages of delay elements.   7. The TDC calibration method according to claim 6, wherein the calibration control circuit stores and holds the frequency range of the first signal to be measured and the set stage number information of the delay element corresponding to the frequency range in association with each other. .   During calibration, a first signal having a predetermined phase difference in a predetermined frequency range is input to the delay line, and the current source of the delay element is decreased or increased in predetermined steps starting from the maximum or minimum value. The TDC calibration method according to claim 6, wherein the position of the edge detected by the edge detector is controlled to be a predetermined number of stages of delay elements corresponding to the phase difference.   When the detected edge position is greater than or equal to a predetermined first number of delay elements or less than or equal to a second number smaller than the first number, the bias generation circuit The TDC calibration method according to claim 6, wherein the delay time of the delay element is controlled to be shortened or lengthened by controlling the delay time.

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