CN102299709A - High precision pulse width comparator based on time-to-digit conversion - Google Patents
High precision pulse width comparator based on time-to-digit conversion Download PDFInfo
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Abstract
The invention discloses an automatic frequency comparison circuit of a high precision pulse width comparator based on time-to-digit conversion. In the invention, a DLL module, which is added to an auto frequency correction (AFC) device of a phase lock loop (PLL), can generate a plurality of delay phase clocks which have a same frequency and phase difference with a reference clock. The reference clock and the delay clocks are counted and all counter results are accumulated. Simultaneously, a feedback clock is counted. A capacitance array is adjusted through comparing a counter accumulation value of the reference clock and the delay clocks with a feedback counter value. A DLL delay PLL circuit is only needed to be added to the circuit so that frequency resolution can be greatly raised, a frequency difference between the reference clock and the feedback clock can be distinguished with high precision, automatic correction time can be greatly reduced and PLL locking time can be shortened. Therefore, in a modern communication system, a demand of rapidly switching a PLL frequency can be satisfied.
Description
Technical field
The present invention is applicable to communication system, relates to a kind of high accuracy pulsewidth comparison means based on the time figure switch technology that is used for AFC (Auto frequency correction) the automatic frequency calibration circuit of rfic chip phase-locked loop.
Background technology
At present, in Modern Communication System, radio frequency chip often need cover wider frequency, and exceeded the VCO(Voltagecontroloscillator voltage controlled oscillator) scope that can cover by regulation voltage, PLL phase-locked loop (PhaseLockLoop phase-locked loop) therefore need all can normally lock in bigger frequency range for radio frequency chip provides local oscillator.As shown in Figure 1, existing phase-locked loop increases VCO frequency adjustable adjusting range by increase adjustable capacitor array to VCO, can lock and keep less VCO sensitivity at big frequency range VCO, guarantees that the phase noise of system can not worsen.Power on and VCO and Divider(frequency divider at phase-locked loop systems) stable after, by reference clock is counted the identical time with the frequency divider feedback clock, by comparing the size of two Counter Values, judge that the feedback clock frequency is higher or on the low side at this moment, increase the capacitor array value if the feedback clock frequency is higher and then reduce the VCO output frequency, if the feedback clock frequency is on the low side then reduce the capacitor array value and then increase the VCO output frequency, change capacitor array after counter restart new round counting.By binary search algorithm, find the most approaching reasonable capacitor array configuration.Like this through finishing the automatic frequency calibration several times.But, because reference clock frequency and the feedback clock frequency differs and not quite, therefore need the counting long period could its frequency difference of frequency division, cause phase-locked loop output clock to reach and oversizely can not satisfy in the communication system stabilization time the clock frequency requirement of switching fast.
Summary of the invention
The object of the present invention is to provide a kind of realization simple, can realize AFC (the Auto frequency correction) circuit of the fast automatic calibration of frequency.
For solving the problems of the technologies described above, the technical scheme that AFC of the present invention (Auto frequency correction) automatic frequency calibration circuit adopts is: a kind of high accuracy pulsewidth comparison means based on the time figure conversion, and whole phase-locked loop mainly comprises as lower module:
The PFD phase frequency detector produces charging or the discharge instruction signal of using to charge pump according to the difference of reference clock and feedback clock frequency and phase place;
The CP charge pump charges or discharges according to the output of PFD phase frequency detector;
The LF loop filter carries out the conversion of electric current to voltage, produces the control voltage of VCO voltage controlled oscillator 104;
The VCO voltage controlled oscillator carries out the conversion of voltage to frequency, produces needed high frequency clock;
Switched capacitor array is connected with the VCO voltage controlled oscillator;
The Divider frequency divider, the high frequency clock that the VCO voltage controlled oscillator is exported carries out frequency division, produces corresponding feedback clock and gives the PFD phase frequency detector, forms feedback control loop;
AFC automatic frequency calibration module, when phase-locked loop integral body had just powered on, the whole loop of phase-locked loop this moment was also not closed, and described Divider frequency divider is exported to AFC automatic frequency calibration module, regulates for its switched capacitor array to the VCO voltage controlled oscillator;
The DLL module produces the phase retardation clock of a plurality of and reference clock same frequency equiphase difference and inputs to AFC automatic frequency calibration module.
Described AFC automatic frequency calibration module inside is to reference clock and phase retardation clock count, and the add up clock counter result of back and Divider frequency divider of count results is compared, and disposes according to comparative result by-pass cock capacitor array.
Described by-pass cock capacitor array configuration is found only capacitor array configuration by binary search algorithm.
After AFC automatic frequency calibration module found the suitable capacitance array configurations, the corresponding feedback clock of Divider was given the PFD phase frequency detector, formed feedback control loop, and phase-locked loop is started working;
Owing to adopted above-mentioned structure, the present invention adopts the high accuracy pulsewidth based on the time figure conversion of delay phase-locked loop relatively more theoretical, on the basis of original automatic frequency calibrating installation, increase the DLL module and produce phase retardation clock a plurality of and reference clock same frequency equiphase difference, add up to reference clock and delayed clock thereof counting and with all counter results simultaneously, simultaneously feedback clock is counted, by relatively reference clock and delayed clock counter accumulated value thereof and feedback counter value are adjusted capacitor array.Only needing above the circuit increases the DLL delay locked-loop circuit, just can reduce the count cycle of parameter clock, therefore the reference clock count cycle that need be still less than traditional automatic frequency calibration circuit.Increase substantially frequency resolution, can more high-precisionly tell the frequency difference of reference clock and feedback clock, reduce the automatic alignment time significantly, shorten phase lock loop lock on time, thereby can satisfy the demand that modern communication systems is switched fast to phase-locked loop frequency.
Description of drawings
Fig. 1 is present existing phase-locked loop integrated stand composition.
Fig. 2 is VCO frequency-voltage curve.
Fig. 3 is the schematic diagram that adopts the phase-locked loop of the high accuracy pulsewidth comparison means of changing based on time figure.
The high accuracy pulsewidth that Fig. 4 is based on the time figure conversion compares AFC frequency automatic calibration module diagram.
Fig. 5 is the binary search algorithm schematic diagram.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in further detail.
As shown in Figure 3, a kind of phase-locked loop that adopts based on the high accuracy pulsewidth comparison means of time figure conversion of the present invention comprises:
PFD (Phase Frequency Detector) phase frequency detector 101 produces charging or discharge instruction signal to charge pump 102 usefulness according to the difference of reference clock and feedback clock frequency and phase place;
CP (charge bump) charge pump 102 charges or discharges according to the output of PFD phase frequency detector 101;
LF (Loop filter) loop filter 103 carries out the conversion of electric current to voltage, produces the control voltage of VCO voltage controlled oscillator 104;
VCO (Voltage control oscillator) voltage controlled oscillator 104 carries out the conversion of voltage to frequency, produces needed high frequency clock;
Switched capacitor array 105 is connected with VCO voltage controlled oscillator 104; In order to satisfy the covering of present communication system contrast broad frequency, and the voltage-regulation scope that satisfies the performance VCO self of design can not be too big, so be designed to the framework of adjustable condenser array, find and the immediate capacitor array configuration of needed clock frequency thereby can constantly approach by binary search algorithm.
Divider frequency divider 106, the high frequency clock that VCO voltage controlled oscillator 104 is exported carries out frequency division, produces corresponding feedback clock and gives PFD phase frequency detector 101, forms feedback control loop;
AFC (Auto frequency correction) automatic frequency calibration module 107, when phase-locked loop integral body has just powered on, the whole loop of phase-locked loop this moment is also not closed, described Divider frequency divider 106 is exported to AFC automatic frequency calibration module, regulates for its switched capacitor array to VCO voltage controlled oscillator 104;
DLL module 108 produces the phase retardation clock of a plurality of and reference clock same frequency equiphase difference and inputs to AFC automatic frequency calibration module 107.
Described AFC automatic frequency calibration module 107 inside are to reference clock and phase retardation clock count, add up back and the clock counter result of Divider frequency divider 106 of count results compared, dispose according to comparative result by-pass cock capacitor array 105.
Described by-pass cock capacitor array 105 configurations are found only capacitor array configuration by binary search algorithm.
After AFC automatic frequency calibration module 107 found the suitable capacitance array configurations, Divider frequency divider 106 corresponding feedback clocks were given PFD phase frequency detector 101, formed feedback control loop, and cycle of phase-locked loop enters operating state;
The present invention compares with traditional AFC automatic frequency calibration module structure has increased a DLL module, also count reference clock and delayed clock from only the reference clock technology having been become simultaneously the counter of reference clock AFC automatic frequency calibration module inside, to count results add up the back and frequency divider clock counter result compare, according to comparative result control capacittance array configurations, find only capacitor array configuration by binary search algorithm successively.
As shown in Figure 2, the configuration of different capacitor arrays is the relation of VCO output clock frequency and control voltage down, selects requiredly among one group of F-V figure of the effect of AFC automatic frequency calibration module from figure, guarantees that the VCO locking frequency drops on the selected F-V line.
The work schematic diagram of AFC automatic frequency calibration module as shown in Figure 4, after having adopted multiphase clock 401 based on the time figure conversion, because reference count is simultaneously to a plurality of phase count of reference clock, need the reference clock count cycle still less, can significantly improve resolution, thereby can in the shorter time, distinguish the frequency speed of reference clock and frequency-dividing clock, thereby can in the shorter time, finish binary search algorithm and find suitable capacitance arrangement 402.Thereby phase-locked loop can lock in the short period of time, satisfies the requirement that modern communication systems is switched fast to clock frequency.
Binary search algorithm as shown in Figure 5, it is N+1=7 time that the binary search algorithm of whole 6 bits need be finished counts, owing to adopted the raising of delay phase-locked loop frequency resolution, thereby counter only need be counted the fewer clock cycle and both can finish the frequency speed and distinguish.Be used for the time of binary search thereby significantly reduce.After finishing, each counting adjusts accordingly by relatively capacitor array being exported of counter result, counter makes zero and carries out new round counting then, so operation is N+1=7 time, the result of last as shown above three countings preserves, each result all compares with preset value, selects the pairing capacitor array configuration of the count results output of difference minimum.So far, the calibration of AFC automatic frequency is finished, and VCO selects correct capacitor array configuration, cycle of phase-locked loop closure.
In a word; though the present invention has exemplified above-mentioned preferred implementation, should illustrate, though those skilled in the art can carry out various variations and remodeling; unless such variation and remodeling have departed from scope of the present invention, otherwise all should be included in protection scope of the present invention.
Claims (3)
1. high accuracy pulsewidth comparison means based on time figure conversion, whole phase-locked loop mainly comprises as lower module:
PFD phase frequency detector (101) produces charging or discharge instruction signal to charge pump (102) usefulness according to the difference of reference clock and feedback clock frequency and phase place;
CP charge pump (102) charges or discharges according to the output of PFD phase frequency detector (101);
LF loop filter (103) carries out the conversion of electric current to voltage, produces the control voltage of VCO voltage controlled oscillator (104);
VCO voltage controlled oscillator (104) carries out the conversion of voltage to frequency, produces needed high frequency clock;
Switched capacitor array (105) is connected with VCO voltage controlled oscillator (104);
Divider frequency divider (106), the high frequency clock that VCO voltage controlled oscillator (104) is exported carries out frequency division, produces corresponding feedback clock and gives PFD phase frequency detector (101), forms feedback control loop;
AFC (Auto frequency correction) automatic frequency calibration module (107), when phase-locked loop integral body has just powered on, the whole loop of phase-locked loop this moment is also not closed, described Divider frequency divider (106) is exported to AFC automatic frequency calibration module, regulates for its switched capacitor array to VCO voltage controlled oscillator (104) (105);
DLL module (108) produces the phase retardation clock of a plurality of and reference clock same frequency equiphase difference and inputs to AFC automatic frequency calibration module (107).
2. according to the described a kind of automatic frequency calibration circuit that adopts based on the high accuracy pulsewidth comparison means of time figure conversion of claim 1, it is characterized in that: described AFC automatic frequency calibration module (107) is inner to reference clock and phase retardation clock count, add up back and the clock counter result of Divider frequency divider (106) of count results compared, dispose according to comparative result by-pass cock capacitor array (105).
3. according to the described a kind of automatic frequency calibration circuit that adopts based on the high accuracy pulsewidth comparison means of time figure conversion of claim 2, it is characterized in that: described by-pass cock capacitor array (105) configuration is found only capacitor array configuration by binary search algorithm.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751985A (en) * | 2012-07-16 | 2012-10-24 | 中科芯集成电路股份有限公司 | Automatic frequency calibration circuit applied to VCO (Voltage Controlled Oscillator) |
| CN105897259A (en) * | 2015-02-17 | 2016-08-24 | 恩智浦有限公司 | Two-point modulation of a semi-digital phase locked loop |
| CN107565959A (en) * | 2017-09-05 | 2018-01-09 | 英特格灵芯片(天津)有限公司 | A kind of high speed delay phase-locked loop and its automatic frequency calibration method |
| CN108988855A (en) * | 2017-05-30 | 2018-12-11 | 格芯公司 | Injection locked oscillator system and method |
| CN112019187A (en) * | 2020-09-04 | 2020-12-01 | 东南大学 | Automatic frequency calibration circuit |
| CN113054998A (en) * | 2019-12-26 | 2021-06-29 | 澜至电子科技（成都）有限公司 | Linear calibration system and method of time-to-digital converter and digital phase-locked loop |
| CN113541683A (en) * | 2021-06-08 | 2021-10-22 | 西安电子科技大学 | Phase-locked loop automatic frequency calibrator based on programmable three-frequency divider |
| CN113810046A (en) * | 2020-06-12 | 2021-12-17 | 连云港坤芯微电子科技有限公司 | Quick automatic frequency calibration device and method |
| CN118795756A (en) * | 2024-09-10 | 2024-10-18 | 浙江赛思电子科技有限公司 | A calibration method and system for a digital time converter |
| CN119420348A (en) * | 2025-01-06 | 2025-02-11 | 苏州博创集成电路设计有限公司 | All-digital delay phase-locked loop circuit and calibration method |
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| US4789996A (en) * | 1988-01-28 | 1988-12-06 | Siemens Transmission Systems, Inc. | Center frequency high resolution digital phase-lock loop circuit |
| EP1693967A1 (en) * | 2003-12-10 | 2006-08-23 | Matsushita Electric Industrial Co., Ltd. | Delta-sigma type fraction division pll synthesizer |
| CN101951259A (en) * | 2010-08-26 | 2011-01-19 | 上海南麟电子有限公司 | Phase-locked loop and automatic frequency calibration circuit thereof and phase-locked loop self-tuning locking method |
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2011
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US4789996A (en) * | 1988-01-28 | 1988-12-06 | Siemens Transmission Systems, Inc. | Center frequency high resolution digital phase-lock loop circuit |
| EP1693967A1 (en) * | 2003-12-10 | 2006-08-23 | Matsushita Electric Industrial Co., Ltd. | Delta-sigma type fraction division pll synthesizer |
| CN101951259A (en) * | 2010-08-26 | 2011-01-19 | 上海南麟电子有限公司 | Phase-locked loop and automatic frequency calibration circuit thereof and phase-locked loop self-tuning locking method |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751985B (en) * | 2012-07-16 | 2014-08-06 | 中科芯集成电路股份有限公司 | Automatic frequency calibration circuit applied to VCO (Voltage Controlled Oscillator) |
| CN102751985A (en) * | 2012-07-16 | 2012-10-24 | 中科芯集成电路股份有限公司 | Automatic frequency calibration circuit applied to VCO (Voltage Controlled Oscillator) |
| CN105897259A (en) * | 2015-02-17 | 2016-08-24 | 恩智浦有限公司 | Two-point modulation of a semi-digital phase locked loop |
| CN105897259B (en) * | 2015-02-17 | 2021-02-05 | 恩智浦有限公司 | Time-to-digital converter and phase-locked loop |
| CN108988855B (en) * | 2017-05-30 | 2022-09-09 | 格芯公司 | Injection Locked Oscillator System and Method |
| CN108988855A (en) * | 2017-05-30 | 2018-12-11 | 格芯公司 | Injection locked oscillator system and method |
| CN107565959A (en) * | 2017-09-05 | 2018-01-09 | 英特格灵芯片(天津)有限公司 | A kind of high speed delay phase-locked loop and its automatic frequency calibration method |
| CN107565959B (en) * | 2017-09-05 | 2024-02-27 | 豪威模拟集成电路(北京)有限公司 | High-speed delay phase-locked loop |
| CN113054998A (en) * | 2019-12-26 | 2021-06-29 | 澜至电子科技（成都）有限公司 | Linear calibration system and method of time-to-digital converter and digital phase-locked loop |
| CN113810046A (en) * | 2020-06-12 | 2021-12-17 | 连云港坤芯微电子科技有限公司 | Quick automatic frequency calibration device and method |
| CN112019187B (en) * | 2020-09-04 | 2023-10-27 | 东南大学 | An automatic frequency calibration circuit |
| CN112019187A (en) * | 2020-09-04 | 2020-12-01 | 东南大学 | Automatic frequency calibration circuit |
| CN113541683B (en) * | 2021-06-08 | 2022-11-25 | 西安电子科技大学 | A Phase-Locked Loop Automatic Frequency Calibrator Based on Programmable Three-Frequency Divider |
| CN113541683A (en) * | 2021-06-08 | 2021-10-22 | 西安电子科技大学 | Phase-locked loop automatic frequency calibrator based on programmable three-frequency divider |
| CN118795756A (en) * | 2024-09-10 | 2024-10-18 | 浙江赛思电子科技有限公司 | A calibration method and system for a digital time converter |
| CN119420348A (en) * | 2025-01-06 | 2025-02-11 | 苏州博创集成电路设计有限公司 | All-digital delay phase-locked loop circuit and calibration method |
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Application publication date: 20111228 |