CN107565959A - A kind of high speed delay phase-locked loop and its automatic frequency calibration method - Google Patents
A kind of high speed delay phase-locked loop and its automatic frequency calibration method Download PDFInfo
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Abstract
The present invention relates to a kind of high speed delay phase-locked loop and its automatic frequency calibration method, wherein, high speed delay phase-locked loop includes automatic frequency calibration algorithm module, chain of delay, four-divider, phase discriminator, sample circuit, charge pump, wave filter, voltage regulator and bias-voltage generating circuit；Automatic frequency calibration algorithm module is used for the sampled result for obtaining sample circuit output；And the output of the output voltage and bias-voltage generating circuit of voltage regulator is set；Chain of delay is used to generate input clock and delayed clock according to the output voltage of voltage regulator, the delay control voltage of wave filter and high-frequency clock；Four-divider is used to carry out two divided-frequency twice respectively to input clock and delayed clock；Phase discriminator is used to carry out phase demodulation to the input clock after reduction of speed and delayed clock, and exports correspondingly phase error signal to charge pump；Charge pump is used to phase error signal being converted into current signal, and wave filter generates the delay control voltage according to current signal.
Description
Technical field
The invention belongs to high-speed interface field of data transmission, it is mainly used in the generation of orthogonal clock in high-speed interface circuit,
It is related to a kind of high speed delay phase-locked loop and its automatic frequency calibration method.
Background technology
With the development of sub-micron, sub-micro technology, super large-scale integration and system integration technology are increasingly
Maturation, the collection of chip is increasing on a large scale, operating rate is also increasingly faster, and this causes the piece as chip important component
The quality of internal clock is even more important.Because the delay phase-locked loop of unconditional stability have " zero-lag ", low noise, low jitter and
The characteristics of easily designed, the clock for being suitably applied mass rapid chip are synchronous.In recent years, clock is used as using delay phase-locked loop
The technology of distribution is had been widely used in the chips such as field programmable gate array, microprocessor.
In high-speed interface circuit, often clock and data recovery is participated in using orthogonal clock.Produce the realization side of orthogonal clock
Formula has two-divider, multiphase filter etc..When data rate is up to per second more than ten, twenties lucky position (Gbps), use is above-mentioned
Method realizes orthogonal clock with regard to relatively difficult.
The content of the invention
In order to overcome raw stable orthogonal clock of being had difficult labour in high-speed interface circuit, the present invention uses high speed delay phase-locked loop
Method realize, while a kind of automatic frequency calibration method is proposed, for carrying out correctly delay frequency to high speed delay phase-locked loop
Band selection, selects the appropriate frequency bands being suitable under current application environment, then special by the closed loop of high speed delay phase-locked loop again
Property carry out loop-locking, so as to which the orthogonal clock stablize exports.
To achieve the above object, one aspect of the present invention provides a kind of high speed delay phase-locked loop, including automatic frequency calibration
Algoritic module, chain of delay, four-divider, phase discriminator, sample circuit, charge pump, wave filter, voltage regulator and biased electrical
Press generation circuit；Automatic frequency calibration algorithm module, for obtaining the sampled result of sample circuit output, sampled result includes four
Input clock and delayed clock after frequency divider frequency dividing；And the output voltage of voltage regulator and bias voltage is set to produce electricity
The output on road；Chain of delay, for the output voltage according to voltage regulator, wave filter delay control voltage and high speed when
Clock generates input clock and delayed clock；Four-divider, for carrying out two divided-frequency twice respectively to input clock and delayed clock,
So as to complete the reduction of speed of four frequency dividings, the speed of input clock and delayed clock is set to be down to the speed that phase discriminator is correctly handled；
Phase discriminator, for carrying out phase demodulation to the input clock after reduction of speed and delayed clock, and correspondingly phase error is exported to charge pump
Signal；Charge pump, for phase error signal to be converted into current signal, wave filter generates delay control electricity according to current signal
Pressure.
Preferably, chain of delay forms link using the variable phase inverter of multilevel delay, and the time delay of phase inverter leads to
The output voltage of voltage regulator and the delay control voltage of wave filter are adjusted respectively, the output voltage of voltage regulator
Corresponding delay coarse adjustment, the delay control voltage of wave filter correspondingly postpone fine tuning.
Preferably, the phase discriminator input clock later to reduction of speed and delayed clock carry out phase demodulation, judge that phase is advanced still
Hysteresis, output phase error signal is to charge pump.
Preferably, the phase error signal that phase discriminator exports is converted into simulation current flow by charge pump, is exported to rear class
Wave filter.
Preferably, supply voltage of the output of voltage regulator as chain of delay, different supply voltages correspondingly prolong
The obstructed delay frequency band of slow link, by selecting different supply voltage values, it is determined that being adapted to the delay frequency band of present output frequency.
Preferably, bias-voltage generating circuit is used to produce two height control voltages, VH in automatic frequency calibration process
And VL, control voltage is configured.
Preferably, sample circuit is used to mutually be sampled the input clock after frequency dividing and delayed clock, so that it is determined that
The precedence relationship of two clocks, sampled result is exported and judged to automatic frequency calibration algorithm module, and then determine frequency band
Selection.
On the other hand a kind of automatic frequency calibration method is provided, comprised the following steps：The output of voltage regulator is set
The output of voltage and bias-voltage generating circuit；Obtain the sampled result of input clock and delayed clock after reduction of speed；According to adopting
Sample result, the delay frequency band required for current input clock frequency is selected, complete automatic frequency calibration.
The present invention utilizes a kind of automatic frequency calibration method, for carrying out correctly delay frequency band to high speed delay phase-locked loop
Selection, selects the appropriate frequency bands being suitable under current application environment, then passes through the closed loop characteristic of high speed delay phase-locked loop again
Loop-locking is carried out, so as to the orthogonal clock output stablized.
Brief description of the drawings
Fig. 1 is high speed delay phase-locked loop overall structure block diagram of the present invention；
Fig. 2 is automatic frequency calibration method schematic diagram of the present invention；
Fig. 3 is time diagram when automatic frequency calibration sampled result of the present invention is 00；
Fig. 4 is time diagram when automatic frequency calibration sampled result of the present invention is 01；
Fig. 5 is time diagram when automatic frequency calibration sampled result of the present invention is 11.
Embodiment
Below by drawings and examples, technical scheme is described in further detail.
Fig. 1 is high speed delay phase-locked loop overall structure block diagram of the present invention.
As shown in figure 1, high speed delay phase-locked loop, including：Automatic frequency calibration algorithm module, chain of delay, four frequency dividings
Device, phase discriminator, sample circuit, charge pump, wave filter, voltage regulator and bias-voltage generating circuit.
Automatic frequency calibration algorithm module is used for the sampled result for obtaining sample circuit output, and sampled result includes four frequency dividings
Input clock and delayed clock after device frequency dividing, and the output voltage and bias-voltage generating circuit of voltage regulator are set
Output；Chain of delay generates defeated according to the output voltage of voltage regulator, the delay control voltage of wave filter and high-frequency clock
Enter clock and delayed clock；Four-divider input clock and delayed clock carry out two divided-frequency twice respectively, so as to complete four frequency dividings
Reduction of speed, the speed of input clock and delayed clock is down to the speed that phase discriminator is correctly handled；After phase discriminator is to reduction of speed
Input clock and delayed clock carry out phase demodulation, and to charge pump output correspondingly phase error signal；Charge pump misses phase
Difference signal is converted into current signal, and wave filter generates delay control voltage according to current signal.
Chain of delay, link is formed using the variable phase inverter of multilevel delay, the time delay of phase inverter can pass through electricity
Voltage Vldo and control voltage Vctrl are adjusted respectively in source, and supply voltage Vldo correspondingly postpones coarse adjustment, control voltage Vctrl
Corresponding delay fine tuning.
Wherein, orthogonal clock takes out inside chain of delay, respectively CLK_I and CLK_Q.
Four-divider, two divided-frequency twice is carried out respectively to input clock CLK_IN and delayed clock CLK_OUT, so as to complete
The reduction of speed of four frequency dividings, enables the speed of input clock and delayed clock to be down to the speed that phase discriminator is correctly handled.
Phase discriminator, the input clock CLK_IN4 later to reduction of speed and delayed clock CLK_OUT4 carry out phase demodulation, judge phase
Advanced or hysteresis, output phase error signal UP/DOWN is to charge pump.
Charge pump, the phase error signal UP/DOWN that phase discriminator exports is converted into simulation current flow Ich, exported to after
The wave filter of level.
Wave filter, the current signal for being exported to charge pump carry out Integral Processing, obtain a stable magnitude of voltage, should
Delay control voltage Vctrl of the voltage as chain of delay, the retardation of chain of delay is determined, after Vctrl is stable, just
Hand over clock can be to be taken out from delay cell link.
Voltage regulator, it is exported corresponds to delay chain as the supply voltage Vldo, different Vldo of chain of delay
Obstructed delay frequency band, by selecting different Vldo values, it is determined that being adapted to the delay frequency band of present output frequency.
Bias-voltage generating circuit, it is right for producing two height control voltages, VH and VL in automatic frequency calibration process
Control voltage Vctrl is configured.
Sample circuit is used to mutually be sampled the input clock CLK_IN4 after frequency dividing and delayed clock CLK_OUT4,
So that it is determined that the precedence relationship of two clocks, sampled result is exported and judged to automatic frequency calibration algorithm, and then determine
The selection of frequency band.
Automatic frequency calibration algorithm module, electricity is produced by the output voltage Vldo and bias voltage that set voltage regulator
The output on road, after the input clock after obtaining reduction of speed and the sampled result of delayed clock, according to sampled result, select and work as
Delay frequency band required for preceding input clock frequency, complete the function of automatic frequency calibration.
Including two loops in whole delay phase-locked loop, first loop is frequency band selection loop, including chain of delay,
Four-divider, sample circuit, voltage regulator, bias-voltage generating circuit, automatic frequency calibration algorithm module.Second loop
For analog closed-loop fine tuning loop, including chain of delay, four-divider, phase discriminator, charge pump, wave filter, voltage regulator.Two
Individual loop common sparing module, successively works.
Fig. 2 is automatic frequency calibration method schematic diagram of the present invention.
As shown in Fig. 2 frequency band selection loop first works, performed by the order of automatic frequency calibration algorithm.Selection frequency first
Rate highest frequency band, i.e. regulated output voltage are adjusted to highest, now chain of delay corresponding most short time delay.It is high
Fast clock CLK is handled by chain of delay, obtains input clock CLK_IN and delayed clock CLK_OUT, due to CLK_IN and
CLK_OUT frequency is equal to maximum clock frequency, and general phase discriminator is extremely difficult to the phase demodulation speed suitable with this, therefore, first right
CLK_IN and CLK_OUT carries out identical four scaling down processing, two clocks is obtained by identical frequency dividing path
Four frequency-dividing clocks of two clocks, respectively CLK_IN4 and CLK_OUT4.By bias-voltage generating circuit successively be arranged to VH and
VL two control voltages of height, resulting clock sampling value records when control voltage Vctrl is equal into the two high-low voltages
Get off.Circulate selection for the first time is frequency highest frequency band, and gained sequential is as shown in Figure 3.CLK_OUTH and CLK_OUTL points
Vctrl is not corresponded to equal to the CLK_OUT output clocks under the conditions of VH and VL, and CLK_OUT4H and CLK_OUT4L correspond to CLK_ respectively
OUTH and CLK_OUTL tetra- export clock after dividing, because this frequency band be frequency highest subband, therefore, CLK_OUT4H with
CLK_OUT4L is 0 to CLK_IN4 rising edge sampled result, and sampled value corresponding to this frequency band is exactly 00.Then, frequency band is made
Number subtracts 1, is once again set up bias-voltage generating circuit, obtains the clock after CLK_IN and CLK_OUT tetra- is divided in the same way
Sampled result and preservation.The traversal of all frequency bands is completed by this operation, until frequency band number is kept to 0, stops circulation.
In whole ergodic process, sampled result can occur according to 00,01,11 order, respectively corresponding diagram 3, Fig. 4, Fig. 5
Three kinds of situations.Sampled result 00 and 11 represents present band when no matter why control voltage is worth, delayed clock CLK_OUT phase
Capital is advanced or lags behind input clock CLK_IN, and both of these case imply that analog closed-loop can not be locked in target delay scope
Interior, control voltage Vctrl can exceed the voltage range that ceiling voltage VH and minimum voltage VL is limited.Therefore, sampled result is made
Target sub-band is only for 01 frequency band, in the subband, control voltage can guarantee that analog closed-loop is locked not over preset range
After fixed, CLK_OUT has the delay of just a cycle relative to CLK_IN.
After frequency band selection loop work is completed, it is determined that the output voltage Vldo of voltage regulator, now, it is possible to cut
Analog closed-loop fine tuning loop work is shifted to, the closed-loop stabilization characteristic that the process fully relies on analog circuit is controlled voltage
Vctrl locking.Four frequency-dividing clock CLK_IN4 and CLK_OUT4 are carried out phase error comparison by phase discriminator, obtain it is advanced with it is stagnant
Data signal UP/DOWN afterwards, it by digital signal transition is simulation current flow to control charge pump, is obtained by the integral characteristic of wave filter
The control that the control voltage stable to one is postponed to chain of delay, complete the generating process of whole orthogonal clock.
Above-described embodiment, the purpose of the present invention, technical scheme and beneficial effect are carried out further
Describe in detail, should be understood that the embodiment that the foregoing is only the present invention, be not intended to limit the present invention
Protection domain, within the spirit and principles of the invention, any modification, equivalent substitution and improvements done etc., all should include
Within protection scope of the present invention.
Claims (8)
- A kind of 1. high speed delay phase-locked loop, it is characterised in that including automatic frequency calibration algorithm module, chain of delay, four points Frequency device, phase discriminator, sample circuit, charge pump, wave filter, voltage regulator and bias-voltage generating circuit；The automatic frequency calibration algorithm module, for obtaining the sampled result of sample circuit output, the sampled result includes Input clock and delayed clock after four-divider frequency dividing；And the output voltage of the voltage regulator and the biasing are set The output of voltage generation circuit；The chain of delay, the delay control voltage for the output voltage according to the voltage regulator, the wave filter Input clock and delayed clock are generated with high-frequency clock；The four-divider, for carrying out two divided-frequency twice respectively to the input clock and the delayed clock, so as to complete The reduction of speed of four frequency dividings, enables the speed of input clock and delayed clock to be down to the speed that phase discriminator is correctly handled；The phase discriminator, for carrying out phase demodulation to the input clock after reduction of speed and delayed clock, and phase is exported to the charge pump Should ground phase error signal；The charge pump, for the phase error signal to be converted into current signal, the wave filter is believed according to the electric current Number generation delay control voltage.
- 2. high speed delay phase-locked loop as claimed in claim 1, it is characterised in that the chain of delay can using multilevel delay The phase inverter of change forms link, and time delay of phase inverter passes through the output voltage of the voltage regulator and the wave filter Delay control voltage is adjusted respectively, and the output voltage of the voltage regulator correspondingly postpones coarse adjustment, and the wave filter prolongs Slow control voltage correspondingly postpones fine tuning.
- 3. high speed delay phase-locked loop as claimed in claim 1, it is characterised in that during the phase discriminator input later to reduction of speed Clock and delayed clock carry out phase demodulation, judge phase in advance or lag, output phase error signal is to charge pump.
- 4. high speed delay phase-locked loop as claimed in claim 1, it is characterised in that the phase that the charge pump exports phase discriminator Error signal is converted into simulation current flow, exports the wave filter to rear class.
- 5. high speed delay phase-locked loop as claimed in claim 1, it is characterised in that the output of the voltage regulator is as delay The supply voltage of cellular chain, different supply voltages corresponds to the obstructed delay frequency band of delay chain, by selecting different power supplys Magnitude of voltage, it is determined that being adapted to the delay frequency band of present output frequency.
- 6. high speed delay phase-locked loop as claimed in claim 1, it is characterised in that the bias-voltage generating circuit is used for automatic Two height control voltages, VH and VL are produced in frequency calibration procedure, control voltage is configured.
- 7. high speed delay phase-locked loop as claimed in claim 1, it is characterised in that the sample circuit is used for will be defeated after frequency dividing Enter clock and delayed clock is mutually sampled, so that it is determined that the precedence relationship of two clocks, sampled result is exported to automatic Frequency calibration algoritic module is judged, and then determines the selection of frequency band.
- A kind of 8. automatic frequency calibration method, it is characterised in that applied to high speed delay phase-locked loop as claimed in claim 1, Comprise the following steps：The output of the output voltage and bias-voltage generating circuit of voltage regulator is set；Obtain the sampled result of input clock and delayed clock after reduction of speed；According to sampled result, the delay frequency band required for current input clock frequency is selected, completes automatic frequency calibration.
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Cited By (1)
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| CN111812619A (en) * | 2020-06-23 | 2020-10-23 | 深圳市精嘉微电子有限公司 | Device and method for measuring edge arrival time of picosecond-level resolution electric signal |
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