CN119341523A - DCC circuit - Google Patents
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- CN119341523A CN119341523A CN202411891373.2A CN202411891373A CN119341523A CN 119341523 A CN119341523 A CN 119341523A CN 202411891373 A CN202411891373 A CN 202411891373A CN 119341523 A CN119341523 A CN 119341523A
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Abstract
本发明公开了一种DCC电路，属于集成电路领域。为提升调节范围，本发明的DCC电路接收输入时钟并获得输出时钟，DCC电路包括若干DCDL、第一选择模块、第二选择模块和相位插值器，每个DCDL均包括n条延迟支线和多路选择器；输入时钟经过若干DCDL后产生多个延迟时钟；多个延迟时钟作为第一选择模块的输入信号和第二选择模块的输入信号，分别生成第一插值输入信号和第二插值输入信号；第一插值输入信号和第二插值输入信号作为相位插值器的输入信号，相位插值器生成所述输出时钟；n条延迟支线分别包括数量各不相等的反相器；根据输入时钟的频率，选定n条延迟支线中的一条延迟支线，作为多路选择器的输出通路。本发明的调节范围更广泛，使用频率范围更宽。
The present invention discloses a DCC circuit, which belongs to the field of integrated circuits. In order to improve the adjustment range, the DCC circuit of the present invention receives an input clock and obtains an output clock. The DCC circuit includes a plurality of DCDLs, a first selection module, a second selection module and a phase interpolator, and each DCDL includes n delay branches and a multiplexer; the input clock generates a plurality of delayed clocks after passing through a plurality of DCDLs; the plurality of delayed clocks are used as input signals of the first selection module and the second selection module, respectively generating a first interpolation input signal and a second interpolation input signal; the first interpolation input signal and the second interpolation input signal are used as input signals of the phase interpolator, and the phase interpolator generates the output clock; the n delay branches respectively include inverters of different numbers; according to the frequency of the input clock, one of the n delay branches is selected as the output path of the multiplexer. The adjustment range of the present invention is wider and the use frequency range is wider.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a DCC circuit.
Background
Register clock drivers (Register Clock Driver, RCD) are key components that make up a registered dual in-line memory module (REGISTERED DUAL IN-Line Memory Module, RDIMM), and play a central role in timing and clock signal management and optimization within the memory module.
The main function of the RCD involves receiving the instruction from the cpu and performing preprocessing, and as a bridge for communication between the cpu and the RDIMM, performing tasks including timing correction, clock signal amplification, delay management, and signal distribution, and generally, cooperating with a Data Buffer (DB), to improve the stability and operation performance of the memory. The internal structure of the RCD integrates key technical links such as a clock distribution logic unit, a time sequence control module, a clock amplifying component, a delay line and the like.
Clock duty cycle calibration (Duty Cycle Calibration, DCC) circuits play an important role as an advanced clock management technique. Fig. 1 is a prior art DCC circuit diagram. The DCC circuit encompasses metal oxide semiconductor (Metal Oxide Semiconductor, MOS) transistors M0, M1, M2, M3, M4, M5, M6, M7, as well as an input clock CKIN, an intermediate clock CKMID, and an output clock CKOUT.
The basic goal of the DCC circuit design is to utilize the fine adjustment of the current intensities of the MOS transistors M2, M3, M6, and M7 to realize the precise control of the edge slew rates (i.e., rising edge and falling edge slopes) of the intermediate clock CKMID and the output clock CKOUT clock, so as to ensure that the duty cycle of the output clock CKOUT accurately reaches the desired value, such as 50%. The adjusting process is realized by changing the parallel configuration of the MOS transistors M2 to M7 or adjusting the grid voltage, so that the balance of pull-up current and pull-down current is precisely controlled, and the transition characteristic of the clock edge is effectively managed.
However, current schemes suffer from regulatory range limitations, poor linear response, and direct intervention in the edge transition process makes the system more sensitive to power supply noise, especially during slow edge transitions.
Because the current scheme realizes the adjustment of the duty ratio by directly adjusting the rising edge falling edge rising time, if a larger adjustment range is required to be obtained, the slower rising edge falling edge rising time is required to be relied on. The effect of noise becomes greater as the climb time becomes longer, whether random jitter or deterministic jitter.
In addition, different adjustment configurations may lead to output phase deviations, which constitute a non-negligible problem in high-precision delay control applications.
Therefore, developing a solution with a wider adjustment range, better linearity and stronger power supply noise suppression capability becomes an urgent need in the field.
Disclosure of Invention
In order to alleviate or partially alleviate the above technical problem, the solution of the present invention is as follows:
The DCC circuit receives an input clock and obtains an output clock, the DCC circuit comprises a plurality of DCDL, a first selection module, a second selection module and a phase interpolator, each DCDL comprises n delay branches and a multiplexer, n is a positive integer larger than 1, the input clock generates a plurality of delay clocks after passing through the DCDL, the delay clocks serve as input signals of the first selection module and input signals of the second selection module to respectively generate a first interpolation input signal and a second interpolation input signal, the first interpolation input signal and the second interpolation input signal serve as input signals of the phase interpolator, the phase interpolator generates the output clock, in addition, the n delay branches respectively comprise inverters with different numbers, and one delay branch of the n delay branches is selected as an output path of the multiplexer according to the frequency of the input clock.
Further, when the frequency of the input clock becomes high, a delay branch line with a smaller number of inverters is selected as an output path of the multiplexer, and when the frequency of the input clock becomes low, a delay branch line with a larger number of inverters is selected as an output path of the multiplexer.
Further, the rising edge of the first interpolation input signal and the rising edge of the second interpolation input signal are aligned with the rising edge of one delay clock of the plurality of delay clocks, the first selection module and the second selection module comprise an OR gate and an AND gate, so that the generated falling edge of the first interpolation input signal and the generated falling edge of the first interpolation input signal can form a plurality of continuous sections, wherein the plurality of continuous sections comprise a first section and a second section adjacent to the first section, the second interpolation input signal used for forming the first section and the second interpolation input signal used for forming the second section are generated in the same generation mode, the plurality of continuous sections comprise a third section adjacent to the second section, and the first interpolation input signal used for forming the second section and the first interpolation input signal used for forming the third section are generated in the same generation mode.
Further, the manner of generating the first or second interpolation input signal includes directly taking one of the plurality of delay clocks as the first or second interpolation input signal.
Further, the phase interpolator comprises a first set of tri-state gates and a second set of tri-state gates, the control code is converted into a first thermometer code and a second thermometer code through a transcoding module, the first set of tri-state gates are controlled through the first thermometer code, the second set of tri-state gates are controlled through the second thermometer code, and the second thermometer code is generated by inputting the first thermometer code into at least a first inverter.
Further, the first interpolation input signal is used as the input signal of the first group of three-state gates, the second interpolation input signal is used as the input signal of the second group of three-state gates, the output signal of the first group of three-state gates and the output signal of the second group of three-state gates are used as the input signals of the second inverter, and the output signal of the second inverter is an output clock.
Further, the DCC circuit is applied in a clock sampling scenario.
Further, the DCC circuit is applied in a register clock driver.
The technical scheme of the invention has one or more of the following beneficial technical effects:
(1) The input clock dcc_in has a suitable and large duty cycle adjustment range over a wide frequency range.
(2) The applicable frequency range is wide, the implementation can be controlled through the digital register, and the scheme is reliable and effective.
(3) The duty ratio adjustment is realized through the logic gate instead of the traditional mode of analog current adjustment, so that the method is more stable and reliable, has stronger resistance to capacitive noise and better power consumption.
(4) The digital CMOS logic gate is adopted for implementation, the structure is simple and clear, and the adjusting range and the linearity are better than those of the traditional prior art.
(5) The thermometer code is used for controlling the phase interpolator, so that better linearity is ensured, the rising edge of the output clock DCC_OUT is not influenced by the adjusting gear, the thermometer code is suitable for RCD and other scenes needing clock sampling, coarse adjustment of a logic gate and fine adjustment of the phase interpolator are realized, and the clock signal is controlled more accurately.
Furthermore, other advantageous effects that the present invention has will be mentioned in the specific embodiments.
Drawings
FIG. 1 is a diagram of a prior art DCC circuit;
FIG. 2 is a schematic diagram of a DCC circuit configuration of the present invention;
FIG. 3 is a schematic diagram of a DCDL structure;
FIG. 4 is a timing diagram of signals according to the present invention;
Fig. 5 is a circuit diagram of a phase interpolator of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order to clearly describe the technical solution of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. Those skilled in the art will appreciate that the words "first," "second," and the like do not limit the number and order of execution.
Fig. 2 is a schematic diagram of the DCC circuit structure of the present invention, an input clock dcc_in of the DCC circuit, and an output clock dcc_out of the DCC circuit. The DCC circuit includes several digitally controlled delay chains (DIGITALLY CONTROLLED DELAY LINES, DCDL) and DCDL is used to generate the same delay. The DCDL in the invention can be used for expanding the applicable clock frequency range of the DCC circuit.
The input clock dcc_in passes through a plurality of DCDLs to generate a plurality of delay clocks. Illustratively, setting a 4-way DCDL will produce a 5-way delay clock. The 5 delay clocks dcc_dly0, dcc_dly1, dcc_dly2, dcc_dly3, and dcc_dly4 are each fed into the first selection block and the second selection block, respectively, as input signals to perform timing control, and to obtain a first interpolation input signal dcc_x and a second interpolation input signal dcc_y for interpolation to obtain the falling edge of the output clock dcc_out, respectively.
The first interpolation input signal dcc_x and the second interpolation input signal dcc_y are input to a phase interpolator (Phase Interpolator, PI) by which an output clock dcc_out of the DCC circuit is obtained. In the phase interpolator, the falling edge of the output clock dcc_out is used for adjustment. The output clock dcc_out is the duty cycle adjusted target clock. The rising edge of the first interpolation input signal dcc_x and the rising edge of the second interpolation input signal dcc_y are aligned.
IN addition, dcc_dly0 is a clock of one path directly led out from the input clock dcc_in without any delay unit.
Further, the input clock dcc_in is a clock that requires the DCC circuit to adjust the duty cycle, and its source may be a phase locked loop or other clock path.
Fig. 3 is a schematic diagram of DCDL structure. Illustratively, the DCDL includes n delay legs, wherein a first delay leg illustratively includes 2 inverters, a second delay leg illustratively includes 4 inverters, an n delay leg illustratively includes 2n inverters, n is a positive integer greater than 1. In other words, the n delay legs include an unequal number of inverters to produce n different delays.
The n delay branch lines all receive the clock CLK_IN to be delayed, the output of the n delay branch lines serves as the input of the multiplexer, the output path of the multiplexer is controlled through the configuration register, one delay branch line is selected to be connected to the output end of the DCDL, and the delayed clock CLK_OUT is output.
By controlling the output path of the multiplexer, a delay leg with a smaller delay can be selected when the frequency of the input clock dcc_in is higher. Conversely, when the frequency of the input clock dcc_in is low, a delay branch line with a larger delay may be selected. The technical means has the advantages that the input clock dcc_in has a proper and large duty ratio adjusting range IN a wide frequency range.
FIG. 4 is a timing diagram of signals according to the present invention. The rising edge of the first interpolation input signal dcc_x and the rising edge of the second interpolation input signal dcc_y are each aligned with the rising edge of one of the plurality of delay clocks.
Illustratively, the rising edge of dcc_dly2 may be taken as the rising edge of the final DCC circuit output clock dcc_out, and the falling edge of DCC circuit output clock dcc_out may be generated by the falling edges of two delay clocks of dcc_dly0, dcc_dly1, dcc_dly2, dcc_dly3, and dcc_dly4 through the phase interpolator.
The falling edge of the output clock dcc_out falls within a first interval, a second interval, a third interval, or a fourth interval depending on the duty ratio of the target. The first section, the second section, the third section, and the fourth section are divided by the first interpolation input signal dcc_x and the second interpolation input signal dcc_y output from the first selection module and the second selection module, respectively.
Illustratively, in circuit value calculation logic, the first and second interpolation input signals dcc_x and dcc_y are generated by an or gate and an and gate:
a first interval:
;
the second interval:
;
third interval:
;
Fourth interval:
;
wherein the symbol is' "Representation and logic, symbol""Means or logic. Dcc_x=0 in fig. 4 for ease of reading2 Is "dcc_x=dcc_dly0" as described aboveDcc_dly2", dcc_x=2 are the abbreviations of the above-mentioned" dcc_x=dcc_dly 2", and other abbreviations are similar.
It is apparent that the first interpolation input signal dcc_x or the second interpolation input signal dcc_y in adjacent sections is kept unchanged, which results in continuity of sections, increases linearity at the time of section switching, and reduces circuit complexity.
In other words, in the first selecting module and the second selecting module, an or gate and an and gate are included, so that the generated falling edge of the first interpolation input signal dcc_x and the falling edge of the first interpolation input signal dcc_x may form a plurality of continuous sections, wherein the plurality of continuous sections include a first section and a second section adjacent to the first section.
Further, the second interpolation input signal dcc_y for forming the first section and the second interpolation input signal dcc_y for forming the second section are generated by the same generation method.
The plurality of continuous sections include a third section adjacent to the second section, and the first interpolation input signal dcc_x for forming the second section and the first interpolation input signal dcc_x for forming the third section are generated in the same generation manner.
For example, it is also possible to directly take one of a plurality of delay clocks as the first interpolation input signal dcc_x or the second interpolation input signal dcc_y.
Fig. 5 is a circuit diagram of a phase interpolator of the present invention. The phase interpolator circuit includes a first set of tri-state gates and a second set of tri-state gates. Wherein the first set of tri-state gates is controlled by a first thermometer code THM <15:0>, and the second set of tri-state gates is controlled by a second thermometer code THM_B <15:0 >. Illustratively, the first set of tri-state gates and the second set of tri-state gates each include a number of tri-state gates, illustratively, 16 tri-state gates. The invention can control the interpolation quantity through the thermometer code, and ensure that the opening of the tri-state gate used for interpolation is linear.
Further, the first thermometer code THM <15:0> and the second thermometer code THM_B <15:0> are mutually opposite signals. As a signal inversion technique conventional in the art, the second set of tri-state gates may be controlled by inputting the first thermometer code THM <15:0> into at least a first inverter (not shown in fig. 5) to generate the second thermometer code thm_b <15:0>, and further by the second thermometer code thm_b <15:0 >.
The first interpolation input signal dcc_x and the second interpolation input signal dcc_y are input signals to the phase interpolator and are weighted by the first thermometer code THM <15:0> and the second thermometer code thm_b <15:0>, respectively. Specifically, the first interpolated input signal dcc_x is used as an input signal for the first set of tri-state gates and the second interpolated input signal dcc_y is used as an input signal for the second set of tri-state gates. The output signals of the first set of tri-state gates and the output signals of the second set of tri-state gates are used as input signals of a second inverter (rightmost inverter in fig. 5), and the output signals of the second inverter are output clocks dcc_out.
With the increase of the adjustment gear, the falling edge synthesized by the first interpolation input signal dcc_x and the second interpolation input signal dcc_y will move backward, and since the rising edges of the first interpolation input signal dcc_x and the second interpolation input signal dcc_y are fixed, with the change of the adjustment gear, the falling edge of the output clock dcc_out also changes, but the rising edge of the output clock dcc_out is unchanged, that is, the duty ratio of the output clock dcc_out can be adjusted by the first thermometer code and the second thermometer code.
The invention provides a DCC circuit applied to a clock path of a fifth generation Double Data Rate synchronous dynamic random access memory (Double Data Rate 5th-generation Synchronous Dynamic Random Access Memory, DDR SDRAM) protocol. The design can effectively adjust and maintain the duty ratio of the clock path by virtue of the high-precision and high-linearity characteristics, and ensure the high quality of the output clock signal.
Numerous specific details are set forth in the above description in order to provide a better illustration of the invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
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| CN202411891373.2A CN119341523B (en) | 2024-12-20 | 2024-12-20 | DCC circuit |
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| JP2002190733A (en) * | 2000-12-21 | 2002-07-05 | Toshiba Corp | Clock synchronization circuit for phase compensation |
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| US20150188527A1 (en) * | 2013-12-27 | 2015-07-02 | Erin D. FRANCOM | Apparatus for a monotonic delay line, method for fast locking of a digital dll with clock stop/start tolerance, apparatus and method for robust clock edge placement, and apparatus and method for clock offset tuning |
| CN112335180A (en) * | 2018-12-14 | 2021-02-05 | 英特尔公司 | High speed digital phase interpolator with duty cycle correction circuit |
| CN113328733A (en) * | 2021-06-10 | 2021-08-31 | 中国科学院微电子研究所 | Duty ratio calibration circuit and method |
-
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- 2024-12-20 CN CN202411891373.2A patent/CN119341523B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002190733A (en) * | 2000-12-21 | 2002-07-05 | Toshiba Corp | Clock synchronization circuit for phase compensation |
| JP3854065B2 (en) * | 2000-12-21 | 2006-12-06 | 株式会社東芝 | Phase compensation clock synchronization circuit |
| US20100039157A1 (en) * | 2006-09-13 | 2010-02-18 | Shunichi Kaeriyama | Clock adjusting circuit and semiconductor integrated circuit device |
| US20080169852A1 (en) * | 2007-01-11 | 2008-07-17 | Jun-Bae Kim | Delay locked loop circuits and method for controlling the same |
| US20150188527A1 (en) * | 2013-12-27 | 2015-07-02 | Erin D. FRANCOM | Apparatus for a monotonic delay line, method for fast locking of a digital dll with clock stop/start tolerance, apparatus and method for robust clock edge placement, and apparatus and method for clock offset tuning |
| CN112335180A (en) * | 2018-12-14 | 2021-02-05 | 英特尔公司 | High speed digital phase interpolator with duty cycle correction circuit |
| CN113328733A (en) * | 2021-06-10 | 2021-08-31 | 中国科学院微电子研究所 | Duty ratio calibration circuit and method |
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