CN119341522B - Clock duty cycle regulating circuit - Google Patents
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- CN119341522B CN119341522B CN202411891255.1A CN202411891255A CN119341522B CN 119341522 B CN119341522 B CN 119341522B CN 202411891255 A CN202411891255 A CN 202411891255A CN 119341522 B CN119341522 B CN 119341522B
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Abstract
The invention discloses a clock duty cycle adjusting circuit, and belongs to the field of integrated circuits. The clock duty ratio adjusting circuit comprises a plurality of delay units, a first selection module, a second selection module and a phase interpolator, wherein the input clock generates a plurality of delay clocks after passing through the delay units, the plurality of delay clocks are used as input signals of the first selection module to generate first interpolation input signals, the plurality of delay clocks are used as input signals of the second selection module to generate second interpolation input signals, the first interpolation input signals and the second interpolation input signals are used as input signals of the phase interpolator, the phase interpolator generates output clocks, and rising edges of the first interpolation input signals and rising edges of the second interpolation input signals are aligned with rising edges of one delay clock of the plurality of delay clocks. The clock duty ratio regulating circuit has wider regulating range and better linearity.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a clock duty cycle adjusting circuit.
Background
The register clock driver (Register Clock Driver, RCD) is a core component for dual in-line memory modules (REGISTERED DUAL IN-Line Memory Module, RDIMM) with registers, responsible for managing and optimizing timing and clock signal transmissions within the memory modules. The core responsibility is to relay instructions from the central processing unit (Central Processing Unit, CPU) to perform the necessary processing before the information is transferred to the memory module. As an intermediary between the CPU and the RDIMM, the RCD performs functions such as timing adjustment, clock signal enhancement, delay control, and signal distribution, and typically cooperates with a Data Buffer (DB) to enhance the stability and operating efficiency of the memory. The internal structure of the RCD comprises key components such as clock distribution logic, a time sequence controller, a clock amplifier, a time delay line and the like.
A clock duty cycle adjustment (Duty Cycle Calibration, DCC) circuit is an important clock control circuit. Fig. 1 is a prior art DCC circuit comprising metal oxide semiconductor (Metal Oxide Semiconductor, MOS) transistors M0, M1, M2, M3, M4, M5, M6, and M7, an input clock CKIN, an intermediate clock CKMID, and an output clock CKOUT.
The DCC circuit aims to finely control the clock edge transition time (the slope of the rising edge and the falling edge) of the intermediate clock CKMID and the output clock CKOUT by adjusting the current intensities of the MOS transistors M2, M3, M6, and M7, so as to ensure that the duty cycle of the final output clock CKOUT reaches a preset value, for example, 50%. The implementation way involves changing the parallel number of M2 to M7 or adjusting the grid voltage thereof, thereby realizing accurate control on the pull-up and pull-down current difference and further regulating the transition characteristic of the clock edge.
However, this approach faces problems with limited regulation range, poor linearity, and direct intervention in the edge transition time results in a system that is more sensitive to supply noise, especially when the edges transition slowly. Furthermore, different adjustment settings may cause output phase shifts, which is a impermissible drawback in applications requiring strict delay control.
Based on the above, a solution with wider adjustment range, better linearity and stronger resistance to power supply noise is needed in the art.
Disclosure of Invention
In order to alleviate or partially alleviate the above technical problem, the solution of the present invention is as follows:
The clock duty cycle adjusting circuit receives an input clock and obtains an output clock, the clock duty cycle adjusting circuit comprises a plurality of delay units, a first selection module, a second selection module and a phase interpolator, the input clock generates a plurality of delay clocks after passing through the plurality of delay units, the plurality of delay clocks are used as input signals of the first selection module to generate a first interpolation input signal, the plurality of delay clocks are used as input signals of the second selection module to generate a second interpolation input signal, the first interpolation input signal and the second interpolation input signal are used as input signals of the phase interpolator, the phase interpolator generates the output clock, in addition, rising edges of the first interpolation input signal and rising edges of the second interpolation input signal are aligned with rising edges of one delay clock in the plurality of delay clocks, in the first selection module and the second selection module, the plurality of delay clocks are used as input signals of the first selection module, the plurality of delay clocks are used as input signals of the second selection module, the first interpolation input signals and the second interpolation input signals can form a plurality of continuous interpolation intervals, and the first interpolation intervals and the second interpolation intervals can form the second continuous intervals.
Further, the plurality of consecutive sections includes a third section adjacent to the second section, and the first interpolation input signal for forming the second section and the first interpolation input signal for forming the third section are generated by the same generation method.
Further, the manner of generating the first or second interpolation input signal includes directly taking one of the plurality of delay clocks as the first or second interpolation input signal.
Further, the phase interpolator includes a first set of tri-state gates and a second set of tri-state gates.
Further, the control code is converted into a first thermometer code and a second thermometer code through a transcoding module, the first group of three-state gates are controlled through the first thermometer code, the second group of three-state gates are controlled through the second thermometer code, and the second thermometer code is generated through inputting the first thermometer code into at least a first inverter.
Further, the first interpolated input signal is used as input signal for the first set of tri-state gates and the second interpolated input signal is used as input signal for the second set of tri-state gates.
Further, the output signals of the first set of tri-state gates and the output signals of the second set of tri-state gates are used as input signals of a second inverter, and the output signals of the second inverter are output clocks.
Further, the clock duty cycle adjustment circuit is applied in a clock sampling scenario.
Further, the clock duty cycle adjustment circuit is applied in a fifth generation double data rate synchronous dynamic random access memory protocol clock path.
Further, the clock duty cycle adjustment circuit is applied in a register clock driver. The technical scheme of the invention has one or more of the following beneficial technical effects:
(1) The duty ratio adjustment is realized through the complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) logic gate instead of the traditional mode of analog current adjustment, so that the capacitor is more stable and reliable, has stronger resistance to capacitance noise and better power consumption.
(2) The digital CMOS logic gate is adopted for implementation, the structure is simple and clear, and the adjusting range and the linearity are better than those of the traditional prior art.
(3) A coarse adjustment interval is generated through logic gates in the first selection module and the second selection module, then a fine adjustment gear is generated through a phase interpolator, and the control on the clock signal is more accurate.
(4) Better linearity is ensured by the thermometer code controlled phase interpolator.
(5) The rising edge of the output clock dcc_out is not influenced by the adjusting gear, and is suitable for other scenes needing clock sampling such as RCD.
Furthermore, other advantageous effects that the present invention has will be mentioned in the specific embodiments.
Drawings
FIG. 1 is a diagram of a prior art DCC circuit;
FIG. 2 is a schematic diagram of a delay line;
FIG. 3 is a schematic diagram of a DCC circuit configuration of the present invention;
FIG. 4 is a timing diagram of signals according to the present invention;
FIG. 5 is a schematic diagram of a thermometer code generation module of the present invention;
Fig. 6 is a circuit diagram of a phase interpolator of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order to clearly describe the technical solution of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. Those skilled in the art will appreciate that the words "first," "second," and the like do not limit the number and order of execution.
Fig. 2 is a schematic diagram of a delay line. IN the invention, the input clock dcc_in generates a plurality of delay clocks after passing through a plurality of delay units.
By way of example, the delay time of each delay unit is the same by 4 delay units, and the input clock dcc_in is the 4 delay units IN turn, and the delay line may lead out 5 delay clocks of equal phase difference, dcc_dly0, dcc_dly1, dcc_dly2, dcc_dly3, or dcc_dly4. Wherein dcc_dly0 is a path clock directly led out by the input clock dcc_in without any delay unit. Where the input clock dcc_in is the clock that requires the DCC circuit to adjust the duty cycle, the source may be a phase locked loop or other clock path.
Illustratively, the rising edge of dcc_dly2 may be taken as the rising edge of the final DCC circuit output clock dcc_out, which is then generated by the falling edges of two delay clocks of dcc_dly0, dcc_dly1, dcc_dly2, dcc_dly3, and dcc_dly4 and through the phase interpolators (Phase Interpolator, PI).
Fig. 3 is a schematic diagram of the DCC circuit structure of the present invention. The 5-way delay clocks dcc_dly0, dcc_dly1, dcc_dly2, dcc_dly3, and dcc_dly4 are each fed into the first selection module and the second selection module, respectively, as input signals to perform timing control, and to obtain a first interpolation input signal dcc_x and a second interpolation input signal dcc_y for falling edge interpolation, respectively. The first interpolation input signal dcc_x and the second interpolation input signal dcc_y are used as inputs of a phase interpolator, and the output clock dcc_out of the DCC circuit is obtained through the phase interpolator. The output clock dcc_out is a duty cycle adjusted clock.
FIG. 4 is a timing diagram of signals according to the present invention. The rising edge of the first interpolation input signal dcc_x and the rising edge of the second interpolation input signal dcc_y are each aligned with the rising edge of one of the plurality of delay clocks.
Which interval (first interval, second interval, third interval, or fourth interval) the falling edge of the output clock dcc_out falls in depends on the duty cycle of the target. The first section, the second section, the third section, and the fourth section are divided by the first interpolation input signal dcc_x and the second interpolation input signal dcc_y output from the first selection module and the second selection module, respectively.
Illustratively, in circuit value calculation logic, the first and second interpolation input signals dcc_x and dcc_y are generated by an or gate and an and gate:
A first interval:
;
the second interval:
;
third interval:
;
fourth interval:
;
Wherein the symbol is' "Representation and logic, symbol""Means or logic. Dcc_x=0 in fig. 4 for ease of reading2 Is "dcc_x=dcc_dly0" as described aboveDcc_dly2", dcc_x=2 are the abbreviations of the above-mentioned" dcc_x=dcc_dly 2", and other abbreviations are similar.
It is apparent that the first interpolation input signal dcc_x or the second interpolation input signal dcc_y in adjacent sections is kept unchanged, which results in continuity of sections, increases linearity at the time of section switching, and reduces circuit complexity.
In other words, in the first selecting module and the second selecting module, an or gate and an and gate are included, so that the generated falling edge of the first interpolation input signal dcc_x and the falling edge of the first interpolation input signal dcc_x may form a plurality of continuous sections, wherein the plurality of continuous sections include a first section and a second section adjacent to the first section.
Further, the second interpolation input signal dcc_y for forming the first section and the second interpolation input signal dcc_y for forming the second section are generated by the same generation method.
The plurality of continuous sections include a third section adjacent to the second section, and the first interpolation input signal dcc_x for forming the second section and the first interpolation input signal dcc_x for forming the third section are generated in the same generation manner.
For example, it is also possible to directly take one of a plurality of delay clocks as the first interpolation input signal dcc_x or the second interpolation input signal dcc_y.
FIG. 5 is a schematic diagram of a thermometer code generation module of the present invention. For example, the control code BIN <3:0> comprises 4 bits, and after passing through the transcoding module, a 16-bit first thermometer code THM <15:0> is generated, and after being inverted by at least a first inverter, a second thermometer code thm_b <15:0> is obtained. In other words, the first thermometer code and the second thermometer code are mutually inverted signals. The specific scheme for generating thermometer codes is well known to those skilled in the art and will not be described in detail herein.
Fig. 6 is a circuit diagram of a phase interpolator of the present invention. The phase interpolator circuit includes a first set of tri-state gates and a second set of tri-state gates. Wherein the first set of tri-state gates is controlled by a first thermometer code THM <15:0>, and the second set of tri-state gates is controlled by a second thermometer code THM_B <15:0 >. Illustratively, the first set of tri-state gates and the second set of tri-state gates each include a number of tri-state gates, illustratively, 16 tri-state gates. The invention can control the interpolation quantity through the thermometer code, and ensure that the opening of the tri-state gate used for interpolation is linear.
The first interpolation input signal dcc_x and the second interpolation input signal dcc_y are input signals to the phase interpolator and are weighted by the first thermometer code THM <15:0> and the second thermometer code thm_b <15:0>, respectively. Specifically, the first interpolated input signal dcc_x is used as an input signal for the first set of tri-state gates and the second interpolated input signal dcc_y is used as an input signal for the second set of tri-state gates. The output signals of the first group of tri-state gates and the output signals of the second group of tri-state gates are used as input signals of a second inverter, and the output signals of the second inverter are output clocks DCC_OUT.
With the increase of the adjustment gear, the falling edge synthesized by the first interpolation input signal dcc_x and the second interpolation input signal dcc_y will move backward, and since the rising edges of the first interpolation input signal dcc_x and the second interpolation input signal dcc_y are fixed, different adjustment gears are generated with the change of the control code BIN <3:0>, the falling edge of the output clock dcc_out also changes, but the rising edge of the output clock dcc_out is unchanged, that is, the duty ratio of the output clock dcc_out can be adjusted by the control code BIN <3:0 >.
The invention provides a DCC circuit applied to a clock path of a fifth generation Double Data Rate synchronous dynamic random access memory (Double Data Rate 5th-generation Synchronous Dynamic Random Access Memory, DDR SDRAM) protocol. The design can effectively adjust and maintain the duty ratio of the clock path by virtue of the high-precision and high-linearity characteristics, and ensures the high quality of the output clock signal.
Numerous specific details are set forth in the above description in order to provide a better illustration of the invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A clock duty cycle adjustment circuit that receives an input clock and obtains an output clock, characterized in that:
The clock duty cycle adjusting circuit comprises a plurality of delay units, a first selection module, a second selection module and a phase interpolator;
after the input clock passes through a plurality of delay units, generating a plurality of delay clocks;
the plurality of delay clocks are used as input signals of a first selection module to generate a first interpolation input signal;
the plurality of delay clocks are used as input signals of a second selection module to generate second interpolation input signals;
The first and second interpolated input signals serve as input signals for a phase interpolator, which generates the output clock, and furthermore,
The rising edge of the first interpolated input signal and the rising edge of the second interpolated input signal are both aligned with the rising edge of one of the plurality of delay clocks;
In the first selection module and the second selection module, each comprises an OR gate and an AND gate, so that the generated falling edge of the first interpolation input signal and the falling edge of the first interpolation input signal can form a plurality of continuous sections, wherein the plurality of continuous sections comprise a first section and a second section adjacent to the first section, and
The second interpolation input signal for forming the first section and the second interpolation input signal for forming the second section are generated by the same generation method.
2. The clock duty cycle adjustment circuit of claim 1, wherein:
the plurality of consecutive intervals includes a third interval adjacent to the second interval;
The first interpolation input signal for forming the second section and the first interpolation input signal for forming the third section are generated by the same generation method.
3. The clock duty cycle adjustment circuit of claim 2, wherein:
the manner of generating the first or second interpolated input signal includes:
one of the plurality of delay clocks is directly used as a first interpolation input signal or a second interpolation input signal.
4. A clock duty cycle adjustment circuit as claimed in claim 3, wherein:
the phase interpolator includes a first set of tri-state gates and a second set of tri-state gates.
5. The clock duty cycle adjustment circuit of claim 4, wherein:
Converting the control code into a first thermometer code and a second thermometer code through a transcoding module;
Controlling a first group of tri-state gates through a first thermometer code, and controlling a second group of tri-state gates through a second thermometer code;
The second thermometer code is generated by inputting the first thermometer code into at least a first inverter.
6. The clock duty cycle adjustment circuit of claim 5, wherein:
The first interpolated input signal is used as input signal for the first set of tri-state gates and the second interpolated input signal is used as input signal for the second set of tri-state gates.
7. The clock duty cycle adjustment circuit of claim 6, wherein:
the output signals of the first group of tri-state gates and the output signals of the second group of tri-state gates are used as input signals of a second inverter, and the output signals of the second inverter are output clocks.
8. The clock duty cycle adjustment circuit of claim 7, wherein:
The clock duty cycle adjusting circuit is applied to a clock sampling scene.
9. The clock duty cycle adjustment circuit of claim 7, wherein:
The clock duty cycle adjustment circuit is applied to a fifth generation double data rate synchronous dynamic random access memory protocol clock path.
10. The clock duty cycle adjustment circuit of claim 7, wherein:
the clock duty cycle adjustment circuit is applied to a register clock driver.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202411891255.1A CN119341522B (en) | 2024-12-20 | 2024-12-20 | Clock duty cycle regulating circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202411891255.1A CN119341522B (en) | 2024-12-20 | 2024-12-20 | Clock duty cycle regulating circuit |
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| CN119341522A CN119341522A (en) | 2025-01-21 |
| CN119341522B true CN119341522B (en) | 2025-03-14 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115223607A (en) * | 2021-04-20 | 2022-10-21 | 三星电子株式会社 | Quadrature error correction circuit and semiconductor memory device including the same |
| CN116827316A (en) * | 2023-07-11 | 2023-09-29 | 合芯科技(苏州)有限公司 | Clock signal duty cycle regulating circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3854065B2 (en) * | 2000-12-21 | 2006-12-06 | 株式会社東芝 | Phase compensation clock synchronization circuit |
| US9124257B2 (en) * | 2011-12-29 | 2015-09-01 | Intel Corporation | Digital clock placement engine apparatus and method with duty cycle correction and quadrature placement |
| CN116820185B (en) * | 2023-08-25 | 2023-11-17 | 高澈科技(上海)有限公司 | Programmable multiphase clock device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115223607A (en) * | 2021-04-20 | 2022-10-21 | 三星电子株式会社 | Quadrature error correction circuit and semiconductor memory device including the same |
| CN116827316A (en) * | 2023-07-11 | 2023-09-29 | 合芯科技(苏州)有限公司 | Clock signal duty cycle regulating circuit |
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