CN119133220A - A GaN transistor structure and preparation method thereof - Google Patents

Abstract

The invention discloses a GaN transistor structure and a preparation method thereof, wherein a grid electrode in the GaN transistor is of a closed frame structure, and surrounds a source electrode, so that the drain electrode and the source electrode can be thoroughly isolated, the electric field distribution between the grid electrode and a channel is optimized, the forward bias grid voltage of the transistor is obviously improved, the formation of a leakage channel is effectively restrained, the leakage current is greatly reduced, and the stability and the reliability of a device in a circuit are enhanced. In addition, the grid electrode adopting the structure can optimize the electric field distribution around the grid electrode, reduce the generation and propagation paths of high-energy electrons, and remarkably enhance the robustness of the grid electrode under the high-temperature condition, thereby effectively inhibiting the damage of impact ionization effect on the grid electrode.

Description

GaN transistor structure and preparation method thereof

Technical Field

The invention belongs to the field of semiconductor device design, and particularly relates to a GaN transistor structure and a preparation method thereof.

Background

High Electron Mobility Transistors (HEMTs) are widely used in high frequency and high power electronic devices, and have been attracting attention because they exhibit excellent electrical characteristics in high frequency, high power and high temperature environments. However, the conventional HEMT structure still faces many challenges under specific conditions, and the phenomenon of gate leakage current surge easily occurs under high temperature or strong electric field. This is mainly due to the increased gate leakage current (non-source current) caused by impact ionization effects, which severely affects the stability and reliability of the device. Referring to fig. 1, especially, the gate leakage current of the conventional GaN HEMT (gallium nitride high electron mobility transistor) is greatly affected by the mechanisms of generating photo-generated carriers, charging and discharging the surface state, filling and releasing the trap state, and the like, so as to increase the gate leakage current.

In order to solve the above technical problems, in the prior art, gaN HEMT design introduces optimization such as high-K dielectric material, passivation layer and field plate, electric field distribution, etc. into the structure, for example, high-K dielectric material such as HfO ₂ (hafnium oxide) and Al ₂O₃ (aluminum oxide) is deposited in the gate region, which is used to replace traditional SiO ₂ (silicon nitride) or Si ₃N₄. The high-K dielectric material has higher dielectric constant, can realize the same channel modulation effect under lower gate voltage and reduce leakage current and gate voltage stress, and is deposited by depositing a passivation layer (such as SiN (silicon nitride) and AlN (aluminum nitride)) on the GaN surface and an AlGaN (aluminum gallium nitride)/GaN heterojunction interface, wherein the passivation layer can reduce the surface state density and the gate leakage current. The grid electrode region adopts a double-layer metal grid electrode structure, the upper layer is grid electrode metal, and the lower layer is a protective metal layer under the grid electrode. An insulating layer is sandwiched between two layers of metal, and a gate is buried in GaN material, and a passivation layer is covered over the gate. The buried gate design reduces the surface electric field source by changing the electric field distribution, the polar field plate design is that a field plate is added in the source electrode area, the source electrode field plate is combined with the grid electrode field plate for use, the electric field distribution is further optimized, and the like.

In addition, the conventional HEMT structure is composed of an AlGaN/GaN heterojunction, which grows a GaN layer on a buffer layer as a main conductive path, and deposits a layer of AlGaN on the GaN layer to form a high-density, high-mobility two-dimensional electron gas (2 DEG), thereby providing high conductivity and low on-resistance. This structure makes HEMTs have wide prospects in high voltage and high frequency applications. However, under high temperature or strong electric field environments, the conventional HEMT has no additional insulating layer because the gate electrode is in direct contact with the AlGaN layer. The structure is simple to prepare, but is easily influenced by impact ionization under high voltage, higher leakage current and lower breakdown voltage occur, stability and reliability of the device are influenced, and under the illumination condition, a low-resistance path is directly formed between a 2DEG channel and top grid metal by photo-generated carriers, so that the performance of the device is influenced by potential change. Furthermore, deep level traps exist in GaN and AlGaN materials, and these level traps may capture photogenerated carriers, and also increase gate leakage current, which affects circuit performance.

The p-GaN HEMT (gallium phosphide high electron mobility transistor) can improve the energy band at the AlGaN/GaN heterojunction interface by introducing a p-type GaN layer below the grid of the traditional device and on the AlGaN/GaN heterojunction, and the p-GaN cap layer is higher than the fermi level when the grid bias voltage is 0V, so that the enhancement type (E-mode) operation is realized, and the problems of leakage current increase and breakdown voltage reduction can be solved to a certain extent. Therefore, the p-GaN HEMT is excellent in high temperature and high frequency conditions, and is suitable for high power and high frequency application scenarios. Although the p-GaN HEMT has good electrical properties, the problem of gate leakage current still needs to be further solved, and particularly, the leakage current is significantly increased under high temperature conditions, and in order to obtain a p-type conductive GaN layer, magnesium is generally used as a dopant to obtain the p-type conductive GaN layer, but the Mg dopant has low solubility in GaN and high ionization energy, so that it is difficult to achieve a sufficiently high hole concentration, resulting in that the p-GaN layer is difficult to completely deplete the 2DEG under the gate in practical use. Meanwhile, mg inevitably diffuses into the ALGaN barrier layer and the GaN channel layer during high temperature growth. Such diffusion behavior can greatly hinder the rise of the device threshold voltage, thereby compromising device performance.

MIS HEMTs (metal-insulator-semiconductor high electron mobility transistors) employ high-K gate dielectric materials, such as HfO ₂ (hafnium dioxide) and Al ₂O₃ (aluminum oxide), instead of conventional SiO ₂ (silicon dioxide) or Si ₃N₄ (silicon nitride), to improve gate capacitance to reduce gate leakage current and enhance voltage withstand and thermal stability of the gate. By introducing the insulating layer between the grid electrode and the AlGaN layer, the grid leakage current is effectively reduced, the electrical performance of the device is improved, and the high-K dielectric material has higher dielectric constant, so that the same channel modulation effect can be realized under lower grid voltage, and the leakage current and the grid voltage stress are reduced. However, the problem of reliability of the gate dielectric of MIS HEMTs (metal-insulator-semiconductor high electron mobility transistors) in high temperature environments needs to be further studied and solved, and under uv irradiation, uv light induces excessive trap states in the insulating layer, which makes charge trapping in the gate dielectric more serious, while charge trapping in the GaN buffer is significantly suppressed.

Disclosure of Invention

The invention discloses a GaN transistor structure and a preparation method thereof, which avoid the problem of grid leakage under the conditions of high temperature, strong electric field and illumination.

The invention discloses a GaN transistor structure, comprising:

a grid in a closed frame structure;

The gate surrounds the source and isolates the source from the drain.

Further, the gate, the source and the drain are all located in the active region.

Further, the active region is located between the source and the drain;

A portion of the gate extends into the inactive region.

Further, the gate is made of at least one of titanium, aluminum and tungsten.

Further, the gate is deposited on the surface of an insulating layer, and the insulating layer is located on the gate region.

Further, the gate is in direct contact with the p-doped layer, the metal layer, and/or the insulating layer.

Further, the GaN transistor includes a p-GaN HEMT, a MIS-HEMT, and a GaN MOSFET.

The invention also provides a preparation method of the GaN transistor structure, which comprises the following steps:

providing a front end structure;

forming an insulating layer in the gate region in the front-end structure;

A closed recess is formed in the insulating layer,

Depositing gate metal within the recess forms a gate that surrounds the source and isolates the source from the drain.

Further, the providing a front end structure includes:

Providing a substrate;

a channel layer, a barrier layer, a passivation layer and a p-type doping layer are sequentially laminated on the substrate;

determining a growth area of a source electrode and a drain electrode on the p-type doped layer;

removing the p-type doped layer of the growth region;

And depositing a metal layer on the surface of the barrier layer to form the source electrode and the drain electrode.

Further, after depositing gate metal in the groove to form a gate, the method further comprises:

Passivation and protection are performed by using a plasma enhanced chemical vapor deposition p-type doped layer;

performing device isolation by using a fluorine ion implantation method;

The pad region is determined, the p-type doped layer is removed, and a pad metal electrode is deposited.

Compared with the prior art, the invention can at least realize the following technical effects:

the invention introduces the grid electrode with the closed frame structure, and the grid electrode surrounds the source electrode, so that the drain electrode and the source electrode can be thoroughly isolated, the electric field distribution between the grid electrode and a channel is optimized, the forward bias grid electrode voltage of the transistor is obviously improved, the formation of a leakage channel is effectively restrained, the leakage current is greatly reduced, and the stability and the reliability of the circuit are enhanced. In addition, the grid electrode adopting the structure can optimize the electric field distribution around the grid electrode, reduce the generation and propagation paths of high-energy electrons, and remarkably enhance the robustness of the grid electrode under the high-temperature condition, thereby effectively inhibiting the damage of impact ionization effect on the grid electrode.

Drawings

FIG. 1 is a schematic diagram of a prior art gate structure;

FIG. 2 is a schematic diagram of a GaN transistor gate structure according to an embodiment of the invention;

FIG. 3 is a schematic diagram of another GaN transistor gate structure according to the first embodiment of the invention;

FIG. 4 is a schematic diagram of a p-GaN HEMT according to an embodiment of the invention;

fig. 5 is a flowchart of a method for manufacturing a p-GaN HEMT according to the second embodiment of the present invention.

Detailed Description

A GaN transistor structure and a method of fabricating the same of the present invention will be described in conjunction with the schematic drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art may modify the invention described herein while still achieving the advantageous effects of the invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.

The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "front", "rear", "left", "right", vertical "," horizontal "," top "," bottom "," inner "," outer ", etc. indicate orientations or positional relationships based on the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the scope of the present invention. Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Referring to fig. 2-3, the present invention discloses a GaN transistor structure, which includes a gate having a closed frame structure, wherein the gate surrounds a source and isolates the source from a drain.

In this embodiment, by introducing a gate with a closed frame structure, and the gate surrounds the source, the drain and the source can be completely isolated, thereby significantly increasing the forward bias gate voltage of the transistor. The fully-enclosed grid structure not only effectively controls the formation of a leakage channel in the passive region and greatly reduces leakage current, but also enhances the stability and reliability of the circuit. In addition, the grid electrode adopting the structure can optimize the electric field distribution around the grid electrode, reduce the generation and propagation paths of high-energy electrons, and remarkably enhance the robustness of the grid electrode under the high-temperature condition, thereby effectively inhibiting the damage of impact ionization effect on the grid electrode.

In one embodiment, referring to fig. 2, the gate, the source and the drain may all be disposed in the active region.

In another embodiment, referring to fig. 3, a portion of the gate may be located in an inactive region, the active region being located between the source and the drain, and the distance between two parallel outer sides of the gate being greater than the width of the active region.

In a specific embodiment, the gate of the closed frame structure may be a rectangular frame structure, a circular ring structure or an elliptical ring structure, and may be further adjusted to other closed frame structures with different shapes according to the electrical isolation requirement of the source and the drain. Furthermore, the specific dimensions of the closed frame are not particularly limited herein and may be optimized and adjusted by those skilled in the art according to the electrical isolation requirements.

Further, in this embodiment, the gate is deposited on the surface of an insulating layer, and the insulating layer is located above the gate region.

In this embodiment, the gate can be in direct contact with the p-doped layer, the metal layer, and/or the insulating layer.

In one embodiment, materials that may be used for the insulating layer include, but are not limited to, silicon dioxide (SiO ₂) or silicon nitride (Si ₃N₄).

The transistor gate structure described above can be used on many different types of GaN transistors, such as p-GaN HEMTs, MIS-HEMTs, and GaN MOSFETs.

In one embodiment, referring to fig. 4, the p-GaN HEMT comprises a GaN buffer layer, an AlGaN barrier layer, a p-GaN layer, and a dielectric layer (i.e., an insulating layer) sequentially deposited on a substrate, a source electrode and a drain electrode formed at both ends of the AlGaN barrier layer, and a gate electrode formed on a surface of the p-GaN layer and surrounding the source electrode.

In another specific embodiment, the GaN HEMT structure comprises a GaN buffer layer, an AlGaN barrier layer, a Schottky metal layer, an insulating layer, a source electrode and a drain electrode which are sequentially deposited on a substrate, wherein the source electrode and the drain electrode are formed at two ends of the AlGaN barrier layer, and a grid electrode of the structure is formed on the surface of the Schottky metal layer and surrounds the source electrode.

In another specific embodiment, the MIS-HEMT structure comprises a GaN buffer layer, an AlGaN barrier layer, a SiN ₃N₄ insulating layer, a source electrode and a drain electrode which are sequentially deposited on a substrate, wherein the source electrode and the drain electrode are formed at two ends of the AlGaN barrier layer, and a grid electrode of the structure which is formed on the surface of the SiN ₃N₄ insulating layer and surrounds the source electrode.

In another specific embodiment, the GaN MOSFET comprises a GaN buffer layer, a GaN layer, an AlGaN layer, an insulating layer, a source electrode and a drain electrode, wherein the GaN buffer layer, the GaN layer, the AlGaN layer and the insulating layer are sequentially deposited on a substrate, the source electrode and the drain electrode are formed at two ends of the AlGaN layer, and a grid electrode of the structure is formed on the surface of the insulating layer and surrounds the source electrode.

Example two

Referring to fig. 5, this embodiment discloses a preparation method for preparing a transistor structure as disclosed in embodiment one, which includes:

s1, providing a front end structure;

S2, forming an insulating layer on a grid electrode area of the front end structure;

s3, forming a closed groove on the insulating layer;

S4, depositing gate metal in the groove to form a gate, wherein the gate surrounds the source electrode and isolates the source electrode from the drain electrode.

In this embodiment, the front-end structure includes, but is not limited to, p-GaN HEMT, MIS-HEMT, gaN MOSFET, and other GaN devices where no metal gate is deposited. The person skilled in the art can set the transistor gate structure described above on different GaN devices according to the actual situation.

In a specific embodiment, a method for preparing a p-GaN HEMT with the gate structure is as follows:

s11, providing a substrate, wherein the substrate is made of monocrystalline silicon, sapphire and the like.

And S12, sequentially stacking a channel layer, a barrier layer, a passivation layer and a p-type doping layer on the substrate, and optionally introducing a buffer layer and a conversion layer between the channel layer and the substrate according to practical conditions.

Wherein, the channel layer adopts GaN material. The barrier layer is made of AlGaN material, the thickness is generally 10-20 nm, the doped Al component is generally 10% -30%, and the barrier layer is used for reducing lattice mismatch and thermal expansion coefficient difference between the substrate and the active layer material and reducing defect density. The passivation layer is, but not limited to, si ₃N₄ to protect the device surface. The p-type doped layer is p-type GaN formed by Mg doping, the thickness is 50-100 nm, the Mg doping concentration is 1018cm ^-3 -1020 cm ^-3, and the p-type doped layer can deplete two-dimensional electron gas in the channel layer 2 so as to realize a normally-off state of the gallium nitride device under zero gate source bias.

It will be appreciated by those skilled in the art that the doping concentrations, doping metal elements and thicknesses in the p-type doped layer and the barrier layer, including but not limited to those described above, may be selected differently according to actual needs. In addition, by precisely controlling the Mg and Al doping concentrations in the p-type doped layer and AlGaN barrier layer, the formation and migration of the 2DEG can be optimized.

S13, determining the growth areas of a source electrode and a drain electrode on the p-type doped layer, removing the p-type doped layer in the growth areas, and annealing to form the source electrode and the drain electrode after depositing a metal layer on the surface of the barrier layer.

S14, determining a gate region on the p-type doped layer, forming an insulating layer in the gate region in the front-end structure, forming a gate region with a closed frame structure on the surface of the insulating layer through photoetching and etching technology, and finally depositing gate metal in the gate region to obtain a gate.

S15, performing passivation and protection by using a plasma enhanced chemical vapor deposition p-type doped layer, performing device isolation by using a fluorine ion implantation method, removing the p-type doped layer after determining a bonding pad area, and depositing a bonding pad metal electrode.

In this embodiment, optimization of the electrical isolation effect and the gate control capability can be achieved by adjusting the gate thickness and the insulating layer thickness.

In summary, the movement of photo-generated carriers in the gate region of the GaN HEMT adopting the gate structure is strictly limited, and the influence of the photo-generated carriers on the surface state and the trap state of the gate is reduced. The optimization not only remarkably reduces the grid leakage current caused by the photo-generated carriers, but also improves the overall stability and reliability of the device under the illumination condition. Through the thorough isolation measure, the effective control of the photo-generated carriers is realized, so that the influence of the photo-generated carriers on the surface state and the trap state of the grid electrode is minimized. Thus, not only enhances the reliability of the device in optoelectronic applications, but also exhibits excellent stability and durability in non-optoelectronic environments.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (10)

1. A kind of GaN transistor structure, characterized by comprising the following steps:

a grid in a closed frame structure;

The gate surrounds the source and isolates the source from the drain.

2. The GaN transistor structure of claim 1 wherein,

The gate, the source and the drain are all located within the active region.

3. The GaN transistor structure of claim 1 wherein,

An active region is located between the source and the drain;

A portion of the gate extends into the inactive region.

4. The GaN transistor structure of claim 1, wherein the gate is at least one of titanium, aluminum, and tungsten.

5. The GaN transistor structure of claim 1 wherein the gate is deposited on a surface of an insulating layer, the insulating layer being located on the gate region.

6. The GaN transistor structure of claim 1, wherein the gate is in direct contact with the p-doped layer, the metal layer, and/or the insulating layer.

7. The GaN transistor structure of claim 1 wherein the GaN transistor comprises a p-GaN HEMT, a MIS-HEMT, and a GaN MOSFET.

8. A method for preparing a GaN transistor structure, the method comprising:

Providing a front end structure;

forming an insulating layer on the gate region of the front-end structure;

forming a closed groove on the insulating layer;

depositing gate metal within the recess forms a gate that surrounds the source and isolates the source from the drain.

9. The method of manufacturing a GaN transistor structure of claim 8, wherein said providing a front-end structure comprises:

Providing a substrate;

a channel layer, a barrier layer, a passivation layer and a p-type doping layer are sequentially laminated on the substrate;

determining a growth area of a source electrode and a drain electrode on the p-type doped layer;

removing the p-type doped layer of the growth region;

And depositing a metal layer on the surface of the barrier layer to form the source electrode and the drain electrode.

10. The method of manufacturing a GaN transistor structure of claim 9, further comprising, after depositing gate metal in said recess to form a gate:

Passivation and protection are performed by using a plasma enhanced chemical vapor deposition p-type doped layer;

performing device isolation by using a fluorine ion implantation method;

The pad region is determined, the p-type doped layer is removed, and a pad metal electrode is deposited.