CN115084232B - Heterojunction transverse double-diffusion field effect transistor, manufacturing method, chip and circuit - Google Patents

Abstract

The invention provides a heterojunction lateral double-diffusion field effect transistor, a manufacturing method, a chip and a circuit, and relates to the technical field of semiconductors. The transistor includes: a substrate; a gallium nitride buffer layer formed on the substrate; a source doped region, a gallium nitride body region, a gallium nitride drift region, and a drain doped region formed side by side on the gallium nitride buffer layer region; AlGaN barrier layer, formed on part of the GaN drift region; gate oxide dielectric layer, formed on the GaN body region, AlGaN barrier layer and part of the GaN not covered by the AlGaN barrier layer On the drift region; the source metal electrode is formed on the source doped region; the drain metal electrode is formed on the drain doped region; the gate metal electrode is formed on part of the gate oxide dielectric layer. The transistor provided by the invention can increase the breakdown voltage of the transistor, improve the electron mobility, ensure the speed of the device, reduce the complex field plate structure, reduce the manufacturing difficulty, and reduce the production cost.

Description

Heterojunction lateral double diffused field effect transistor, manufacturing method, chip and circuit

technical field

The invention relates to the technical field of semiconductors, in particular to a heterojunction lateral double-diffusion field effect transistor, a manufacturing method of the heterojunction lateral double-diffusion field effect transistor, a chip and a circuit.

Background technique

As a lateral power device, the Lateral Double-Diffused MOSFET (LDMOS) has its electrodes located on the surface of the device, and is easy to achieve monolithic integration with low-voltage signal circuits and other devices through internal connections. With the advantages of high voltage, large gain, good linearity, high efficiency, and good broadband matching performance, it has been widely used in power integrated circuits, especially low power consumption and high frequency circuits.

In the prior art, the breakdown voltage of the lateral double diffused field effect transistor is low, and the electron mobility is low, which affects the device speed, and the surface electric field in the drift region is large, which also reduces the breakdown voltage of the lateral double diffused field effect transistor. The field plate can increase the surface electric field in the drift region and reduce the peak value of the electric field, thereby suppressing the hot carrier effect and increasing the breakdown voltage. Therefore, the field plate structure is usually designed for lateral double-diffused field effect transistors, but the field plate structure process is complicated. , it is difficult to manufacture, the production cost is high, and the improvement effect on the breakdown voltage and the speed of the device is relatively low.

Contents of the invention

In view of the low breakdown voltage and low electron mobility of the lateral double-diffused field effect transistor in the prior art, which affects the device speed, and the field plate structure process is complex, the production is difficult, the production cost is high, and the breakdown voltage and device speed are improved. The technical problem of low effect, the present invention provides a kind of manufacturing method of heterojunction lateral double diffusion field effect transistor, a kind of heterojunction lateral double diffusion field effect transistor, a kind of chip and a kind of circuit, adopt this method to prepare The heterojunction lateral double diffused field effect transistor can improve the breakdown voltage of the lateral double diffused field effect transistor, improve the electron mobility, ensure the speed of the device, reduce the complex field plate structure, reduce the difficulty of manufacturing, and reduce the production cost.

In order to achieve the above object, the first aspect of the present invention provides a heterojunction lateral double diffused field effect transistor, the heterojunction lateral double diffused field effect transistor comprises: a substrate; a gallium nitride buffer layer formed on the substrate above; a source doped region, a gallium nitride body region, a gallium nitride drift region, and a drain doped region are formed side by side on the gallium nitride buffer layer; wherein, the gallium nitride body region has a first conductivity type, the source doped region, the gallium nitride drift region and the drain doped region have a second conductivity type; an aluminum gallium nitride barrier layer is formed on part of the gallium nitride drift region; gate oxide a dielectric layer formed on the gallium nitride body region, the aluminum gallium nitride barrier layer and a part of the gallium nitride drift region not covered by the aluminum gallium nitride barrier layer; a source metal electrode formed on the source On the region doping region; the drain metal electrode is formed on the drain region doping region; the gate metal electrode is formed on part of the gate oxide dielectric layer.

Further, the thickness of the gate oxide dielectric layer between the gate metal electrode and the gallium nitride body region is between 50nm and 150nm.

Further, the thickness of the AlGaN barrier layer is between 20nm and 50nm.

Further, the doped source region and the doped drain region are heavily doped with the second conductivity type.

Further, the source metal electrode and the drain metal electrode are made of Ti/Al/Ti/Au metal.

Further, the gate metal electrode is made of Ni/Au metal.

The second aspect of the present invention provides a method for manufacturing a heterojunction lateral double-diffused field effect transistor. The method for manufacturing a heterojunction lateral double-diffused field effect transistor includes: forming a substrate; forming a gallium nitride buffer on the substrate layer; forming a gallium nitride drift region, a gallium nitride body region, an aluminum gallium nitride barrier layer, a gate oxide dielectric layer, a source doped region and a drain doped region; wherein, the source doped region, the a gallium nitride drift region, the gallium nitride body region and the drain doped region are formed side by side on the gallium nitride buffer layer, and the aluminum gallium nitride barrier layer is formed on part of the gallium nitride drift region, The gate oxide dielectric layer is formed on the GaN body region, the AlGaN barrier layer, and a part of the GaN drift region not covered by the AlGaN barrier layer; the GaN body region having a first conductivity type, the source doped region, the gallium nitride drift region and the drain doped region having a second conductivity type; forming a source metal electrode on the source doped region; A drain metal electrode is formed on the drain doped region; a gate metal electrode is formed on part of the gate oxide dielectric layer.

Further, the formation of the gallium nitride drift region, the gallium nitride body region, the aluminum gallium nitride barrier layer, the gate oxide dielectric layer, the source region doped region and the drain region doped region includes: A first conductive type gallium nitride layer and a second conductive type gallium nitride layer arranged side by side are formed on the layer; the aluminum gallium nitride barrier layer is formed on a part of the second conductive type gallium nitride layer; on the aluminum gallium nitride layer The gate oxide dielectric layer is formed on the barrier layer, part of the first conductivity type gallium nitride layer and part of the second conductivity type gallium nitride layer not covered by the aluminum gallium nitride barrier layer; by ion implantation The first conductive type gallium nitride layer covered by the gate oxide dielectric layer forms the source doped region, and the second conductive type gallium nitride layer not covered by the gate oxide dielectric layer forms the drain region doped region , wherein the gallium nitride layer of the first conductivity type that has not been ion-implanted is the gallium nitride body region, and the gallium nitride layer of the second conductivity type that has not been ion-implanted is the gallium nitride drift region.

Further, the thickness of the gate oxide dielectric layer between the gate metal electrode and the gallium nitride body region is between 50nm and 150nm.

Further, the thickness of the AlGaN barrier layer is between 20nm and 50nm.

Further, the doped source region and the doped drain region are heavily doped with the second conductivity type.

Further, the source metal electrode and the drain metal electrode are made of Ti/Al/Ti/Au metal.

Further, the gate metal electrode is made of Ni/Au metal.

A third aspect of the present invention provides a chip, which includes the above-mentioned heterojunction lateral double-diffused field effect transistor.

A fourth aspect of the present invention provides a circuit, which includes the above-mentioned heterojunction lateral double-diffused field effect transistor.

Through the technical solution provided by the present invention, the present invention has at least the following technical effects:

The heterojunction lateral double-diffused field effect transistor of the present invention comprises a substrate, on which a gallium nitride buffer layer is formed, and on the gallium nitride buffer layer, an active region doped region, a gallium nitride body region, The gallium nitride drift region and the drain region doped region, the gallium nitride body region has the first conductivity type, the source region doped region, the gallium nitride drift region and the drain region doped region have the second conductivity type, and the partially nitrided An aluminum gallium nitride barrier layer is formed on the gallium drift region, a gate oxide dielectric layer is formed on the gallium nitride body region, the aluminum gallium nitride barrier layer and a part of the gallium nitride drift region not covered by the aluminum gallium nitride barrier layer, and the source metal The electrode is formed on the source doped region, the drain metal electrode is formed on the drain doped region, and the gate metal electrode is formed on part of the gate oxide dielectric layer. The heterojunction formed by the aluminum gallium nitride barrier layer and the underlying gallium nitride drift region generates a two-dimensional electron gas. Using the electron concentration of the two-dimensional electron gas can improve electron mobility and improve the device speed of the lateral double-diffused field effect transistor. At the same time Utilizing the advantages of gallium nitride's wide bandgap and high critical breakdown electric field improves the breakdown voltage of the lateral double-diffused field effect transistor, avoiding the problem of low breakdown voltage caused by the surface electric field in the drift region of the lateral double-diffused field effect transistor, and There is no need to add a complicated field plate structure, which reduces manufacturing difficulty and production cost.

Description of drawings

The accompanying drawings are used to provide a further understanding of the embodiments of the present invention, and constitute a part of the specification, and are used together with the following specific embodiments to explain the embodiments of the present invention, but do not constitute limitations to the embodiments of the present invention. In the attached picture:

1 is a cross-sectional view of a gallium nitride buffer layer formed in a method for manufacturing a heterojunction lateral double-diffused field-effect transistor according to an embodiment of the present invention;

2 is a cross-sectional view of a second conductivity type gallium nitride layer formed in the method for manufacturing a heterojunction lateral double-diffused field effect transistor according to an embodiment of the present invention;

3 is a cross-sectional view of the first conductivity type gallium nitride layer formed in the method for manufacturing the heterojunction lateral double-diffused field effect transistor provided by the embodiment of the present invention;

4 is a cross-sectional view of an AlGaN barrier layer formed in a method for manufacturing a heterojunction lateral double-diffused field-effect transistor according to an embodiment of the present invention;

5 is a cross-sectional view of a gate oxide dielectric layer formed in a method for manufacturing a heterojunction lateral double-diffused field-effect transistor according to an embodiment of the present invention;

6 is a cross-sectional view of a source doped region, a drain doped region, a gallium nitride body region, and a gallium nitride drift region formed in the method for manufacturing a heterojunction lateral double-diffused field effect transistor according to an embodiment of the present invention;

7 is a cross-sectional view of a source metal electrode and a drain metal electrode formed in the method for manufacturing a heterojunction lateral double-diffused field effect transistor according to an embodiment of the present invention;

8 is a cross-sectional view of a heterojunction lateral double-diffused field-effect transistor formed in the method for manufacturing a heterojunction lateral double-diffused field-effect transistor according to an embodiment of the present invention;

FIG. 9 is a flowchart of a method for manufacturing a heterojunction lateral double-diffused field effect transistor according to an embodiment of the present invention.

Explanation of reference signs

1-substrate; 2-gallium nitride buffer layer; 3-second conductivity type gallium nitride layer; 4-first conductivity type gallium nitride layer; 5-aluminum gallium nitride barrier layer; 6-gate oxide dielectric layer; 7-source doped region; 8-drain doped region; 9-gallium nitride body region; 10-gallium nitride drift region; 11-source metal electrode; 12-drain metal electrode; 13-gate metal electrodes.

detailed description

The specific implementation manners of the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation manners described here are only used to illustrate and explain the embodiments of the present invention, and are not intended to limit the embodiments of the present invention.

It should be noted that, in the case of no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

In the present invention, unless stated to the contrary, the used orientation words such as "up, down, top, bottom" generally refer to the directions shown in the drawings or refer to the vertical, perpendicular or gravitational directions The terms used to describe the mutual positional relationship of the various components mentioned above.

The present invention will be described in detail below with reference to the accompanying drawings and examples.

Please refer to FIG. 8, the first aspect of the present invention provides a heterojunction lateral double-diffused field effect transistor, the heterojunction lateral double-diffused field effect transistor includes: a substrate 1; a gallium nitride buffer layer 2 formed on the On the substrate 1; the source region doped region 7, the gallium nitride body region 9, the gallium nitride drift region 10 and the drain region doped region 8 formed side by side on the gallium nitride buffer layer 2; wherein, the The gallium nitride body region 9 has a first conductivity type, the source doped region 7, the gallium nitride drift region 10 and the drain doped region 8 have a second conductivity type; the aluminum gallium nitride barrier layer 5 , formed on part of the gallium nitride drift region 10; the gate oxide dielectric layer 6, formed on the gallium nitride body region 9, the aluminum gallium nitride barrier layer 5 and the aluminum gallium nitride barrier layer 5 not covered GaN drift region 10; source metal electrode 11, formed on the source doped region 7; drain metal electrode 12, formed on the drain doped region 8; gate metal electrode 13, formed on part of the gate oxide dielectric layer 6 .

Specifically, in the embodiment of the present invention, the substrate 1 is a silicon substrate or a silicon carbide substrate. In this embodiment, the substrate 1 is a silicon carbide substrate. Those skilled in the art can select the type of substrate according to the performance of the semiconductor device to be formed, so the type of substrate should not limit the protection scope of the present invention too much. A gallium nitride buffer layer 2 is formed on the substrate 1, and the gallium nitride buffer layer 2 is lightly doped with the first conductivity type. On the gallium nitride buffer layer 2, an active region doped region 7, a gallium nitride body region 9, a gallium nitride drift region 10 and a drain region doped region 8 are formed side by side, and the gallium nitride body region 9 has a first conductivity type , the source doped region 7, the gallium nitride drift region 10 and the drain doped region 8 have a second conductivity type, and the lightly doped gallium nitride buffer layer 2 of the first conductivity type can be combined with the source doped region 7 and The doped drain region 8 forms a reverse PN junction to avoid device leakage.

An AlGaN barrier layer 5 is formed on part of the GaN body region 9 near the junction of the drain doped region 8 and the GaN body region 9, and the GaN drift region 10 is much thicker than the AlGaN barrier layer. Layer 5, only spontaneous polarization exists; while the AlGaN barrier layer 5 is thinner and the lattice constant of the AlGaN material is larger than that of the Gallium Nitride (GaN) material, the lattice mismatch between the two makes the AlGaN The barrier layer 5 is subjected to tensile stress, and the AlGaN barrier layer 5 has piezoelectric polarization and spontaneous polarization. At this time, the total polarization of the AlGaN barrier layer 5 and the spontaneous polarization of the GaN drift region 10 will partially cancel each other out, and both of the polarizations are negative, that is, they will generate Positive polarized charges, negative polarized charges are generated at the upper interface, and finally, since the spontaneous polarization and pressure polarization of the AlGaN barrier layer 5 are stronger than those of the GaN drift region 10, the charges pass through the interface between the two Cancellation leaves a net positively polarized charge. According to the principle of charge balance, negatively charged electrons with the same magnitude as the positive polarized charge density are induced at the interface between the GaN drift region 10 and the AlGaN barrier layer 5 .

Because GaN drift region 10 and AlGaN barrier layer 5 have different forbidden band widths, the forbidden band width of AlGaN is higher than that of GaN, so that there is a band difference between the conduction band bottoms of the two. The band step difference plus a large amount of positive charges at the interface will bend the energy band at the bottom of the conduction band, and the energy band bending will form a two-dimensional potential well at the junction of the heterojunction. This two-dimensional potential well will confine the polarization-induced electrons, and these electrons can only move two-dimensionally along the plane parallel to the abrupt junction interface in the potential well, forming a two-dimensional electron gas. The electron mobility of the two-dimensional electron gas structure is more than twice that of the bulk electron mobility. Using the electron concentration of the two-dimensional electron gas can increase the electron mobility and improve the device speed of the lateral double-diffused field effect transistor. In the AlGaN/GaN heterojunction structure, even without any doping of the AlGaN barrier layer, the surface density of the induced two-dimensional electron gas can be as high as More than 2×10 ¹³ cm ^-2 .

At the same time, the GaN body region 9 and the GaN drift region 10 have a forbidden bandwidth and a high critical breakdown electric field, which improves the breakdown voltage of the lateral double-diffused field effect transistor and can avoid the surface electric field in the drift region of the lateral double-diffused field effect transistor. Therefore, it is not necessary to add a complex field plate structure, and only the gate needs to be fabricated, that is, in the GaN body region 9, the AlGaN barrier layer 5 and those not covered by the AlGaN barrier layer 5 The gate oxide dielectric layer 6 is formed on the gallium nitride drift region 10 , and the gate metal electrode 13 is formed on part of the gate oxide dielectric layer 6 , which reduces manufacturing difficulty and production cost. The gate oxide dielectric layer 6 is formed above the GaN body region 9 and the AlGaN barrier layer 5, and the GaN drift region 10 is not covered by the AlGaN barrier layer 5 and is in contact with the GaN body region 9 above. The gate metal electrode 13 is formed on part of the gate oxide dielectric layer 6 .

The source metal electrode 11 is formed on the source doped region 7 and forms a source with the source metal electrode 11 . The drain metal electrode 12 is formed on the drain doped region 8 and forms a drain with the drain metal electrode 12 . The two-dimensional electron gas between the aluminum gallium nitride barrier layer 5 and the lower gallium nitride body region 9 is lateral, and the source and drain electrodes are respectively arranged on the side of the gallium nitride body region 9 and the gallium nitride drift region 10. The conduction resistance of the lateral double-diffused field effect transistor is reduced, the conduction speed of the device is further improved, and the conduction characteristic of the device is improved.

According to the heterojunction lateral double-diffused field effect transistor provided by the present invention, the heterojunction formed by the AlGaN barrier layer and the underlying GaN drift region 10 generates a two-dimensional electron gas, and the electron concentration of the two-dimensional electron gas can be used to Improve electron mobility, increase the device speed of lateral double-diffusion field effect transistors, and at the same time take advantage of GaN's wide bandgap and high critical breakdown electric field to increase the breakdown voltage of lateral double-diffusion field-effect transistors and avoid lateral double diffusion The problem of low breakdown voltage caused by the surface electric field in the drift region of the field effect transistor does not need to add a complicated field plate structure, which reduces the difficulty of manufacturing and reduces the production cost.

Further, the gate oxide dielectric layer 6 between the gate metal electrode 13 and the gallium nitride body region 9 has a thickness of 50-150 nm.

Specifically, in the embodiment of the present invention, the thickness of the gate oxide dielectric layer 6 between the gate metal electrode 13 and the gallium nitride body region 9 is between 50 nm and 150 nm. If the gate oxide dielectric layer 6 is too thick, the The higher the threshold voltage, the lower the switching speed; if the gate oxide dielectric layer 6 is too thin, defects are likely to occur during chemical vapor deposition, and breakdown is easy, and the chemical vapor deposition process is not easy to control, which affects the uniformity of the gate oxide dielectric layer 6 . Preferably, the thickness of the gate oxide dielectric layer 6 between the gate metal electrode 13 and the gallium nitride body region 9 is 100 nm.

Further, the thickness of the AlGaN barrier layer 5 is between 20nm and 50nm.

Specifically, in the embodiment of the present invention, the thickness of the AlGaN barrier layer 5 is between 20 and 50 nm. If the AlGaN barrier layer 5 is too thick, it is difficult to control the thickness of the gate oxide dielectric layer 6; if the AlGaN barrier layer 5 is too thin, the formed AlGaN barrier layer 5 has more defects, and the device is prone to breakdown. Preferably, the AlGaN barrier layer 5 has a thickness of 30 nm.

Furthermore, the thickness of the gallium nitride buffer layer 2 is between 1-2 um. If the gallium nitride buffer layer 2 is too thick, the manufacturing cost of the device will be increased; if the gallium nitride buffer layer 2 is too thin, it will not have a buffering effect.

Further, the thickness of the GaN body region 9 and the GaN drift region 10 is between 50-100 nm. If the GaN body region 9 and the GaN drift region 10 are too thick, the production cost will be increased and the smoothness of the surface will be affected. degree, and the uniformity of doping is poor; if the gallium nitride body region 9 and the gallium nitride drift region 10 are too thin, the epitaxial process is not easy to control, and the gallium nitride body region 9 and the gallium nitride drift region 10 are easy to There are defects, and the on-resistance during operation is too large, which increases the loss of the device and affects the characteristics of the device.

Further, the doped source region 7 and the doped drain region 8 are heavily doped with the second conductivity type.

Further, the source metal electrode 11 and the drain metal electrode 12 are made of Ti/Al/Ti/Au metal.

Specifically, in the embodiment of the present invention, the source metal electrode 11 and the drain metal electrode 12 can respectively form ohmic contacts with the source doped region 7 and the drain doped region 8, shielding the influence of high voltage, reducing the source The leakage current injection of the terminal ohmic contact improves the off-state breakdown voltage of the lateral double diffused field effect transistor.

Further, the gate metal electrode 13 is made of Ni/Au metal.

Please refer to FIG. 1-FIG. 9. The second aspect of the present invention provides a method for manufacturing a heterojunction lateral double-diffused field-effect transistor. The method for manufacturing a heterojunction lateral double-diffused field-effect transistor includes: S101: forming a substrate 1; S102: Form a GaN buffer layer 2 on the substrate 1; S103: Form a GaN drift region 10, a GaN body region 9, an AlGaN barrier layer 5, a gate oxide dielectric layer 6, a doped source region impurity region 7 and drain region doped region 8; wherein, the source region doped region 7, the gallium nitride drift region 10, the gallium nitride body region 9 and the drain region doped region 8 are formed side by side On the gallium nitride buffer layer 2, the aluminum gallium nitride barrier layer 5 is formed on a part of the gallium nitride drift region 10, and the gate oxide dielectric layer 6 is formed on the gallium nitride body region 9, the On the AlGaN barrier layer 5 and the GaN drift region 10 not covered by the AlGaN barrier layer 5; the GaN body region 9 has the first conductivity type, and the source region doped region 7, The gallium nitride drift region 10 and the drain doped region 8 have a second conductivity type; S104: form a source metal electrode 11 on the source doped region 7; S105: dope the drain region Forming a drain metal electrode 12 on the impurity region 8 ; S106 : forming a gate metal electrode 13 on part of the gate oxide dielectric layer 6 .

Step S101 is first performed: forming a substrate 1 .

Please refer to FIG. 1 , specifically, in the embodiment of the present invention, the lateral double-diffused field effect transistor provided can be either an N-type lateral double-diffused field-effect transistor or a P-type lateral double-diffused field effect transistor. When the lateral double diffused field effect transistor is an N type lateral double diffused field effect transistor, the first conductivity type is P type, and the second conductive type is N type; when the lateral double diffused field effect transistor is a P type lateral double diffused field effect transistor In the case of an effect transistor, the first conductivity type is N-type, and the second conductivity type is P-type, which is not limited in the present invention. In the following embodiments, only an N-type lateral double-diffused field effect transistor is used as an example for illustration.

Step S102 is then performed: forming a gallium nitride buffer layer 2 on the substrate 1 .

Specifically, in the embodiment of the present invention, the gallium nitride buffer layer 2 is formed on the substrate 1 through an epitaxial process.

Then step S103 is performed: forming the GaN drift region 10, the GaN body region 9, the AlGaN barrier layer 5, the gate oxide dielectric layer 6, the source doped region 7 and the drain doped region 8; wherein, the The source region doped region 7, the gallium nitride drift region 10, the gallium nitride body region 9 and the drain region doped region 8 are formed side by side on the gallium nitride buffer layer 2, and the aluminum The gallium nitride barrier layer 5 is formed on part of the gallium nitride drift region 10, the gate oxide dielectric layer 6 is formed on the gallium nitride body region 9, the aluminum gallium nitride barrier layer 5 and the On the gallium nitride drift region 10 covered by the barrier layer 5; the gallium nitride body region 9 has the first conductivity type, the source doped region 7, the gallium nitride drift region 10 and the drain doped region Impurity region 8 has the second conductivity type.

Further, the formation of the gallium nitride drift region 10, the gallium nitride body region 9, the aluminum gallium nitride barrier layer 5, the gate oxide dielectric layer 6, the source region doped region 7 and the drain region doped region 8 includes: A gallium nitride layer 4 of the first conductivity type and a gallium nitride layer 3 of the second conductivity type arranged side by side are formed on the gallium nitride buffer layer 2; the aluminum gallium is formed on part of the gallium nitride layer of the second conductivity type 3 Nitrogen barrier layer 5; formed on the aluminum gallium nitride barrier layer 5, part of the first conductivity type gallium nitride layer 4 and part of the second conductivity type gallium nitride layer 3 not covered by the aluminum gallium nitride barrier layer 5 The gate oxide dielectric layer 6; the source region doped region 7 is formed in the first conductivity type gallium nitride layer 4 not covered by the gate oxide dielectric layer 6 by ion implantation, The second conductivity type gallium nitride layer 3 covered by the layer 6 forms the drain doped region 8, wherein the first conductivity type gallium nitride layer 4 that has not been ion-implanted is the gallium nitride body region 9, not The ion-implanted gallium nitride layer 3 of the second conductivity type is the gallium nitride drift region 10 .

Further, the doped source region 7 and the doped drain region 8 are heavily doped with the second conductivity type.

Specifically, in the embodiment of the present invention, after the gallium nitride buffer layer 2 is formed, a layer of N-type gallium nitride is epitaxially formed to form the second conductivity type gallium nitride layer 3, and on the second conductivity type gallium nitride layer 3 A layer of silicon dioxide is deposited on the surface by chemical vapor phase, and a photoresist is formed on the surface of the silicon dioxide. The photoresist is etched to form a first etching window, and the silicon dioxide and the second etching window are dry etched through the first etching window. The conductivity type gallium nitride layer 3 forms the structure shown in FIG. 2 . Next, select the epitaxial P-type GaN, remove the silicon dioxide on the surface of the second conductivity type GaN layer 3, and chemically mechanically polish the excess P-type GaN to form the first conductivity type GaN layer in FIG. 3 4. Then a layer of AlGaN is epitaxially grown, and the AlGaN is etched to obtain the AlGaN barrier layer 5 in FIG. The position where region 8 and GaN body region 9 meet. Next, a layer of silicon dioxide is chemically vapor deposited on the surface, and the silicon dioxide is dry-etched, and the aluminum gallium nitride barrier layer 5, part of the first conductivity type gallium nitride layer 4 and the areas not covered by the aluminum gallium nitride barrier layer 5 A gate oxide dielectric layer 6 is formed on the gallium nitride layer 3 of the second conductivity type, as shown in FIG. 5 . Then N-type ion heavy doping is carried out, and the source region doping region 7 is formed in the first conductivity type gallium nitride layer 4 not covered by the gate oxide dielectric layer 6, and the second conductivity type GaN layer not covered by the gate oxide dielectric layer 6 The gallium nitride layer 3 forms the doped region 8 of the drain region, while the first conductivity type gallium nitride layer 4 that has not been ion-implanted forms the gallium nitride body region 9, and the second conductivity type gallium nitride layer 3 that has not been ion-implanted GaN drift region 10 is formed, as shown in FIG. 6 .

Step S104 is then performed: forming a source metal electrode 11 on the source doped region 7 .

Step S105 is then performed: forming a drain metal electrode 12 on the drain doped region 8 .

Further, the source metal electrode 11 and the drain metal electrode 12 are made of Ti/Al/Ti/Au metal.

Please refer to FIG. 7. Specifically, in the embodiment of the present invention, after forming the source doped region 7 and the drain doped region 8, a layer of Ti/Al/Ti/Au metal is physically vapor deposited, and the Ti/Al/ Ti/Au metal is etched, and the metal material on the source doped region 7 and the drain doped region 8 is retained, and the source metal electrode 11 is formed on the source doped region 7, and on the drain doped region 8 A drain metal electrode 12 is formed.

Finally, step S106 is executed: forming the gate metal electrode 13 on part of the gate oxide dielectric layer 6 .

Further, the gate metal electrode 13 is made of Ni/Au metal.

Please refer to FIG. 8. Specifically, in an embodiment of the present invention, a layer of Ni/Au metal is physically vapor deposited on the surface of the device, and the Ni/Au metal near the source metal electrode 11 and the drain metal electrode 12 is removed by etching, A gate metal electrode 13 is formed on part of the gate oxide dielectric layer 6 .

Further, the gate oxide dielectric layer 6 between the gate metal electrode 13 and the gallium nitride body region 9 has a thickness of 50-150 nm.

Further, the thickness of the AlGaN barrier layer 5 is between 20nm and 50nm.

A third aspect of the present invention provides a chip, which includes the above-mentioned heterojunction lateral double-diffused field effect transistor.

A fourth aspect of the present invention provides a circuit, which includes the above-mentioned heterojunction lateral double-diffused field effect transistor.

The preferred embodiment of the present invention has been described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the specific details of the above embodiment, within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, These simple modifications all belong to the protection scope of the present invention.

In addition, it should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable way if there is no contradiction. The combination method will not be described separately.

In addition, various combinations of different embodiments of the present invention can also be combined arbitrarily, as long as they do not violate the idea of the present invention, they should also be regarded as the disclosed content of the present invention.

Claims (15)

1. A heterojunction lateral double-diffused field effect transistor, comprising:

a substrate;

the gallium nitride buffer layer is formed on the substrate and is lightly doped with a first conductive type;

the source region doped region, the gallium nitride body region, the gallium nitride drift region and the drain region doped region are formed on the gallium nitride buffer layer in parallel; wherein the gallium nitride body region has a first conductivity type, and the source region doped region, the gallium nitride drift region, and the drain region doped region have a second conductivity type;

the AlGaN barrier layer is formed on part of the GaN drift region;

the gate oxide dielectric layer is formed on the gallium nitride body region, the aluminum gallium nitrogen barrier layer and the gallium nitride drift region which is partially uncovered by the aluminum gallium nitrogen barrier layer;

the source metal electrode is formed on the source region doped region;

the drain electrode metal electrode is formed on the drain region doping region;

and the grid metal electrode is formed on part of the grid oxide dielectric layer.

2. The heterojunction lateral double-diffused field effect transistor of claim 1, wherein the thickness of the gate oxide dielectric layer between the gate metal electrode and the gallium nitride body region is between 50 and 150nm.

3. The heterojunction lateral double-diffused field effect transistor according to claim 1, wherein the thickness of the aluminum gallium nitride barrier layer is 20 to 50nm.

4. The heterojunction lateral double diffused field effect transistor of claim 1, wherein said source region doped region and said drain region doped region are heavily doped of a second conductivity type.

5. The heterojunction lateral double-diffused field effect transistor of claim 1, wherein the source metal electrode and the drain metal electrode are made of Ti/Al/Ti/Au metal.

6. The heterojunction lateral double-diffused field effect transistor of claim 1, wherein the gate metal electrode is made of Ni/Au metal.

7. A method for manufacturing a heterojunction transverse double-diffused field effect transistor is characterized by comprising the following steps:

forming a substrate;

forming a gallium nitride buffer layer on the substrate, wherein the gallium nitride buffer layer is lightly doped with a first conductive type;

forming a gallium nitride drift region, a gallium nitride body region, an aluminum gallium nitrogen barrier layer, a gate oxide dielectric layer, a source region doped region and a drain region doped region; the source region doped region, the gallium nitride drift region, the gallium nitride body region and the drain region doped region are formed on the gallium nitride buffer layer side by side, the aluminum gallium nitride barrier layer is formed on part of the gallium nitride drift region, and the gate oxide dielectric layer is formed on the gallium nitride body region, the aluminum gallium nitride barrier layer and part of the gallium nitride drift region which is not covered by the aluminum gallium nitride barrier layer; the gallium nitride body region has a first conductivity type, and the source region doped region, the gallium nitride drift region, and the drain region doped region have a second conductivity type;

forming a source metal electrode on the source region doped region;

forming a drain metal electrode on the drain region doped region;

and forming a grid metal electrode on part of the grid oxide dielectric layer.

8. The method of claim 7, wherein the forming of the gan drift region, gan body region, algan barrier layer, gate oxide dielectric layer, source region doped region and drain region doped region comprises:

forming a first conductive type gallium nitride layer and a second conductive type gallium nitride layer which are arranged side by side on the gallium nitride buffer layer;

forming the AlGaN barrier layer on part of the second conduction type GaN layer;

forming the gate oxide dielectric layer on the AlGaN barrier layer, part of the first conductive type GaN layer and part of the second conductive type GaN layer which is not covered by the AlGaN barrier layer;

and forming the source region doped region on the first conductive type gallium nitride layer which is not covered by the gate oxide dielectric layer through ion implantation, and forming the drain region doped region on the second conductive type gallium nitride layer which is not covered by the gate oxide dielectric layer, wherein the first conductive type gallium nitride layer which is not implanted by the ions is the gallium nitride body region, and the second conductive type gallium nitride layer which is not implanted by the ions is the gallium nitride drift region.

9. The method of claim 7, wherein the thickness of the gate oxide dielectric layer between the gate metal electrode and the gallium nitride body region is between 50nm and 150nm.

10. The method according to claim 7, wherein the thickness of the AlGaN barrier layer is 20-50 nm.

11. The method of claim 7, wherein the source region doped region and the drain region doped region are heavily doped with the second conductivity type.

12. The method according to claim 7, wherein the source metal electrode and the drain metal electrode are made of Ti/Al/Ti/Au metal.

13. A method of fabricating a heterojunction lateral double-diffused field effect transistor according to claim 7, wherein said gate metal electrode is made of Ni/Au metal.

14. A chip comprising a heterojunction lateral double-diffused field effect transistor according to any one of claims 1 to 6.

15. A circuit comprising a heterojunction lateral double-diffused field effect transistor according to any of claims 1 to 6.

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