CN118943015A - A method for manufacturing an axially ultra-thin chip product - Google Patents
A method for manufacturing an axially ultra-thin chip product Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 238000000227 grinding Methods 0.000 claims abstract description 59
- 238000009792 diffusion process Methods 0.000 claims abstract description 50
- 238000003466 welding Methods 0.000 claims abstract description 35
- 238000005476 soldering Methods 0.000 claims abstract description 26
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052796 boron Inorganic materials 0.000 claims abstract description 23
- 230000032683 aging Effects 0.000 claims abstract description 15
- 238000012545 processing Methods 0.000 claims abstract description 12
- 238000005554 pickling Methods 0.000 claims abstract description 11
- 238000004806 packaging method and process Methods 0.000 claims abstract description 9
- 238000001465 metallisation Methods 0.000 claims abstract description 8
- 239000013078 crystal Substances 0.000 claims abstract description 7
- 238000004026 adhesive bonding Methods 0.000 claims abstract description 6
- 238000001723 curing Methods 0.000 claims abstract description 3
- 238000000465 moulding Methods 0.000 claims abstract 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 50
- 238000007747 plating Methods 0.000 claims description 33
- 229910052759 nickel Inorganic materials 0.000 claims description 25
- 238000004140 cleaning Methods 0.000 claims description 23
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 21
- 229910052737 gold Inorganic materials 0.000 claims description 21
- 239000010931 gold Substances 0.000 claims description 21
- 238000001035 drying Methods 0.000 claims description 20
- 238000005260 corrosion Methods 0.000 claims description 13
- 230000007797 corrosion Effects 0.000 claims description 13
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 230000035882 stress Effects 0.000 abstract description 11
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000000926 separation method Methods 0.000 abstract description 2
- 239000011148 porous material Substances 0.000 abstract 1
- 239000002253 acid Substances 0.000 description 29
- 238000005406 washing Methods 0.000 description 22
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 12
- 229910052698 phosphorus Inorganic materials 0.000 description 12
- 239000011574 phosphorus Substances 0.000 description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 8
- 238000010304 firing Methods 0.000 description 7
- 238000010301 surface-oxidation reaction Methods 0.000 description 7
- 238000005498 polishing Methods 0.000 description 5
- 238000003825 pressing Methods 0.000 description 5
- 239000000843 powder Substances 0.000 description 4
- 238000002791 soaking Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 230000002035 prolonged effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000002180 anti-stress Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000009863 impact test Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4885—Wire-like parts or pins
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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Abstract
本申请涉及半导体分离器件生产的技术领域，具体公开了一种轴向超薄芯片产品制造方法。一种轴向超薄芯片产品制造方法，包括以下步骤：S1、晶圆片选择：选择电阻率为15‑23Ω*cm，厚度为220‑240μm的单晶片作为待处理晶圆片；S2、晶圆片处理：对待处理晶圆片进行正面研磨、预扩散、背面研磨、硼扩散、双面研磨、表面金属化、划片处理，得到中间晶圆片；S3、封装：将中间晶圆片经焊接、酸洗、上胶、固化、模压、老化、回流焊、二次老化处理，得到半成品二极管。本申请制备得到的二极管具有气孔小、尺寸薄、风险低、抗应力能力优异以及耐焊接热能力优异等优点。
The present application relates to the technical field of semiconductor separation device production, and specifically discloses a method for manufacturing an axial ultra-thin chip product. A method for manufacturing an axial ultra-thin chip product, comprising the following steps: S1, wafer selection: selecting a single crystal with a resistivity of 15-23Ω*cm and a thickness of 220-240μm as a wafer to be processed; S2, wafer processing: performing front grinding, pre-diffusion, back grinding, boron diffusion, double-sided grinding, surface metallization, and slicing on the wafer to be processed to obtain an intermediate wafer; S3, packaging: welding, pickling, gluing, curing, molding, aging, reflow soldering, and secondary aging on the intermediate wafer to obtain a semi-finished diode. The diode prepared by the present application has the advantages of small pores, thin size, low risk, excellent stress resistance, and excellent resistance to welding heat.
Description
Technical Field
The application relates to the technical field of semiconductor separation device production, in particular to a manufacturing method of an axial ultrathin chip product.
Background
Integrated circuit chips are continuously developed in the direction of high density and light weight, and in order to meet the requirements, the wafer needs to be thinned and cut. The wafer thinning technology is a key technology of stacked chip packaging, and the thinning process is an important process for chip production, and has a great influence on the production quality of chips and the like. In the current wafer thinning process, the wafer is generally thinned to a predetermined thickness range, and then cut into individual chips. However, as the frequency in the electronic circuit increases, the product becomes smaller and thinner, the power increases, the corresponding fast rectifying, the ultra-fast rectifying device, the lost power increases, and a large amount of materials are consumed because the chip area used is increased to avoid failure.
Disclosure of Invention
In order to solve the problems of larger and larger chip area and higher material consumption, the application provides a method for adopting the following technical scheme:
the application provides a manufacturing method of an axial ultrathin chip product, which comprises the following steps:
S1, selecting a wafer: selecting a single crystal wafer with resistivity of 15-23 omega cm and thickness of 220-240 mu m as a wafer to be processed;
S2, processing a wafer: carrying out front grinding, pre-diffusion, back grinding, boron diffusion, double-sided grinding, surface metallization and scribing on the wafer to be processed to obtain an intermediate wafer;
S3, packaging: and (3) performing welding, acid washing, sizing, curing, mould pressing, ageing, reflow soldering and secondary ageing treatment on the intermediate wafer to obtain the semi-finished diode.
By adopting the technical scheme, the thickness of the chip is optimized, and the base width is compressed while the thermal resistance of the chip is reduced. The thickness of the chip can be further reduced by utilizing the grinding thinning treatment such as front grinding, back grinding and double-sided grinding, so that the structure of the finally obtained chip product is more compact. The front side grinding process can reduce or eliminate mechanical stress damage caused by dicing and maintain the integrity of the wafer.
The application carries out reflow soldering impact test on the packaged and aged product, can effectively reduce the generation of stress failure caused by subsequent wave soldering or reflow soldering stress damage, and improves the use stability of the diode product.
Optionally, in step S2, the front grinding has a grinding thickness of 5-10 μm.
Through adopting above-mentioned technical scheme, optimized the thickness that the front was ground, suitable grinding thickness can attenuate chip thickness to reduce the mechanical stress damage that the cutting led to.
Optionally, in step S2, the square resistance r+×is 0.36-0.45 Ω×cm after the pre-diffusion, and a paper source process is used in the pre-diffusion.
By adopting the technical scheme, the paper source technology is preferably adopted in the pre-diffusion process, so that the uniformity of diffusion source distribution can be improved, the chips can obtain consistent diffusion parameters, the square resistance of an N area is reduced, the forward voltage drop of the chips is further reduced, and the total power consumption of products is reduced.
Optionally, in step S2, the back-grinding thickness is 15-20 μm.
Optionally, in step S2, the resistance square resistance R (Γ) after boron diffusion is 0.10-0.12 Ω cm, and the junction depth is 90-110 μm.
By adopting the technical scheme, the resistor and junction depth in the boron diffusion process are optimized, boron can be uniformly deposited on the surface of the wafer, a dead layer is not easy to form, and the service performance and the service life of a chip product are effectively improved.
Optionally, in step S2, the thickness of the wafer after double-sided lapping is 175-185 μm.
Through adopting above-mentioned technical scheme, fully reduce the total thickness of chip through two-sided attenuate, the total thickness of wafer is suitable, can make the structure of chip product compacter, reduces the material quantity.
Optionally, in step S2, the surface metallization includes the steps of: placing the diffusion sheet subjected to double-sided grinding into corrosive liquid for corrosion, cleaning by using phosphoric acid solution, chemical nickel plating, cleaning and drying, deep burning, acid washing, secondary nickel plating, cleaning and drying, deep burning, acid washing, gold plating and drying; wherein the thickness of single nickel plating is less than or equal to 0.3 mu m, and the thickness of gold plating is less than or equal to 0.02 mu m.
By adopting the technical scheme, double-layer nickel plating and surface metallization treatment are performed on the surface of the wafer, the thickness of the nickel plating layer is reduced, the surface stress caused by the metallization treatment on the surface of the wafer is effectively reduced, thinner gold is electroplated on the surface, the overall structure of the wafer is less in change, the storage time of the wafer in normal temperature and normal humidity can be effectively prolonged due to the inertia of the gold, the weldability of the wafer is improved, and the stability of chip products is improved.
Optionally, in step S3, a soldering lug with a silver content of not less than 3% and a thickness of 0.1mm-0.25mm is selected for the soldering operation.
Through adopting above-mentioned technical scheme, select thick soldering lug to carry out encapsulation processing, can effectively reduce the chip and thin the back probability that takes place to warp, effectively improve the chip anti stress impact ability, maintain the result of use of chip product.
Optionally, in step S3, in the welding process, the temperature of the welding furnace is 313-335 ℃, and the time when the temperature of the welding furnace is greater than 300 ℃ is controlled within 7.5-12 min.
By adopting the technical scheme, the welding temperature is optimized, and the welding treatment is carried out at a lower temperature, so that the welding air holes of the wafer are smaller, the forward voltage drop and the consistency of voltage are improved, and the problem of overlarge welding air holes of the tunnel furnace is effectively solved.
Optionally, in step S3, during the second aging, the wafer is baked for 12-16 hours.
By adopting the technical scheme, the reflow soldering is easier to generate stress damage to the wafer, and the wafer is baked to release the stress impact damage generated in the reflow soldering.
In summary, the application has the following beneficial effects:
1. the wafer is ground and welded at low temperature, so that the welding air holes are smaller in packaging, the forward voltage drop and the voltage consistency are better, and the problem that the welding air holes of the tunnel furnace are overlarge can be solved.
2. According to the application, the thickness of the nickel plating layer on the surface of the wafer is reduced, the surface stress caused by metallization is reduced, the thinner gold plating layer is added, the overall cost is basically unchanged, the storage time of the wafer at normal temperature and normal humidity can be effectively prolonged, and the stability and weldability of the product are improved.
3. The manufacturing method can solve the problem of stress damage of the thin large-size chip under severe temperature change, and improves the stress resistance and the welding heat resistance of the thin chip product.
4. The manufacturing method of the application can improve the surge level to a certain extent from 140A-to 170A.
5. The manufacturing method of the application can realize faster switching time and smaller forward voltage drop under the same chip size.
Drawings
FIG. 1 is a schematic diagram of a polishing method according to an embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to examples.
Examples
Example 1
The application provides a manufacturing method of an axial ultrathin chip product, which comprises the following steps:
s1, selecting a wafer: selecting a radial single crystal wafer with resistivity of 15 omega cm and thickness of 220 μm 111 as the wafer to be processed;
S2, processing a wafer:
s21, front grinding: grinding the front surface of the wafer to be processed, wherein the grinding thickness is 5 mu m;
s22, pre-diffusion: adopting a paper source process to perform phosphorus pre-diffusion, wherein after the phosphorus pre-diffusion, the square resistance R ∈0.36 Ω×cm;
S23, back grinding: carrying out back grinding on the wafer after phosphorus pre-diffusion, wherein the grinding thickness is 15 mu m;
S24, boron diffusion: performing boron diffusion on the wafer subjected to back grinding, wherein in the boron diffusion, the square resistance R (sub-square resistance) is controlled to be 0.1 omega (cm), and the junction depth is controlled to be 90 mu m;
S25, double-sided grinding: double-sided grinding is carried out on the wafer after boron diffusion, so that the thickness of the wafer is 180 mu m;
S26, gold plating: placing the wafer subjected to double-sided grinding into polishing solution (hydrofluoric acid: buffer mass ratio is 1:20), carrying out corrosion treatment for 30s, repeating for three times, cleaning, placing the wafer into Hamo powder solution with mass fraction of 5%, soaking for 30s, washing with hot water, cleaning with acid liquor (H 3PO4:H2O2:H2 O mass ratio is 1:1:5), washing with water, nickel plating, controlling the thickness of a nickel layer to be 0.3 mu m, cleaning, drying, deep firing, acid liquor rinsing to remove surface oxidation, carrying out secondary nickel plating, controlling the thickness of the nickel layer to be 0.3 mu m, cleaning, drying, deep firing, acid liquor rinsing to remove surface oxidation, gold plating, gold layer thickness to be 0.02 mu m, washing, spin-drying, and drying at 75 ℃ for 20min;
S27, scribing: dicing the wafer subjected to gold plating treatment to obtain an intermediate wafer;
s3, packaging:
S31, welding: carrying out welding treatment on the intermediate wafer, specifically adopting solder with the thickness of 0.1mm and 3% of silver, controlling the temperature of a welding furnace to 313-335 ℃, and maintaining the temperature of the welding furnace to be more than or equal to 300 ℃ for 7.5min;
S32, acid washing: carrying out acid pickling corrosion on the welded chip, and carrying out acid pickling corrosion at the temperature of 21 ℃;
S33, intermediate processing: performing gluing, curing, mould pressing and aging treatment on the chip subjected to the acid washing treatment to obtain a semi-finished diode;
s34, reflow soldering treatment: the semi-finished diode is taken and subjected to reflow soldering, and specifically, when the size of a chip is larger than 88mil, the number of times of reflow soldering is 2 times; when the chip size is smaller than 88mil, the number of reflow soldering is two;
s35, secondary aging: and (5) baking the semi-finished diode subjected to reflow soldering at 150 ℃ for 12 hours.
Example 2
The application provides a manufacturing method of an axial ultrathin chip product, which comprises the following steps:
S1, selecting a wafer: selecting single crystal wafer with resistivity of 18 ohm cm and thickness of 230 μm 111 radial as wafer to be processed;
S2, processing a wafer:
s21, front grinding: grinding the front surface of the wafer to be processed, wherein the grinding thickness is 8 mu m;
S22, pre-diffusion: adopting a paper source process to perform phosphorus pre-diffusion, wherein after the phosphorus pre-diffusion, the square resistance R ∈0.40 Ω×cm;
S23, back grinding: carrying out back grinding on the wafer after phosphorus pre-diffusion, wherein the grinding thickness is 18 mu m;
S24, boron diffusion: performing boron diffusion on the wafer subjected to back grinding, wherein in the boron diffusion, the square resistance R (sub-square resistance) is controlled to be 0.11 omega (cm), and the junction depth is controlled to be 100 mu m;
s25, double-sided grinding: double-sided grinding is carried out on the wafer after boron diffusion, so that the thickness of the wafer is 185 mu m;
S26, gold plating: placing the wafer subjected to double-sided grinding into polishing solution (hydrofluoric acid: buffer mass ratio is 1:20), carrying out corrosion treatment for 30s, repeating for three times, cleaning, placing the wafer into Hamo powder solution with mass fraction of 5%, soaking for 30s, washing with hot water, cleaning with acid liquor (H 3PO4:H2O2:H2 O mass ratio is 1:1:5), washing with water, nickel plating, controlling the thickness of a nickel layer to be 0.3 mu m, cleaning, drying, deep firing, acid liquor rinsing to remove surface oxidation, carrying out secondary nickel plating, controlling the thickness of the nickel layer to be 0.3 mu m, cleaning, drying, deep firing, acid liquor rinsing to remove surface oxidation, gold plating, gold layer thickness to be 0.02 mu m, washing, spin-drying, and drying at 75 ℃ for 25min;
S27, scribing: dicing the wafer subjected to gold plating treatment to obtain an intermediate wafer;
s3, packaging:
S31, welding: carrying out welding treatment on the intermediate wafer, specifically adopting solder with the thickness of 0.15mm and 3% of silver, controlling the temperature of a welding furnace to 313-335 ℃, and maintaining the temperature of the welding furnace to be more than or equal to 300 ℃ for 10min;
S32, acid washing: carrying out acid pickling corrosion on the welded chip, and carrying out acid pickling corrosion at the temperature of 21 ℃;
S33, intermediate processing: performing gluing, curing, mould pressing and aging treatment on the chip subjected to the acid washing treatment to obtain a semi-finished diode;
s34, reflow soldering treatment: the semi-finished diode is taken and subjected to reflow soldering, and specifically, when the size of a chip is larger than 88mil, the number of times of reflow soldering is 2 times; when the chip size is smaller than 88mil, the number of reflow soldering is two;
S35, secondary aging: and (5) baking the semi-finished diode subjected to reflow soldering at 150 ℃ for 14 hours.
Example 3
The application provides a manufacturing method of an axial ultrathin chip product, which comprises the following steps:
S1, selecting a wafer: selecting single crystal wafer with resistivity 23 ohm cm and thickness 240 μm 111 radial as wafer to be processed;
S2, processing a wafer:
s21, front grinding: grinding the front surface of the wafer to be processed, wherein the grinding thickness is 10 mu m;
S22, pre-diffusion: adopting a paper source process to perform phosphorus pre-diffusion, wherein after the phosphorus pre-diffusion, the square resistance R ∈0.45 Ω×cm;
s23, back grinding: carrying out back grinding on the wafer after phosphorus pre-diffusion, wherein the grinding thickness is specifically 20 mu m;
S24, boron diffusion: performing boron diffusion on the wafer subjected to back grinding, wherein in the boron diffusion, the square resistance R (sub-square resistance) is controlled to be 0.12 omega (cm), and the junction depth is 110 mu m;
S25, double-sided grinding: double-sided grinding is carried out on the wafer after boron diffusion, so that the thickness of the wafer is 190 mu m;
S26, gold plating: placing the wafer subjected to double-sided grinding into polishing solution (hydrofluoric acid: buffer mass ratio is 1:20), carrying out corrosion treatment for 30s, repeating for three times, cleaning, placing the wafer into Hamo powder solution with mass fraction of 5%, soaking for 30s, washing with hot water, cleaning with acid liquor (H 3PO4:H2O2:H2 O mass ratio is 1:1:5), washing with water, nickel plating, controlling the thickness of a nickel layer to be 0.3 mu m, cleaning, drying, deep firing, acid liquor rinsing to remove surface oxidation, carrying out secondary nickel plating, controlling the thickness of the nickel layer to be 0.3 mu m, cleaning, drying, deep firing, acid liquor rinsing to remove surface oxidation, gold plating, gold layer thickness to be 0.02 mu m, washing, spin-drying, and drying at 75 ℃ for 30min;
S27, scribing: dicing the wafer subjected to gold plating treatment to obtain an intermediate wafer;
s3, packaging:
s31, welding: carrying out welding treatment on the intermediate wafer, specifically adopting solder with the thickness of 0.1mm and 3% of silver, controlling the temperature of a welding furnace to 313-335 ℃, and maintaining the temperature of the welding furnace to be more than or equal to 300 ℃ for 12min;
S32, acid washing: carrying out acid pickling corrosion on the welded chip, and carrying out acid pickling corrosion at the temperature of 21 ℃;
S33, intermediate processing: performing gluing, curing, mould pressing and aging treatment on the chip subjected to the acid washing treatment to obtain a semi-finished diode;
S34, reflow soldering treatment: the semi-finished diode is taken and subjected to reflow soldering, and specifically, when the size of a chip is larger than 88mil, the number of times of reflow soldering is 2 times; when the chip size is smaller than 88mil, the number of reflow soldering is 1 time;
s35, secondary aging: and (5) baking the semi-finished diode subjected to reflow soldering at 150 ℃ for 16 hours.
Comparative example
Comparative example 1
The application provides a manufacturing method of an axial ultrathin chip product, which comprises the following steps:
s1, selecting a wafer: selecting a radial single crystal wafer with resistivity of 15 omega cm and thickness of 220 μm 111 as the wafer to be processed;
S2, processing a wafer:
s21, pre-diffusion: adopting a paper source process to perform phosphorus pre-diffusion, wherein after the phosphorus pre-diffusion, the square resistance R ∈0.36 Ω×cm;
s22, back grinding: carrying out back grinding on the wafer after phosphorus pre-diffusion, wherein the grinding thickness is 15 mu m;
S23, boron diffusion: performing boron diffusion on the wafer subjected to back grinding, wherein in the boron diffusion, the square resistance R (sub-square resistance) is controlled to be 0.1 omega (cm), and the junction depth is controlled to be 90 mu m;
s24, double-sided grinding: double-sided grinding is carried out on the wafer after boron diffusion, so that the thickness of the wafer is 180 mu m;
S25, gold plating: placing the wafer subjected to double-sided grinding into polishing solution (hydrofluoric acid: buffer mass ratio is 1:20), carrying out corrosion treatment for 30s, repeating for three times, cleaning, placing the wafer into Hamo powder solution with mass fraction of 5%, soaking for 30s, washing with hot water, cleaning with acid liquor (H 3PO4:H2O2:H2 O mass ratio is 1:1:5), washing with water, nickel plating, controlling the thickness of a nickel layer to be 0.3 mu m, cleaning, drying, deep firing, rinsing with acid liquor to remove surface oxidation, carrying out secondary nickel plating, controlling the thickness of the nickel layer to be 0.3 mu m, cleaning and drying;
S26, scribing: dicing the wafer subjected to gold plating treatment to obtain an intermediate wafer;
s3, packaging:
S31, welding: carrying out welding treatment on the intermediate wafer, specifically adopting solder with the thickness of 0.1mm and 3% of silver, controlling the temperature of a welding furnace to 313-335 ℃, and maintaining the temperature of the welding furnace to be more than or equal to 300 ℃ for 7.5min;
s32, acid washing: carrying out acid pickling corrosion on the welded chip;
s33, intermediate processing: and (3) carrying out gluing, curing, mould pressing and aging treatment on the chip subjected to the acid washing treatment to obtain the semi-finished diode.
Performance test
(1) Surge capability test: and (5) carrying out surge capability test on the diode product by using a PIF8000 test system.
The diode products of examples 1-3 all have a surge capability of 170A/mm 2, and specifically the diode product of example 1 has a surge capability of 170A/mm 2. The surge capacity of the diode product in example 2 was 175A/mm 2. The surge capacity of the diode product in example 3 was 172A/mm 2. The surge capacity of the diode product in comparative example 1 was 140A/mm 2.
The present embodiment is only for explanation of the present application and is not to be construed as limiting the present application, and modifications to the present embodiment, which may not creatively contribute to the present application as required by those skilled in the art after reading the present specification, are all protected by patent laws within the scope of claims of the present application.
Claims (10)
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| CN104701386A (en) * | 2015-02-11 | 2015-06-10 | 株洲南车时代电气股份有限公司 | Matchable fast recovery diode (FRD) of integrated gate commutate thyristor and manufacturing method of matchable fast recovery diode |
| CN109755116A (en) * | 2017-11-01 | 2019-05-14 | 天津环鑫科技发展有限公司 | Method for manufacturing unidirectional TVS chip by adopting printing process |
| CN111403366A (en) * | 2020-03-19 | 2020-07-10 | 常州星海电子股份有限公司 | Transient diode and packaging process thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104701386A (en) * | 2015-02-11 | 2015-06-10 | 株洲南车时代电气股份有限公司 | Matchable fast recovery diode (FRD) of integrated gate commutate thyristor and manufacturing method of matchable fast recovery diode |
| CN109755116A (en) * | 2017-11-01 | 2019-05-14 | 天津环鑫科技发展有限公司 | Method for manufacturing unidirectional TVS chip by adopting printing process |
| CN111403366A (en) * | 2020-03-19 | 2020-07-10 | 常州星海电子股份有限公司 | Transient diode and packaging process thereof |
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