CN118837726A - MEMS chip testing method and system and storage medium - Google Patents

Abstract

The present application proposes a test method, system and storage medium for MEMS chips. The method includes: the FPGA board is connected to the MCU, and is connected to a number of MEMS chips through its own multiple interfaces, each interface is connected to a MEMS chip, and the MCU is also connected to the host computer; the FPGA board transmits the control instructions received from the host computer to each MEMS chip in parallel; the FPGA board receives the test data transmitted in parallel by each MEMS chip; the FPGA board sends the test data to the MCU, so that the MCU analyzes the test data and sends the analysis results to the host computer, or the FPGA board analyzes the test data and sends the analysis results to the MCU so that the MCU sends them to the host computer. The present application can reduce chip testing time, improve testing efficiency, and can also achieve targeted automatic calibration according to the differences between each MEMS chip.

Description

MEMS chip testing method and system, storage medium

Technical Field

The present application relates to the field of chip testing, and specifically to a testing method and system for a MEMS (Micro Electro Mechanical System) chip, and a storage medium.

Background Art

At present, MEMS chips used to control IMU (Inertial Measurement Unit) or gyroscopes need to be tested before leaving the factory to ensure that the final MEMS chips on the market have good performance. The existing technology usually collects the data generated by the MEMS chip based on the MCU (Micro-controller Unit) of the test machine. This data can be called "test data", and judges whether the MEMS chip meets the factory requirements based on the test data. The MCU and each MEMS chip use serial transmission to transmit test data, but the efficiency of the serial transmission method is slow. Generally speaking, it takes about 20 minutes for each MEMS chip to perform inertial angle testing and calibration. If there are a large number of MEMS chips to be tested, it will take longer, which will undoubtedly seriously affect the test efficiency and factory efficiency of the MEMS chip.

Summary of the invention

In view of this, the present application provides a test method and system for a MEMS chip, and a storage medium, which can at least improve the problem of low efficiency in existing testing of MEMS chips.

The present application provides a method for testing a MEMS chip, wherein the MEMS chip is used to control multiple axes of an IMU or a gyroscope, and the method comprises:

The FPGA (Field Programmable Gate Array) board is connected to the MCU and is connected to several MEMS chips through its own multiple interfaces, each interface is connected to a MEMS chip, and the MCU is also connected to the host computer;

The FPGA board transmits the control instructions received from the host computer to each MEMS chip in parallel;

The FPGA board receives test data transmitted in parallel by each MEMS chip;

The FPGA board sends the test data to the MCU, so that the MCU analyzes the test data and sends the analysis results to the host computer, or the FPGA board analyzes the test data and sends the analysis results to the MCU, so that the MCU sends them to the host computer.

Optionally, each MEMS chip is disposed on the FPGA board; the method further includes:

The FPGA board is provided with a temperature sensor to detect the current temperature of each MEMS chip;

The FPGA board sends the current temperature to the MCU, so that the MCU determines whether the preset temperature is reached, and generates a trigger instruction when it is determined that the current temperature reaches the preset temperature;

In response to receiving the trigger instruction from the MCU, the FPGA board executes the step of transmitting the control instruction received from the host computer to each MEMS chip in parallel.

Optionally, the method further includes:

The FPGA board collects analog signals transmitted in parallel when each MEMS chip is powered on;

The FPGA board converts the collected analog signal into a digital signal;

The FPGA board calibrates each MEMS chip according to the digital signal.

Optionally, the test data is obtained by testing each axis of the IMU or gyroscope at a number of parameter locations; the FPGA board calibrates each MEMS chip according to the digital signal, including:

For two adjacent parameter sites, before outputting an analog signal to the latter parameter site, the calibration of the corresponding MEMS chip is completed according to the digital signal generated by the former parameter site.

Optionally, the test data is presented as a package, the package includes a data header, a data type, a source number, a data length and data content, the source number indicates the MEMS chip from which the test data comes; the method further includes:

The FPGA board acquires data of each axis from the test data;

Create a storage queue for each axis that obtains data and store the corresponding data;

According to the source number and the number of the storage queues, it is determined whether the test data of all MEMS chips are received; and, if so, it is determined that the collection of the test data is completed; if not, the test data transmitted in parallel by each MEMS chip is continuously received.

Optionally, the method further includes:

S11: connecting the multiple interfaces, selecting one of the MEMS chips to send an inquiry packet containing its own identification and the number of storage queues, wherein the storage queue is created when the data corresponding to each axis is obtained from the test data, and a storage queue is created for each axis;

S12: After receiving the inquiry packet, the remaining MEMS chips compare their current storage queue quantities with the storage queue quantity of one of the MEMS chips;

S13: For any of the remaining MEMS chips, if the current storage queue quantity is less than the storage queue quantity of one of the MEMS chips, an inquiry packet is issued;

S14: For any of the remaining MEMS chips, if the current storage queue quantity is greater than or equal to the storage queue quantity of one of the MEMS chips, no inquiry packet is sent;

Repeating S11 to S14 until only one MEMS chip remains;

In response to receiving the packaging package transmitted by the last remaining MEMS chip, it is determined that the test data of all MEMS chips are received, and it is determined that the collection of the test data is completed.

Optionally, the package includes a data header, a data type, a source number, a data length, and data content, wherein the source number indicates the MEMS chip from which the test data comes and identifies the last remaining MEMS chip; the method further includes:

The FPGA board determines that there is only one remaining MEMS chip based on the source number.

Optionally, the method further includes:

Obtain the maximum time duration from when an inquiry packet is sent from one MEMS chip to when it is received by another MEMS chip;

When the time from the last detection of the inquiry packet exceeds the maximum time length, no inquiry packet is received, and it is determined that there is only one MEMS chip left.

The present application provides a MEMS chip testing system, comprising a host computer, an MCU and an FPGA board, wherein the FPGA board is connected to the MCU, the FPGA board is provided with a plurality of interfaces for connecting to a plurality of MEMS chips, each of the interfaces is connected to a MEMS chip, and the MCU is connected to the host computer; wherein the FPGA board, the host computer and the MCU perform the test of the MEMS chip by the method described in any one of the above items.

The present application provides a storage medium storing a test program, which, when executed by a processor, implements corresponding steps of the MEMS chip test method as described in any one of the above items.

As described above, the present application receives the test data generated by each MEMS chip through the FPGA board, and the test data is transmitted between the FPGA board and each MEMS chip through a parallel transmission method. The parallel transmission method enables the test data to be transmitted simultaneously through multiple lines. More test data can be transmitted in the same time, thereby reducing the test time of the MEMS chip and improving the test efficiency.

In addition, the present application can collect the analog signals transmitted in parallel when each MEMS chip is powered on through the FPGA board, and calibrate each MEMS chip accordingly. Hereby, targeted automatic calibration can be implemented according to the differences between each MEMS chip to ensure the optimal performance of each MEMS chip.

Furthermore, the present application can obtain the data of each axis of the IMU or gyroscope from the test data through the FPGA board, and create a storage queue every time the data of one axis is obtained, and store the corresponding data, and then determine whether the test data of all MEMS chips is received based on the source number carried in the test data and the number of storage queues, thereby automatically determining whether the test data collection is completed.

The present application can also connect multiple interfaces through an FPGA board to interconnect multiple MEMS chips. These MEMS chips determine whether to send an inquiry packet by comparing the number of storage queues, and thereby determine whether it is the last MEMS chip to send an inquiry packet. Based on this, the present application can automatically determine whether the test data has been collected through the interconnection between these MEMS chips without the need for any of the FPGA board, MCU, and host computer to execute, which can reduce the amount of calculation of any of the FPGA board, MCU, and host computer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic flow chart of a method for testing a MEMS chip according to an embodiment of the present application;

FIG2 is a schematic diagram of the structure of a MEMS chip testing system according to an embodiment of the present application;

FIG3 is a schematic diagram of the interaction between a MEMS chip, an FPGA board, an MCU and a host computer during a test process provided by an embodiment of the present application;

FIG4 is a schematic diagram of another interaction between a MEMS chip, an FPGA board, an MCU and a host computer during a test process provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of a process for detecting whether test data collection is completed according to an embodiment of the present application.

DETAILED DESCRIPTION

In order to solve the above problems existing in the prior art, the present application provides a test method and system for a MEMS chip, and a storage medium. These protection themes are based on the same concept, and the principles for solving the problems are basically the same or similar. The implementation methods of each protection theme can refer to each other, and the repeated parts will not be repeated.

In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be clearly described below in conjunction with specific embodiments and corresponding drawings. Obviously, the embodiments described below are only part of the embodiments of the present application, not all of the embodiments. In the absence of conflict, the following embodiments and their technical features can be combined with each other and also belong to the technical solutions of the present application.

FIG1 is a flow chart of a test method for a MEMS chip according to an embodiment of the present application. The test method for the MEMS chip can be referred to as a “method” or a “test method”, and its execution subject can be an FPGA board, which is a test board integrated with an FPGA. The MEMS chip is used to control multiple axes of an IMU or a gyroscope. Taking the IMU as an example, the MEMS chip is used to control three-axis accelerometers and three-axis gyroscopes to perform corresponding operations. The method of the present application is to test the results of the MEMS chip controlling the six axes to perform corresponding operations, so as to ensure the performance of the MEMS chip.

As shown in FIG. 1 , the method at least includes the following steps S1 to S4 .

S1: The FPGA board is connected to the MCU and several MEMS chips through its own multiple interfaces. Each interface is connected to a MEMS chip. The MCU is also connected to the host computer.

In conjunction with the scenario shown in FIG. 2 , the host computer is connected to the MCU, for example, a connection is established between the two through a slip ring, and the MCU is connected to multiple MEMS chips through a single FPGA board; a single FPGA board is provided with multiple interfaces, so a single FPGA board can achieve connection with the same number or less than the number of MEMS chips. The figure only shows six MEMS chips by way of example, and they are numbered 1 to n respectively, and the corresponding eight interfaces can be numbered 1 to n respectively, and the MEMS chips with the same number are connected to the interfaces one by one. It should be understood that other examples can set a single or more than two other numbers of FPGA boards to connect to an MCU to meet the test scenario requirements of other numbers of MEMS chips. The structures of the various FPGA boards can be exactly the same or different, and this application does not limit them. The various FPGA boards are interconnected, and data transmission and synchronous control are achieved accordingly.

This application refers to the interface connected to the MEMS chip as the first interface and the interface connected to the MCU as the second interface. In an example shown in Figure 2, the FPGA board is a test board with independent data processing and computing capabilities, and its first interface can be an interface such as an LPT interface, which has a wide range of usage scenarios. The second interface includes but is not limited to a TCP/UDP port, TCP is the transmission control protocol, and UDP is the user datagram protocol. Corresponding data can also be transmitted in parallel between the FPGA board and the MCU, such as transmitting log data and instruction data at the same time, to improve transmission efficiency.

The MEMS chip connected to the FPGA board can be called a chip to be tested. Here, a test connection is established between the host computer, the MCU and each chip to be tested through the FPGA board.

S2: The FPGA board transmits the control instructions received from the host computer to each MEMS chip in parallel.

S3: The FPGA board receives the test data transmitted in parallel by each MEMS chip.

S4: The FPGA board sends the test data to the MCU, so that the MCU analyzes the test data and sends the analysis results to the host computer, or the FPGA board analyzes the test data and sends the analysis results to the MCU, so that the MCU sends them to the host computer.

After step S1 and before step S2, referring to FIG. 3 and FIG. 4, the host computer (for example, through its test management program) issues a control instruction to the MCU, and the MCU forwards it to the FPGA board. The control instruction is used to test one or more of the MEMS chips connected to the FPGA board. Specifically, the control instruction can be distinguished according to the identifiers of the first interfaces carried, to which MEMS chip or chips the control instruction is issued. The control instruction can contain instruction data but not log data.

Each MEMS chip performs a corresponding test according to the control instruction it receives, and generates corresponding test data, which includes but is not limited to the acceleration value and angular velocity value of each axis of the IMU; the test data can be expressed as log data, and then each MEMS chip transmits the test data to the FPGA board through the corresponding first interface. Step S2 can be regarded as a step for the FPGA board to collect test data. In one example, each first interface can have a cache function to cache the test data transmitted by the corresponding MEMS chip. The first interface sends a reminder to the FPGA board when cached data is formed. After detecting the reminder, the FPGA board reads the cached data, thereby realizing parallel transmission between each MEMS chip and the FPGA board. The FPGA board can distinguish the corresponding MEMS chip by the number of the first interface. Taking the scenario shown in Figure 2 as an example, the test data generated and transmitted by the MEMS chip labeled 3 is transmitted through the first interface labeled 3.

In one example of step S4, after the test data of all MEMS chips are transmitted to the FPGA board, the FPGA board packages the test data together and sends them to the MCU; in another example, the FPGA board can send the test data of each MEMS chip to the MCU after receiving it.

As described above, the present application receives the test data generated by each MEMS chip through the FPGA board, and the test data is transmitted between the FPGA board and each MEMS chip through a parallel transmission method. Each MEMS chip and the corresponding first interface can be regarded as a data channel in the parallel transmission. The parallel transmission method enables the test data to be transmitted through multiple channels at the same time. More test data can be transmitted in the same time, thereby reducing the test time of the MEMS chip and improving the test efficiency.

In this application, the FPGA board can send the test data to the MCU for analysis by the MCU as shown in Figure 3, or the FPGA board can analyze the test data as shown in Figure 4. The specific process and principle of the MCU or FPGA board analyzing the test data can be found in the prior art and will not be repeated here. For example, the collected test data is compared with the data obtained by theoretical calculation. When the difference between the two exceeds the preset threshold, it is considered that the test of the current axis is unqualified. The host computer can record the test data and analysis results to form test-related log data.

The temperature of the environment in which the MEMS chip is located is more sensitive to the test results. Therefore, testing the MEMS chip can be understood as confirming whether the operating data of each axis of the IMU at different temperatures meets the preset requirements. Therefore, this application needs to detect whether the current temperature reaches the preset temperature before collecting test data. Referring to Figures 3 and 4, the method also includes:

S101: The FPGA board is provided with a temperature sensor, each MEMS chip is provided on the FPGA board, and the current temperature of each MEMS chip is detected by the temperature sensor.

S102: The FPGA board sends the current temperature to the MCU, so that the MCU determines whether the preset temperature is reached and generates a trigger instruction when it is determined that the current temperature reaches the preset temperature.

The MCU can read the temperature of the FPGA board in real time, and can perform the test after reaching the preset temperature required for the test. When the current temperature does not reach the preset temperature, no trigger instruction is generated, and S101 is continued to be executed.

S103: The FPGA board detects whether a trigger instruction is received from the MCU.

In response to receiving the trigger instruction from the MCU, the FPGA board executes step S2, that is, transmitting the control instruction received from the host computer to each MEMS chip in parallel.

The temperature sensor in the prior art is set on the platform where the MCU is located. The temperature obtained in the actual test is different from the temperature of the actual location of the MEMS chip, which will have an adverse effect on the test results. In this application example, the temperature sensor is placed on the FPGA board. The FPGA board can directly read the real-time temperature closest to each MEMS chip in real time, and the real-time temperature can be compensated more accurately to reach the theoretical preset temperature, thereby ensuring the accuracy of the test data.

Please continue to refer to FIG. 3 and FIG. 4 , the method further includes:

S104: The FPGA board collects analog signals transmitted in parallel when each MEMS chip is powered on.

S105: The FPGA board converts the collected analog signal into a digital signal.

S106: The FPGA board calibrates each MEMS chip according to the digital signal.

Before testing, this example calibrates each MEMS chip through the FPGA board. The MEMS chip can be configured to output analog signals through the pins when designing. In combination with the example shown in Figure 2, an ADC (Analog-to-Digital Converter) sampling chip can be added to the FPGA board. After each MEMS chip is connected to the FPGA board and powered on, it outputs different analog signals. The ADC sampling chip performs sampling and sends the sampled data to the FPGA board. The FPGA board performs real-time data analysis, and then configures the calibration register inside the MEMS chip through the FPGA board for calibration. By comparing the sampled data, it is confirmed whether the MEMS chip is calibrated. In this way, the optimal calibration parameters can be input for each MEMS chip. In one example, this application can pre-load the empirical value into the MEMS chip to reduce the automatic calibration time and improve the efficiency of the automatic calibration; the empirical value can be the historical calibration parameter when calibrating various types of MEMS chips before.

The prior art is to load all MEMS chips with pre-debugged calibration parameters uniformly through MCU, that is, the calibration parameters loaded by all MEMS chips are the same. The prior art cannot achieve targeted automatic calibration according to the differences between each MEMS chip, and it is difficult to ensure the optimal performance of each MEMS chip. This application collects the analog signals transmitted in parallel when each MEMS chip is powered on through the FPGA board, and calibrates each MEMS chip accordingly. It can be seen that this application can achieve targeted automatic calibration according to the differences between each MEMS chip, and ensure the optimal performance of each MEMS chip.

In the actual scenario of testing each MEMS chip, the present application can only select several parameter sites (also called "test points") to test each axis of the IMU or gyroscope, that is, the test data is obtained by testing each axis at several parameter sites. Based on this, in the process of the FPGA board calibrating each MEMS chip according to the digital signal, for two adjacent parameter sites, in time order, the previous parameter site is called the "previous parameter site" and the next parameter site is called the "next parameter site". Before outputting the analog signal to the next parameter site, the calibration of the corresponding MEMS chip is completed according to the digital signal generated by the previous parameter site. Here, the FPGA board can judge the status of the MEMS chip in real time and adjust the calibration parameters in real time. When it reaches the fixed test point, the calibration has been completed, thereby ensuring that the data collected at the test point is more accurate.

Before the FPGA board sends the test data to the MCU, or before the FPGA board analyzes the test data, the present application can detect whether the test data collection is completed through the FPGA board, that is, whether the test data collection of all axes of all MEMS chips is completed. If yes, execute the aforementioned step S4; if no, continue to collect test data until the collection is completed.

In one example, the FPGA board can detect whether the test data collection is complete based on the test data and its storage method. Specifically, in an actual scenario, the test data can be expressed as a package, which includes a data header, a data type, a source number, a data length, and a data content, wherein the source number indicates the MEMS chip from which the test data comes; here, the FPGA board can first parse the package to obtain the data corresponding to each axis from the test data, and then create a storage queue for each axis that obtains the data, and store the corresponding data; based on the source number and the number of storage queues, it is determined whether the test data of all MEMS chips has been received.

If the data of axis 1 is parsed from the package, storage queue 1 is created; if the data of axis 2 is parsed, storage queue 2 is created, and so on. Taking the MEMS chip used to control the IMU as an example, first determine whether the test data comes from all MEMS chips based on the source number. If not, it is determined that the test data of all MEMS chips has not been received. If so, check whether the number of storage queues is equal to the total number of axes of the IMU. If they are equal, it is determined that the test data of all MEMS chips has been received; if they are not equal, for example, the data of axes 1 to 5 are currently parsed, and storage queues 1 to 5 are created, then the number of storage queues is five, which is less than the total number of axes of the IMU (the total number of axes of the IMU is six), then it is determined that the test data of all MEMS chips has not been received.

That is to say, the present application can obtain the data of each axis from the test data through the FPGA board, and create a storage queue and store the corresponding data each time the data of an axis is obtained, and then judge whether the test data of all MEMS chips is received based on the source number carried in the test data and the number of storage queues, thereby automatically realizing the determination of whether the test data collection is completed.

In other examples, the present application can automatically determine whether the test data has been collected through the interconnection between the connected MEMS chips, without the need for any of the FPGA board, MCU and host computer to execute. Specifically, in conjunction with FIG5 , the method further includes the following steps:

S11: Connect multiple interfaces, select one MEMS chip to send an inquiry packet containing its own identification and the number of storage queues, wherein the storage queue is created when the data corresponding to each axis is obtained from the test data, and a storage queue is created for each axis;

S12: After receiving the inquiry packet, the remaining MEMS chips compare their current storage queue quantities with the storage queue quantity of one of the MEMS chips;

For any of the remaining MEMS chips, it is detected whether the current storage queue quantity of the chip itself is less than the preset storage queue quantity (which may be referred to as “preset storage queue quantity”).

S13: For any of the remaining MEMS chips, if the current storage queue quantity is less than the storage queue quantity of the one of the MEMS chips, an inquiry packet is issued;

S14: For any of the remaining MEMS chips, if the current storage queue quantity is greater than or equal to the storage queue quantity of the one of the MEMS chips, no inquiry packet is sent;

Repeating S11 to S14 until only one MEMS chip remains; and,

S15: In response to receiving the packaging package transmitted by the last remaining MEMS chip, it is determined that the test data of all MEMS chips are received, and the collection of the test data is completed.

One of the MEMS chips can be regarded as a MEMS chip that has completed data collection for all its axes. The current storage queue number of any other MEMS chip is less than its storage queue number, indicating that any other MEMS chip has not completed data collection for all axes.

In this example, multiple MEMS chips are interconnected through an FPGA board. These MEMS chips determine whether to send an inquiry packet by comparing the number of storage queues. Based on this, the last MEMS chip to send an inquiry packet is detected. When the package packet (i.e., test data) sent by the last MEMS chip is detected, it can be determined that the collection is completed without the need for any of the FPGA board, MCU, or host computer to execute it, which can reduce the amount of calculation for any of the FPGA board, MCU, or host computer.

The method for determining that there is only one remaining MEMS chip in this application includes but is not limited to the following:

Method 1: Based on the fact that the test data is represented by a package, and the package includes a data header, a data type, a source number, a data length, and data content, this example can set the bytes of the source number so that the source number indicates the MEMS chip from which the test data comes and identifies the last remaining MEMS chip; the FPGA board determines that there is only one remaining MEMS chip based on the source number.

Method 2: Before step S15, the FPGA board obtains the maximum time length from when an inquiry packet is sent from one MEMS chip to when it is received by another MEMS chip; and if no inquiry packet is received when the time length exceeding the maximum time length has passed since the last time an inquiry packet was detected, it is determined that there is only one MEMS chip left.

The embodiment of the present application also provides a test system for a MEMS chip, including a host computer, an MCU and an FPGA board; the FPGA board is connected to the MCU, the FPGA board is provided with multiple interfaces for connecting to a number of MEMS chips, each interface is connected to a MEMS chip, and the MCU is connected to the host computer; the structure of the test system can be seen in Figure 2. Among them, the FPGA board, the host computer and the MCU perform the test of the MEMS chip through any of the above examples.

An embodiment of the present application also provides a storage medium storing a test program, which, when executed by a processor, implements the steps corresponding to the test method of the MEMS chip in any of the above examples.

The storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

Since the program stored in the storage medium can execute the steps in any MEMS chip testing method provided in the embodiments of the present application, the beneficial effects that can be achieved by any MEMS chip testing method provided in the embodiments of the present application can be achieved, see the previous embodiments for details.

In addition, the FPGA board, communication board, host computer and storage medium provided in the embodiment of the present application are complete devices, and also have the corresponding structure of the known devices. The present application only provides an exemplary description of some structural elements involved in chip testing, and does not list other structural elements one by one. For example, the FPGA board can be provided with a data packaging module, a detection module, an acceleration calculation module, an angular velocity calculation module, and an automatic calibration module as shown in Figure 2. The data packaging module can send test data or analysis results to the MCU, the detection module can be used to analyze the test data, etc. The acceleration calculation module is used to test and obtain the acceleration value of each axis of the MEMS chip, the angular velocity calculation module is used to test and obtain the angular velocity value of each axis of the MEMS chip, and the automatic calibration module is used to calibrate each MEMS chip. These modules can be implemented by adapting hardware in actual scenarios. For example, two or more modules can be implemented as one hardware, and one module can be implemented by two or more hardware.

The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. For ordinary technicians in this field, all equivalent structural changes made using the contents of this specification and drawings are also included in the patent protection scope of the present application.

This document uses step codes such as S1, S2, etc., the purpose of which is to express the corresponding content more clearly and concisely, and does not constitute a substantial limitation on the order. When technical personnel in this field implement the specific steps, they may execute S2 first and then S1, etc., but these should all be within the scope of protection of this application.

Although the terms "first, second", etc. are used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. In addition, the singular forms "one", "an", and "the" are intended to include plural forms as well. The terms "or" and "and/or" are interpreted as inclusive, or mean any one or any combination. Only when the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way, an exception to this definition will occur.

Claims (10)

1. A method for testing a MEMS chip, wherein the MEMS chip is used to control multiple axes of an inertial measurement unit (IMU) or a gyroscope, and the method comprises: The FPGA board is connected to the MCU and is connected to several MEMS chips through its own multiple interfaces, each interface is connected to a MEMS chip, and the MCU is also connected to the host computer; The FPGA board transmits the control instructions received from the host computer to each MEMS chip in parallel; The FPGA board receives test data transmitted in parallel by each MEMS chip; The FPGA board sends the test data to the MCU, so that the MCU analyzes the test data and sends the analysis results to the host computer, or the FPGA board analyzes the test data and sends the analysis results to the MCU, so that the MCU sends them to the host computer. 2. The method according to claim 1, characterized in that each MEMS chip is arranged on the FPGA board; the method further comprises: The FPGA board is provided with a temperature sensor to detect the current temperature of each MEMS chip; The FPGA board sends the current temperature to the MCU, so that the MCU determines whether the preset temperature is reached, and generates a trigger instruction when it is determined that the current temperature reaches the preset temperature; In response to receiving the trigger instruction from the MCU, the FPGA board executes the step of transmitting the control instruction received from the host computer to each MEMS chip in parallel. 3. The method according to claim 1, characterized in that the method further comprises: The FPGA board collects analog signals transmitted in parallel when each MEMS chip is powered on; The FPGA board converts the collected analog signal into a digital signal; The FPGA board calibrates each MEMS chip according to the digital signal. 4. The method according to claim 3, characterized in that the test data is obtained by testing each axis of the IMU or gyroscope at several parameter locations; The FPGA board calibrates each MEMS chip according to the digital signal, including: For two adjacent parameter sites, before outputting an analog signal to the latter parameter site, the calibration of the corresponding MEMS chip is completed according to the digital signal generated by the former parameter site. 5. The method according to any one of claims 1 to 4, characterized in that the test data is expressed as a package, the package includes a data header, a data type, a source number, a data length and data content, and the source number indicates the MEMS chip from which the test data comes; The method further comprises: The FPGA board acquires data of each axis from the test data; Create a storage queue for each axis that obtains data and store the corresponding data; According to the source number and the number of the storage queues, it is determined whether the test data of all MEMS chips are received; and if so, it is determined that the collection of the test data is completed. 6. The method according to any one of claims 1 to 4, characterized in that the method further comprises: S11: connecting the multiple interfaces, selecting one of the MEMS chips to send an inquiry packet containing its own identification and the number of storage queues, wherein the storage queue is created when the data corresponding to each axis is obtained from the test data, and a storage queue is created for each axis; S12: After receiving the inquiry packet, the remaining MEMS chips compare their current storage queue quantities with the storage queue quantity of one of the MEMS chips; S13: For any of the remaining MEMS chips, if the current storage queue quantity is less than the storage queue quantity of one of the MEMS chips, an inquiry packet is issued; S14: For any of the remaining MEMS chips, if the current storage queue quantity is greater than or equal to the storage queue quantity of one of the MEMS chips, no inquiry packet is sent; Repeating S11 to S14 until only one MEMS chip remains; In response to receiving the packaging package transmitted by the last remaining MEMS chip, it is determined that the test data of all MEMS chips are received, and it is determined that the collection of the test data is completed. 7. The method according to claim 6, characterized in that the package includes a data header, a data type, a source number, a data length and data content, the source number indicates the MEMS chip from which the test data comes and identifies the last remaining MEMS chip; the method further comprises: The FPGA board determines that there is only one remaining MEMS chip based on the source number. 8. The method according to claim 6, characterized in that the method further comprises: Obtain the maximum time duration from when an inquiry packet is sent from one MEMS chip to when it is received by another MEMS chip; When the time from the last detection of the inquiry packet exceeds the maximum time length, no inquiry packet is received, and it is determined that there is only one MEMS chip left. 9. A testing system for a MEMS chip, characterized in that it comprises a host computer, an MCU and a FPGA board, wherein the FPGA board is connected to the MCU, the FPGA board is provided with a plurality of interfaces for connecting to a plurality of MEMS chips, each of the interfaces is connected to a MEMS chip, and the MCU is connected to the host computer; wherein the FPGA board, the host computer and the MCU perform the test of the MEMS chip through the method described in any one of claims 1 to 8. 10. A storage medium, characterized in that a test program is stored on the storage medium, and when executed by a processor, the test method of the MEMS chip according to any one of claims 1 to 8 is implemented.