CN115656769A - FPGA multi-chip parallel test method, device and computer equipment - Google Patents

Abstract

The application relates to a parallel testing method, device, computer equipment, storage medium and computer program product of FPGA multi-chips. The method comprises: receiving the functional test signal of the test channel of the ATE test system through the corresponding pins of the tested FPGA chip located at least two test positions on the first test board, and testing the tested functional modules of each tested FPGA chip according to the test signal Carry out function test in parallel, obtain the function test result of at least two FPGA chips, be positioned at the FPGA chip under test of the second test board to receive the test signal of ATE test system test channel through corresponding pin, carry out electrical performance test according to test signal, obtain The electrical performance test results of the FPGA chip. This method decouples the functional test and electrical performance test of the FPGA chip, and solves the contradiction between the multi-pin FPGA chip test requirements and the limited test channels of the ATE machine by performing functional tests in parallel, shortens the test time, and improves the test efficiency of the FPGA chip , to achieve rapid testing of batch chips.

Description

FPGA multi-chip parallel test method, device and computer equipment

technical field

The present application relates to the technical field of chip testing, in particular to a FPGA multi-chip parallel testing method, device, computer equipment storage medium and computer program product.

Background technique

A field programmable gate array (FPGA) chip (field programmable gate array, FPGA) has the advantages of high logic density, repeatable configuration, and online programming. With the continuous advancement of semiconductor manufacturing technology, FPGA is developing rapidly towards high speed, large capacity, high density, and multi-function. The scale of internal resources has reached tens of millions or even hundreds of millions of gates, and the number of chip pins has increased from a few hundred to more than 1,000 pins. .

Chip testing is an important way to ensure the quality of FPGA products. As the integration scale of FPGA chips continues to increase, the number of chip pins is increasing. At the same time, with the increase of domestic FPGA chip market size and application demand, the mass production scale of a single model has reached tens of thousands to hundreds of thousands of pieces, and the demand for chip mass production testing has surged, which puts forward the demand for efficient and fast testing of FPGA. In recent years, the FPGA chip testing method based on the ATE (Auto test equipment) automated test system has become the mainstream technology for batch FPGA chip testing due to its high test efficiency and fast test speed.

At present, the number of pins of large-scale advanced FPGA chips has reached more than 1,000 pins, and the demand for chip testing is large, while the number of channels of existing integrated circuit ATE test machines generally does not exceed 2,000. ATE test system Due to the limitation of test channel resources, for FPGA chips with thousands of pins, existing ATE test machines can only perform single-chip tests. For large-capacity, high-density, high-speed FPGA chips, internal functional modules such as digital processor DSP, phase-locked loop PLL, digital clock management unit DCM, controller, and high-speed interface are complex, the scale of test vectors is large, and the test time of a single chip It can reach more than 10 minutes, and the test cost is high, which seriously affects the scale test of mass-produced chips. Therefore, for large-scale FPGA chips with thousands of pins, there are problems of long chip test time, high test cost and low test efficiency, which seriously affect the scale test of mass-produced chips.

Contents of the invention

Based on this, it is necessary to address the above-mentioned technical problems to provide a method, device, computer equipment and computer-readable storage medium for utilizing an ATE test system to realize parallel testing of a large-scale thousand-level quantity pin FPGA multi-chip, improve test efficiency, and reduce Test time and cost.

In a first aspect, the present application provides a method for parallel testing of FPGA multi-chips with thousands of pins by using an ATE test system. The methods include:

The FPGA chip under test that is positioned at at least two test positions on the first test board receives the functional test signal of the ATE test system test channel through the corresponding pin, and parallelizes the tested functional modules of each of the FPGA chips under test according to the clock signal Carry out functional test, obtain the functional test result of at least two described FPGA chips;

The FPGA chip under test on the second test board receives the test signal of the test channel of the ATE test system through the corresponding pin, performs an electrical performance test according to the test signal, and obtains the electrical performance test result of the FPGA chip.

In one of the embodiments, the FPGA chip under test on the first test board receives the functional test signal of the test channel of the ATE test system through the corresponding pin, and the tested FPGA chip of each FPGA chip under test is tested according to the test signal. Test function module to carry out functional test, obtain the functional test result of described FPGA chip, comprise:

The measured FPGA chip located on the first test board receives the clock signal of the ATE test system test channel through the corresponding pin;

According to the clock signal, the FPGA chip built-in self-test vector generation module generates test vectors;

Applying the test vector to the tested functional module of the FPGA chip to obtain actual output;

Comparing the expected output of the test vector and the actual output, obtain the test result of the tested functional module of the FPGA chip;

According to the test results of each of the tested functional modules, the functional test results of the FPGA chip are obtained.

In one of the embodiments, the second test board includes a test position; the number of test channels required for the electrical performance detection is greater than the number of test channels required for the functional performance test, which is close to the test of the ATE test system number of channels.

In one embodiment, the method also includes:

Obtain the test results of the tested functional modules of the FPGA chip under test in different test positions of the first test board;

If the test results of the tested functional modules of the tested FPGA chip in different test positions are qualified, then verify that the test of the tested functional modules of the FPGA chip passes.

In one of the embodiments, the test channel is configured in advance according to pin definition, and the configuration includes power configuration, IO configuration, voltage/current configuration and timing configuration.

In one of the embodiments, the first test board includes four test positions; four FPGA chips to be tested are placed on the test positions at the same time for functional testing in parallel.

In the second aspect, the present application also provides a parallel testing device for FPGA multi-chips. The devices include:

Functional test module, the FPGA chip under test at least two test positions on the first test board is used to receive the functional test signal of the ATE test system test channel through the corresponding pin, and each described FPGA chip under test according to the test signal The tested functional modules are functionally tested in parallel to obtain functional performance test results of at least two FPGA chips;

Electrical performance test module, the described measured FPGA chip that is positioned at the second test board is used for receiving the test signal of ATE test system test channel by corresponding pin, carries out electrical performance test according to described test signal, obtains the described FPGA chip Electrical performance test results.

In a third aspect, the present application also provides a computer device. The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

The FPGA chip under test at least two test positions on the first test board receives the functional test signal of the ATE test system test channel through the corresponding pin, and parallels the tested functional modules of each of the FPGA chips under test according to the test signal Carry out functional test, obtain the functional test result of at least two described FPGA chips;

The FPGA chip under test on the second test board receives the test signal of the test channel of the ATE test system through the corresponding pin, performs an electrical performance test according to the test signal, and obtains the electrical performance test result of the FPGA chip.

In a fourth aspect, the present application also provides a computer-readable storage medium. The computer-readable storage medium has a computer program stored thereon, and when the computer program is executed by a processor, the following steps are implemented:

The FPGA chip under test at least two test positions on the first test board receives the functional test signal of the ATE test system test channel through the corresponding pin, and parallels the tested functional modules of each of the FPGA chips under test according to the test signal Carry out functional test, obtain the functional test result of described FPGA chip;

The FPGA chip under test on the second test board receives the test signal of the test channel of the ATE test system through the corresponding pin, performs an electrical performance test according to the test signal, and obtains the electrical performance test result of the FPGA chip.

In a fifth aspect, the present application also provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the following steps are implemented:

The FPGA chip under test that is positioned at at least two test positions of the first test board receives the functional test signal of the ATE test system test channel through the corresponding pin, and the tested functional modules of each described FPGA chip under test are tested according to the functional test signal. Carry out functional test in parallel, obtain the functional test result of at least two described FPGA chips;

The FPGA chip under test on the second test board receives the test signal of the test channel of the ATE test system through the corresponding pin, performs an electrical performance test according to the test signal, and obtains the electrical performance test result of the FPGA chip.

The above-mentioned FPGA multi-chip parallel testing method, device, computer equipment and storage medium receive the functional test signal of the ATE test system test channel by the FPGA chip under test at least two test positions on the first test board through corresponding pins, according to The test signal performs a functional test on the tested functional modules of each tested FPGA chip in parallel, and obtains the functional test results of at least two FPGA chips. The tested FPGA chip located on the second test board receives the test channel of the ATE test system through the corresponding pin According to the test signal, the electrical performance test is performed according to the test signal, and the electrical performance test result of the FPGA chip is obtained. This method decouples the functional test and electrical performance test of the FPGA chip, and solves the contradiction between the multi-pin FPGA chip test requirements and the limited test channels of the ATE machine by performing functional tests in parallel, shortens the test time, and improves the test efficiency of the FPGA chip , to achieve rapid testing of batch chips.

Description of drawings

Fig. 1 is the schematic flow sheet of the parallel testing method of FPGA multi-chip in an embodiment;

Fig. 2 is the schematic diagram of FPGA chip internal function module BIST test principle in an embodiment;

Fig. 3 is the design schematic diagram of the full pin test of single chip in an embodiment;

Fig. 4 is the design schematic diagram that FPGA multi-chip carries out function test in parallel in one embodiment;

Fig. 5 is the structural block diagram of the parallel testing device of FPGA multi-chip in an embodiment;

Figure 6 is an internal block diagram of a computer device in one embodiment.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, not to limit the present application.

The FPGA multi-chip parallel testing method of the present application can be realized by an ATE (Auto test equipment) automated testing system. The ATE automated test system configures the chip and provides functional test signals such as power supply and clock. The FPGA chip under test located at least two test positions on the first test board receives the functional test signal of the ATE test system test channel through the corresponding pins. According to the test The signal is used to perform functional tests on the tested functional modules of each tested FPGA chip in parallel to obtain the functional test results of at least two FPGA chips. The tested FPGA chip located on the second test board receives the test channel through the corresponding ATE test system pin The test signal is used to perform an electrical performance test according to the test signal to obtain an electrical performance test result of the FPGA chip. This method divides the FPGA chip functional performance test items according to the test IO quantity requirements and test time, adopts multi-chip effective pin parallel test design for FPGA functional test, and adopts single-chip full pin test design for FPGA electrical performance parameter full test, forming a A test method that covers the full test requirements of FPGA functional performance and has high test efficiency.

In one embodiment, as shown in Figure 1, a kind of parallel testing method of FPGA multi-chip is provided, and this method is applied to ATE automated test system, comprises the following steps:

Step 102, the FPGA chip under test at least two test positions on the first test board receives the functional test signal of the ATE test system test channel through the corresponding pin, and performs a test on each functional module of the FPGA chip under test according to the test signal Perform functional tests in parallel to obtain functional test results of at least two FPGA chips.

Among them, the field programmable gate array (FPGA) chip has the advantages of high logic density, repeatable configuration, and online programming. After the hardware system is developed and actually used, it can be reprogrammed to change the system design. At the same time, it also has the advantages of short design and development cycle and low cost. At present, FPGA is developing rapidly in the direction of high speed, large capacity, high density, and multi-function. The scale of internal resources has reached tens of millions or even hundreds of millions of gates, and the number of chip pins has increased from a few hundred to more than 1,000 pins.

Chip testing is an important way to ensure the quality of FPGA products. As the integration scale of FPGA chips continues to increase, the number of chip pins is increasing. At the same time, with the increase of domestic FPGA chip market size and application demand, the mass production scale of a single model has reached tens of thousands to hundreds of thousands of pieces, and the demand for chip mass production testing has surged, which puts forward the demand for efficient and fast testing of FPGA. The FPGA chip testing method of the ATE automated test system has become the mainstream technology for batch FPGA chip testing due to its high test efficiency and fast test speed.

Functional performance test is the key test content of FPGA chip test, which has the characteristics of large test vector scale, long test time but few required ATE test channels. According to the characteristics that all resources of the FPGA chip can be independently configured and reprogrammed, the built-in self-test method is adopted to use the internal programmable logic resources of the chip to build a test control structure for test vector generation, application, and output analysis, using relatively few clocks, Effective pins such as vector and output can realize the functional performance test of the FPGA chip hard core function module and the basic circuit function module. That is, the functional performance test of the FPGA chip requires fewer test channels, the first test board can have at least two test positions, and at least two FPGA chips can perform the functional performance test at the same time. Among them, functional performance testing mainly includes functional performance testing of APM, GTX, BRAM, PLL, DCM, SCAN, CLB, IOB, configuration modules and other hard-core functional circuit modules and basic circuit modules.

Wherein, the ATE test system has two test boards, which are the first test board of the ATE test system and the second test board of the ATE test system. The first test board of the ATE test system performs functional tests on the FPGA chip. Specifically, the ATE automated test system provides a functional test signal through the test channel, and the FPGA chip under test receives the test signal through the corresponding pin, and the test signal acts on the functional module under test for functional testing, and obtains the functional test result of the FPGA chip. Since the functional test has the characteristics of a long test time and a small number of ATE test channels, there may be at least two test positions on the first test board, and the tested FPGA chips placed in at least two test positions perform functional tests in parallel.

Step 104, the FPGA chip under test on the second test board receives the test signal of the test channel of the ATE test system through the corresponding pin, conducts the electrical performance test according to the test signal, and obtains the electrical performance test result of the FPGA chip.

Wherein, the ATE test system has two test boards, which are the first test board of the ATE test system and the second test board of the ATE test system. The first test board of the ATE test system performs a functional test on the FPGA chip, and the second test board of the ATE test system performs an electrical performance test on the FPGA chip. The test of the electrical performance parameter test has the characteristics of short time and a large number of ATE test channels.

Specifically, the ATE automated test system provides a test signal through the test channel, and the FPGA chip under test receives the test signal through the corresponding pin, performs an electrical performance test according to the test signal, and obtains the electrical performance test result of the FPGA chip.

The above-mentioned FPGA multi-chip parallel testing method, receives the functional test signal of the ATE test system test channel by the FPGA chip under test at least two test positions on the first test board through the corresponding pins, and tests each FPGA chip under test according to the test signal The tested functional modules are tested in parallel to obtain the functional test results of at least two FPGA chips. The tested FPGA chip located on the second test board receives the test signal of the ATE test system test channel through the corresponding pin, and performs the test according to the test signal. Electrical performance test, to obtain the electrical performance test results of the FPGA chip. This method decouples the functional test and electrical performance test of the FPGA chip, and solves the contradiction between the multi-pin FPGA chip test requirements and the limited test channels of the ATE machine by performing functional tests in parallel, shortens the test time, and improves the test efficiency of the FPGA chip , to achieve rapid testing of batch chips.

In another embodiment, the FPGA chip under test on the first test board receives the functional test signal of the test channel of the ATE test system through the corresponding pin, and performs a parallel functional performance test on the tested functional module according to the test signal to obtain the FPGA chip. Functional test results, including: the FPGA chip under test on the first test board receives the clock signal of the ATE test system test channel through the corresponding pin; according to the clock signal, the FPGA chip built-in self-test vector generation module generates test vectors; The vector acts on the tested functional module of the FPGA chip to obtain the actual output; compare the expected output and the actual output of the test vector to obtain the test result of the tested functional module of the FPGA chip; according to the test results of each tested functional module, the FPGA chip is obtained The functional test results.

The process of testing the FPGA chip by the ATE automated test system is as follows: use the vector conversion tool to convert the FPGA chip configuration program into a test vector that can be recognized by the ATE machine, and then load the test vector to the FPGA under test through the ATE machine, and the ATE machine simultaneously Provide the signals such as power supply and clock required for the operation of the FPGA chip under test, so that the FPGA chip is in a specific working state, and then judge whether the test item is qualified according to the output of the FPGA chip.

Among them, the functional BIST test design is carried out through the FPGA test development tool, and the configuration code stream is generated after compilation and synthesis, such as the .bit format file generated by the Xilinx FPGA development tool Vivado. Use EDA tools and ATE conversion tools to convert the chip configuration code stream into a pattern test vector file that can be recognized by the ATE test machine, such as the binl file of the Advantest 93000 test machine. It is also possible to use the test program development tool that comes with the ATE test system for test program development according to the FPGA chip function and electrical performance parameter test requirements.

Large-scale high-performance FPGA chip is mainly composed of programmable logic unit (CLB), programmable input and output unit (IOB), programmable interconnect resources (IR), typical functional hard core modules, such as block random access memory (BRAM), Clock manager (DCM), arithmetic processing module (APM), high-speed serial module (GTX), boundary scan module (SCAN), configuration module, etc. Among them, the built-in self-test design divides logic resources into three modules: test pattern generation module (TPG), output response verification circuit module (ORA) and function module under test (DUT). The BIST test principle of the internal functional module of the FPGA chip is shown in Figure 2. The built-in self-test (BIST) design technology adds some additional self-test circuits to the design of the chip, and only needs to apply the necessary control signals from the outside to check the circuit under test by running the built-in self-test hardware and software. defects or malfunctions. The TPG module is written according to the functions of different DUT modules. Under the excitation of the clock signal given by the ATE automated test system, the TPG module generates test vectors such as the excitation, control and all input combinations of the tested module, and the DUT module receives the test vectors. After that, the actual response data is generated. Under the test vector input condition, the TPG module produces the expected data produced by the module under test. The ORA module receives the actual response data and the expected data, compares the actual response data with the expected data, judges whether the function of the DUT module is correct, and outputs the judgment result pass/fail.

In this embodiment, on the basis of the decoupling function test and the electrical performance test, a functional performance test is performed on the FPGA chip to judge the quality of the FPGA chip.

In one embodiment, the second test board includes a test position; the number of test channels required for electrical performance testing is greater than the number of test channels required for functional testing, and is close to the number of test channels of the ATE test system.

Among them, the electrical performance parameter test items mainly include short circuit/open circuit, input high/low level voltage, output high/low level voltage, output high/low level current, pin pull-up/pull-down current, leakage current, etc.

Electrical performance parameters, especially input and output electrical parameters, need to test all IO pins of the FPGA chip. Therefore, for an FPGA chip with a large number of pins, the electrical performance parameter test requires a large number of ATE test channels. Therefore, a single The chip is tested in a full-pin manner. In addition, compared with the functional performance test of FPGA chips with complex tests and large test vector specifications, the test time of electrical performance parameters of FPGA chips is shorter, and the proportion of the total test time of FPGA chips is relatively low.

Figure 3 shows the design of the single-chip full-pin test. As shown in Figure 3, there is only one FPGA chip test Socket on the FPGA chip single-chip full-pin ATE test board, and each test Socket is a test bit. The pin Pin is connected to the corresponding test channel of the ATE machine, and the full coverage test of the electrical performance parameters of the FPGA chip is performed.

In this embodiment, the electrical performance test and the functional test are separated through the second test board of the ATE test system, so as to provide conditions for performing functional tests in parallel.

In another embodiment, the method also includes: obtaining the test results of the tested functional modules of the FPGA chip under test in different test positions of the first test board; If the test result is qualified, it is verified that the test of the tested functional module of the FPGA chip is passed.

Specifically, there are at least two FPGA chip test Sockets on the first test board of the ATE test system, each test Socket is a test position, and the same FPGA chip is respectively placed on different test positions on the first test board of the ATE test system Functional test, if the test results of different test bits are the same, the consistency verification is passed. The passing of the consistency verification indicates that the different test bits on the first test board of the ATE test system are the same and there is no difference.

In this embodiment, check whether the different test bits on the first test board of the ATE test system are different through consistency verification, and the results of different test bits on the first test board of the ATE test system are the same, that is, the consistency verification is passed , to ensure the consistency and accuracy of chip detection results.

In another embodiment, the test channel is pre-configured according to pin definitions, and the configuration includes at least one of power configuration, IO (input, output) configuration, voltage/current configuration and timing configuration.

The power supply configuration includes: positive and negative polarity of the power supply, load capacitance, power board, test bit, corresponding power channel, etc. IO configuration includes: IO channel type (input, output), test mode, impedance, test board, test bit, corresponding test channel, etc. Voltage/current configuration includes: chip pin name, type, input voltage lower limit, input voltage upper limit, output voltage lower limit, output voltage upper limit, voltage/current configuration is to determine the driving voltage applied to FPGA chip pins through ATE testing machine /current, output voltage/current. The timing configuration includes: timing parameter name, parameter model, timing waveform, frequency, etc. The timing configuration is to determine the timing waveform parameters of the signal applied to the pins of the FPGA chip through the ATE test machine.

After defining the pins of the FPGA chip, use the programming tool of the ATE test machine to configure the test channel for the FPGA chip.

In this embodiment, after the test channel is configured on the FPGA chip, the test channel is connected to the pins of the chip through software, so as to perform subsequent functional tests and electrical performance tests.

In one embodiment, the first test board includes four test positions; four FPGA chips to be tested are simultaneously placed on the test positions to perform functional tests in parallel.

Compared with conventional integrated circuits, the ATE test of FPGA needs to focus on testing and verifying the functions of the basic circuit modules and hard-core circuit modules inside the FPGA chip on the basis of realizing the electrical performance parameter test. The FPGA chip functional performance test generally adopts the built-in self-test BIST method, which requires less external IO. At the same time, IO multiplexing can be used to further reduce the required IO, so the number of ATE test channels required is small. Since there are many functional performance test items for FPGA chips, different test items have different requirements for test resources such as ATE test channels, test vector scale, and test time. The general principle of adjusting the division of test items is the general principle that there are fewer electrical performance parameter test items and more IO requirements.

Take a 10-million-gate multi-pin FPGA chip as an example. The number of pins of this chip is 900. The selected ATE machine has 128 power channels and 1024 digital channels. Usually, only one FPGA chip can be tested at the same time. . Through the analysis of the test channel requirements for the effective pins of the FPGA chip functional performance test, the ATE test channels required for the functional performance test of a single FPGA chip are: 216 digital channels and 17 power channels. The 216 digital channels correspond to 46 FPGA configuration pins, 128 FPGA functional performance test vector pins and 42 FPGA chip clock signal pins. The FPGA configuration pins are connected to the ATE test digital channel to configure the FPGA chip for BIST function. The FPGA functional performance test vector pin is connected to the ATE test digital channel to provide vector input for the functional performance test. The FPGA chip clock signal pin is connected to the ATE test digital channel to provide a clock signal for functional performance testing and debugging. The power supply pins of the FPGA chip include more than 200 power supply related pins such as the core power supply VCCINT, the auxiliary circuit power supply VCCAUX, the block memory VCCBRAM power supply, the reference voltage VREF, and GND. pin can be connected to 1 ATE power supply channel, so the FPGA power supply uses 17 ATE power supply channels. Therefore, an ATE machine with 128 power channels and 1024 digital channels can satisfy the functional performance test of four FPGA chips in parallel.

As shown in Figure 4, according to the FPGA chip pins occupied by the FPGA chip function BIST test vector design, under the constraints of the selected FPGA chip ATE machine test channel resources, the ATE test channel resources are allocated to multiple FPGA chip function tests The pins that need to be used, including power supply, clock, vector, configuration, output, etc., realize the connection between the effective pins of multiple FPGA chips and the ATE test channel. There are 4 FPGA chip test sockets on the first ATE test board, and each test socket It is a test bit, which connects effective pins such as power supply, clock, vector, and configuration necessary for functional performance testing to the test channel of the ATE machine to realize parallel testing of multiple chips. The test efficiency PTE can be calculated by the following formula:

In the formula, MST ₁ is the parallel test time of the multi-chip function test item, NS is the number of chips tested in parallel, SST ₁ is the test time of the single-chip electrical performance parameter test item, and SST ₂ is the conventional single chip to complete the function and electrical performance The total time for parameter test item testing.

Taking an FPGA chip with tens of millions of gates and thousands of pins as an example, its functional test items include: APM, CRAM, DRAM, PLL, MBE storage unit fault test, GTX, configuration module and other FPGA internal functional module tests. Electrical performance parameter test items include: short circuit/open circuit, output high/low level (covering CMOS 3.3V/2.5V/1.8V/1.5V/1.2V), pin pull-up current, pin pull-down current, input leakage current , Static current, etc. The built-in self-test design of each module inside the FPGA chip covers the above functional test items. Using the Advantest 93000ATE test machine, the functional performance test of the four chips of the functional test item and the single-chip serial test of the electrical performance parameter test item are realized. Through the functional test verification of the same FPGA chip at the four test positions, the functional test results are the same, which verifies the consistency of the multi-chip parallel test. Table 1 shows the test time required for functional test items and electrical performance parameter test items.

Table 1 Functional test time

Using 4 chips in parallel for functional testing and single-chip full-pin electrical performance parameter testing, the test time for 4 FPGA chips is 56.794s, which significantly shortens the test time, and the test efficiency is 3.31, that is, compared with the ATE test machine, only It can perform single-chip testing, and the testing efficiency is increased by more than 3 times. On this basis, further optimizing the multi-chip effective pin function test design and increasing the number of chips tested at the same time will further improve the test efficiency.

In this embodiment, the built-in self-test BIST method that the chip function test adopts is carried out, only need less ATE test channels, therefore, the test of at least two chips can be carried out in parallel on the first test board of the ATE test system, thereby Improve the test efficiency of FPGA chips, shorten the test time, and realize the rapid test of batch chips.

It should be understood that although the steps in the flow charts involved in the above embodiments are displayed in sequence according to the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts involved in the above embodiments may include multiple steps or stages, and these steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of the steps or stages does not have to be performed sequentially, but may be performed alternately or alternately with other steps or at least a part of steps or stages in other steps.

Based on the same inventive concept, the present application also provides a parallel testing device for realizing the FPGA multi-chip involved above. The implementation scheme provided by the device to solve the problem is similar to the implementation scheme described in the above-mentioned method, so the specific limitations in the parallel test device embodiment of one or more FPGA multichips provided below can refer to the above for FPGA multichip The limitation of the chip parallel testing method will not be repeated here.

In one embodiment, as shown in Figure 5, a kind of FPGA multi-chip parallel testing device 500 is provided, comprising: functional performance testing module 502 and electrical performance testing module 504, wherein:

Functional test module 502, the FPGA chip under test that is positioned at at least two test positions of the first test board is used for receiving the functional test signal of ATE test system test channel by corresponding pin, according to test signal to each described FPGA chip under test The functional modules under test are tested in parallel to obtain the functional performance test results of at least two FPGA chips;

Electrical performance testing module 504, the FPGA chip under test located on the second test board of the ATE testing system is used to receive the test signal of the test channel through the corresponding pin, perform electrical performance test according to the test signal, and obtain the electrical performance test result of the FPGA chip.

In another embodiment, the function test module, the FPGA chip under test located on the first test board is used to receive the function test signal of the test channel of the ATE test system through the corresponding pin, and perform the function test on the function module under test according to the test signal , to obtain the functional test results of the FPGA chip, including: the FPGA chip under test located on the first test board receives the clock signal of the test channel of the ATE test system through the corresponding pin; according to the clock signal, the FPGA chip built-in self-test vector generation module generates Test vector; apply the test vector to the tested functional module of the FPGA chip to obtain the actual output; compare the expected output and actual output of the test vector to obtain the test result of the tested functional module of the FPGA chip; according to the test of each tested functional module As a result, the functional test results of the FPGA chip are obtained.

In another embodiment, the second test board includes a test position; the number of test channels required for electrical performance testing is greater than the number of test channels required for functional performance testing, and is close to the number of test channels of the ATE test system.

In another embodiment, a parallel testing device of FPGA multi-chip also includes: a consistency verification module;

The consistency verification module is used to obtain the test results of the tested functional modules of the FPGA chip under test in different test positions of the first test board; if the test results of the tested functional modules of the tested FPGA chip in different test positions are qualified, then Verify that the test of the tested functional module of the FPGA chip passes.

In another embodiment, the test channel is pre-configured according to the pin definition, and the configuration includes power configuration, IO configuration, voltage/current configuration and timing configuration.

In another embodiment, the first test board includes four test positions; four tested FPGA chips are placed on the test positions at the same time for functional testing in parallel.

Each module in the above-mentioned FPGA multi-chip parallel testing device can be fully or partially realized by software, hardware and combinations thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, and can also be stored in the memory of the computer device in the form of software, so that the processor can invoke and execute the corresponding operations of the above-mentioned modules.

In one embodiment, a computer device is provided. The computer device may be a controller, and its internal structure may be as shown in FIG. 6 . The computer device includes a processor, a memory, a communication interface and a display screen connected by a system bus. Wherein, the processor of the computer device is used to provide calculation and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be realized through WIFI, mobile cellular network, NFC (Near Field Communication) or other technologies. When the computer program is executed by the processor, a method for parallel testing of FPGA multi-chips is realized. The display screen of the computer device may be a liquid crystal display screen or an electronic ink display screen.

Those skilled in the art can understand that the structure shown in FIG. 6 is only a block diagram of a part of the structure related to the solution of this application, and does not constitute a limitation on the computer equipment to which the solution of this application is applied. The specific computer equipment can be More or fewer components than shown in the figures may be included, or some components may be combined, or have a different arrangement of components.

In one embodiment, a computer device is provided, including a memory and a processor, a computer program is stored in the memory, and the processor implements the following steps when executing the computer program:

The FPGA chip under test of at least two test positions on the first test board receives the functional test signal of the ATE test system test channel through the corresponding pin, and performs functions in parallel according to the test signal to the tested functional modules of each described FPGA chip under test. Test, obtain the functional test results of at least two FPGA chips;

The tested FPGA chip located on the second test board receives the test signal of the test channel of the ATE test system through the corresponding pin, conducts the electrical performance test according to the test signal, and obtains the electrical performance test result of the FPGA chip.

In one of the embodiments, the FPGA chip under test on the first test board receives the clock signal of the test channel of the ATE test system through the corresponding pins, and performs a functional test on the functional module under test according to the clock signal to obtain the functional test of the FPGA chip. Results, including:

The measured FPGA chip located on the first test board receives the clock signal of the ATE test system test channel through the corresponding pin;

According to the clock signal, the FPGA chip built-in self-test vector generation module generates test vectors;

Apply the test vector to the tested functional module of the FPGA chip to obtain the actual output;

Compare the expected output and actual output of the test vector to obtain the test result of the tested functional module of the FPGA chip;

According to the test results of each tested functional module, the functional test results of the FPGA chip are obtained.

In one of the embodiments, the second test board includes a test position; the number of test channels required for electrical performance testing is greater than the number of test channels required for functional performance testing, and is close to the number of test channels of the ATE test system.

In one embodiment, the method also includes:

Obtain the test results of the tested functional modules of the tested FPGA chip in different test positions of the first test board;

If the test results of the tested functional modules of the tested FPGA chip at different test positions are qualified, it is verified that the test of the tested functional modules of the FPGA chip passes.

In one embodiment, the test channel is pre-configured according to the pin definition, and the configuration includes power configuration, IO configuration, voltage/current configuration and timing configuration.

In one embodiment, the first test board includes four test positions; four FPGA chips to be tested are simultaneously placed on the test positions for functional testing in parallel.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

The FPGA chips under test at least two test positions on the first test board receive the functional test signals of the ATE test system test channel through corresponding pins, and perform functions in parallel on the tested functional modules of each of the FPGA chips under test according to the test signals. Test, obtain the functional test results of at least two FPGA chips;

The tested FPGA chip located on the second test board receives the test signal of the test channel of the ATE test system through the corresponding pin, conducts the electrical performance test according to the test signal, and obtains the electrical performance test result of the FPGA chip.

In one of the embodiments, the FPGA chip under test at least two test positions on the first test board receives the functional test signal of the ATE test system test channel through the corresponding pin, and the FPGA chip under test is tested according to the test signal. The functional modules under test are tested in parallel to obtain the functional test results of at least two FPGA chips, including:

The measured FPGA chip located on the first test board receives the clock signal of the ATE test system test channel through the corresponding pin;

According to the clock signal, the FPGA chip built-in self-test vector generation module generates test vectors;

Apply the test vector to the tested functional module of the FPGA chip to obtain the actual output;

Compare the expected output and actual output of the test vector to obtain the test result of the tested functional module of the FPGA chip;

According to the test results of each tested functional module, the functional performance test results of the FPGA chip are obtained.

In one embodiment, the second test board includes a test position; the number of test channels required for electrical performance testing is greater than the number of test channels required for functional performance testing.

In one embodiment, the method also includes:

Obtain the test results of the tested functional modules of the tested FPGA chip in different test positions of the first test board;

If the test results of the tested functional modules of the tested FPGA chip at different test positions are qualified, it is verified that the test of the tested functional modules of the FPGA chip passes.

In one embodiment, the test channel is pre-configured according to the pin definition, and the configuration includes power configuration, IO configuration, voltage/current configuration and timing configuration.

In one embodiment, the first test board includes four test positions; four FPGA chips to be tested are simultaneously placed on the test positions for functional testing in parallel.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed through computer programs to instruct related hardware, and the computer programs can be stored in a non-volatile computer-readable storage medium In this case, when the computer program is executed, it may include the processes of the embodiments of the above-mentioned methods. Wherein, any reference to storage, database or other media used in the various embodiments provided in the present application may include at least one of non-volatile and volatile storage. Non-volatile memory can include read-only memory (Read-Only Memory, ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive variable memory (ReRAM), magnetic variable memory (Magnetoresistive Random Access Memory, MRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (Phase Change Memory, PCM), graphene memory, etc. The volatile memory may include random access memory (Random Access Memory, RAM) or external cache memory. As an illustration and not a limitation, the RAM can be in various forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM). The databases involved in the various embodiments provided in this application may include at least one of a relational database and a non-relational database. The non-relational database may include a blockchain-based distributed database, etc., but is not limited thereto. The processors involved in the various embodiments provided by this application can be general-purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, data processing logic devices based on quantum computing, etc., and are not limited to this.

The technical features of the above embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be It is considered to be within the range described in this specification.

The above examples only express several implementation modes of the present application, and the description thereof is relatively specific and detailed, but should not be construed as limiting the patent scope of the present application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be determined by the appended claims.

Claims (10)

1. A parallel testing method of FPGA multiple chips comprises the following steps:

the method comprises the steps that functional test signals of test channels of an ATE test system are received by FPGA chips to be tested which are located in at least two test positions of a first test board through corresponding pins, and functional tests are conducted on tested functional modules of the FPGA chips to be tested in parallel according to the test signals to obtain functional test results of the FPGA chips to be tested;

and the tested FPGA chip positioned on the second test board receives the test signal of the test channel of the ATE test system through the corresponding pin, and performs electrical performance test according to the test signal to obtain an electrical performance test result of the FPGA chip.

2. The method of claim 1, wherein the receiving of the test signal of the test channel of the ATE test system by the FPGA chip under test on the first test board through the corresponding pin and the functional testing of the functional module under test according to the test signal to obtain the functional test result of the FPGA chip, comprises:

the FPGA chip to be tested positioned on the first test board receives a clock signal of a test channel of the ATE test system through a corresponding pin;

according to the clock signal, a built-in self-test vector generation module of the FPGA chip generates a test vector;

the test vector is acted on a tested function module of the FPGA chip to obtain actual output;

comparing the expected output and the actual output of the test vector to obtain a test result of the tested functional module of the FPGA chip;

and obtaining a function test result of the FPGA chip according to the test result of each tested function module.

3. The method of claim 1, wherein said second test board includes a test bit; the number of test channels required for the electrical performance detection is larger than that required for the functional test and is close to that of an ATE test system.

4. The method of claim 2, further comprising:

obtaining the test results of the tested functional modules of the tested FPGA chip at different test positions of the first test board;

and if the test results of the tested function modules of the tested FPGA chip at different test positions are qualified, verifying that the tested function modules of the FPGA chip pass the test.

5. The method of any of claims 1 to 5, wherein the test channels are pre-configured according to a pin definition, the configuration comprising a power supply configuration, an IO configuration, a voltage/current configuration, and a timing configuration.

6. The method of claim 1, wherein the first test board comprises four test bits; and the four FPGA chips to be tested are simultaneously placed on the test positions to carry out the function test in parallel.

7. An apparatus for parallel testing of multiple chips of an FPGA, the apparatus comprising:

the functional test module is used for receiving a clock signal of a test channel of the ATE test system through corresponding pins of the tested FPGA chips positioned in at least two test positions of the first test board, and performing functional test on the tested functional modules of the tested FPGA chips in parallel according to the test signal to obtain functional performance test results of at least two FPGA chips;

and the electrical performance testing module is positioned on the second testing board and used for receiving the testing signal of the testing channel of the ATE testing system through the corresponding pin and carrying out electrical performance testing according to the testing signal to obtain the electrical performance testing result of the FPGA chip.

8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 6.

9. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 6.

10. A computer program product comprising a computer program, characterized in that the computer program realizes the steps of the method of any one of claims 1 to 6 when executed by a processor.

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