CN118820146B - RAID engine and RAID bridge chip - Google Patents
RAID engine and RAID bridge chip Download PDFInfo
- Publication number
- CN118820146B CN118820146B CN202411299457.7A CN202411299457A CN118820146B CN 118820146 B CN118820146 B CN 118820146B CN 202411299457 A CN202411299457 A CN 202411299457A CN 118820146 B CN118820146 B CN 118820146B
- Authority
- CN
- China
- Prior art keywords
- raid
- data
- chip
- engine
- interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/781—On-chip cache; Off-chip memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention discloses a RAID engine and a RAID bridging chip. In order to reduce the design and integration difficulty of the off-chip memory to the bridge chip, the RAID engine comprises an on-chip memory, wherein data is transmitted between the RAID processor and the on-chip memory through a first data interface, and data is transmitted between the SATA core and the on-chip memory through a second data interface. The invention solves the technical problem of high design and integration difficulty of the bridge chip, reduces the chip design and integration difficulty in the bridge chip and avoids the cost of the off-chip memory. The invention is suitable for the field of integrated circuits.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a RAID engine and a RAID bridging chip.
Background
The read-write and storage of a single disk has the risks or defects of limited capacity, low input/output performance and data loss. The redundant array of independent disks (Redundant Array of INDEPENDENT DISKS, RAID) is a storage technology that is designed to overcome the above drawbacks.
The basic idea of a RAID disk array is to form a large disk system with multiple independent disks together, thereby achieving better storage performance and higher reliability than a single disk, but for a computer, the RAID disk array resembles a single hard disk or logical storage unit. The user may decide in what way the device processes the data by configuring the RAID mode of the device.
Typical RAID modes are mainly RAID-0, RAID-1, RAID-5 and RAID-10.RAID-0 mainly realizes striped storage of data and improves the performance of a disk array. RAID-1 mainly realizes mirror image storage and realizes data backup of the disk. RAID-5 realizes data recovery of the disk and enhances the data recovery capacity of the disk. RAID-10 has both RAID-0 and RAID-1 characteristics.
According to the different modes selected, RAID disk arrays may enhance data transfer performance, enhance data recovery, and increase data backup capabilities as compared to monolithic disks.
RAID implementations may be divided into two implementations, soft and hard. Soft RAID in soft implementation refers to the use of a central processing unit (Central Processing Unit, CPU) of a host to perform data computation and processing of the RAID, and hard RAID refers to the use of a specialized processor, i.e., a RAID processor, and a cache to process the RAID data. It is apparent that soft RAID relies heavily on the computational power of the CPU of the host and the data computing and processing algorithms of the RAID.
When the number of disks mounted downstream of the host device is large, more CPU resources and power consumption are required. In contrast, hard RAID does not consume CPU resources, and is more flexible for tasks such as disk monitoring, capacity expansion, backup, replacement and the like.
The RAID bridge chip can realize data transmission between the host device and the disk, and the RAID engine is the core of the RAID bridge chip. In addition to the special processor, the RAID engine in the prior art also needs to implement data buffering and handling by using an off-chip double rate synchronous dynamic random access memory (Dual Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM). In order for a RAID processor and DDR SDRAM to achieve more efficient interaction, the RAID processor designer has to consider adding additional control logic and interfaces, which complicates the data flow interaction, integration, and design development work of the RAID processor.
How to reduce the chip design and integration difficulty in the bridge chip and avoid the cost of the off-chip memory becomes a technical problem to be solved in the field.
Disclosure of Invention
In order to alleviate or partially alleviate the above technical problem, the solution of the present invention is as follows:
A RAID engine comprises an on-chip memory, wherein data is transmitted between a RAID processor and the on-chip memory through a first data interface, and data is transmitted between a SATA core and the on-chip memory through a second data interface.
Further, the RAID engine is a circuit module in a RAID bridge chip.
Further, a DMA module in the SATA core is configured to transfer data from within a physical storage device to within the on-chip memory, or/and transfer data from within an on-chip memory to within a physical storage device.
Further, the RAID engine also includes a control register module for receiving control signals from the RAID processor.
Further, the control signal includes information indicating a RAID mode and a number of physical storage devices.
Further, the first data interface and the second data interface are AMBA data interfaces.
Further, the RAID engine further comprises a RAID state machine, and the RAID state machine is used for jumping to a corresponding RAID data processing mode according to the RAID mode and the information of the number of the physical storage devices, which are acquired from the control register module.
Further, the RAID processor transmits a control signal to the control register module through a first control interface, the RAID engine further comprises a data processing module, the data processing module processes the control signal to obtain a processed control signal, and the data processing module transmits the processed control signal to the SATA core through a second control interface.
Further, the first control interface and the second control interface are both AMBA control interfaces, and the RAID state machine is further configured to, when determining a corresponding RAID data processing mode, further according to information indicated by the data processing module.
A RAID bridge chip comprising a RAID processor, a SATA core, and a RAID engine as claimed in any preceding claim.
The technical scheme of the invention has one or more of the following beneficial technical effects:
(1) The internal self-on-chip storage DRAM of the RAID engine can realize data caching and transmission, and the cost of the off-chip memory is eliminated.
(2) Because no extra DDR SDRAM is required to be added outside the chip, corresponding relevant control logic and interfaces are not required to exist, the integration and design difficulty of the chip are reduced, and the chip area and the number of chip interfaces are reduced.
(3) A RAID engine supporting multiple modes can realize data storage of multiple RAID modes.
Furthermore, other advantageous effects that the present invention has will be mentioned in the specific embodiments.
Drawings
FIG. 1 is a schematic diagram of the operation of a RAID bridge chip incorporating the RAID engine of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order to clearly describe the technical solution of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.
The invention discloses a RAID engine supporting multiple modes, which can realize the storage of multiple RAID mode data, and a self-driven random access memory (Dynamic Random Access Memory, DRAM) in the RAID engine is used for realizing data caching and transmission, and does not need extra off-chip DDR SDRAM, thereby simplifying chip design and integration steps. Specifically, the RAID engine is realized through the following technical scheme.
FIG. 1 illustrates a schematic diagram of the operation of a RAID bridge chip incorporating the RAID engine of the present invention. A RAID processor is a special purpose processor for implementing RAID functions. The RAID bridge chip comprises a RAID processor, a RAID engine and a SATA core.
Typically, in a RAID bridge chip, a RAID engine is directly connected between a RAID processor and a serial advanced technology attachment (SERIAL ADVANCED Technology Attachment, SATA) core of a physical storage device through a first-in-first-Out (FIRST IN FIRST Out, FIFO) interface or an advanced microcontroller bus architecture (Advanced Microcontroller Bus Architecture, AMBA) interface, so as to achieve the technical purpose of the present invention.
Unlike software that can program data processing, the RAID engine of the present invention is a hardware implemented circuit module for implementing data processing between the RAID processor and the SATA core. Obviously, the RAID engine of the present invention may be multiplexed as an intellectual property core in the integrated circuit arts.
The RAID engine comprises an on-chip memory, and further comprises a first data interface, a second data interface, a first control interface and a second control interface.
Data is transferred between the RAID processor and the on-chip memory through a first data interface, and data is transferred between the SATA core and the on-chip memory through a second data interface.
Preferably, the RAID engine further comprises at least a first AMBA control interface, a second AMBA control interface, a first AMBA data interface, and a second AMBA data interface. The first AMBA data interface and the second AMBA data interface are used for realizing data access or/and transmission between the RAID processor and the physical storage device, which includes reading data from the physical storage device to the RAID processor and the host device, and writing data from the host device or/and the RAID processor to the physical storage device.
That is, in the above-described embodiment, the first data interface is a first AMBA data interface and the second data interface is a second AMBA data interface, in other words, in this embodiment, both the first data interface and the second data interface are AMBA data interfaces. The first control interface is a first AMBA control interface and the second control interface is a second AMBA control interface, in other words, in this particular embodiment, both the first control interface and the second control interface are AMBA control interfaces.
Preferably, the physical storage device is a magnetic disk. Taking n disks as an example, disk 1, disk 2, disk n are mounted under a host device, which are connected to the SATA core through SATA interface 1, SATA interface 2, SATA interface n, respectively, where n is a positive integer, such as n is 4.
The RAID engine includes on-chip memory, which may be memory located within the RAID engine. The on-chip memory is illustratively a dynamic random access memory (Dynamic Random Access Memory, DRAM) or a static random access memory (Static Random Access Memory, SRAM).
Based on the RAID bridge chip comprising the on-chip memory, the outside of the RAID bridge chip is not required to be additionally provided with an off-chip DDR SDRAM, so that on one hand, the cost can be reduced, and on the other hand, the design and the integration complexity of the RAID bridge chip can be reduced.
Also included in the SATA core is a direct memory access (Direct Memory Access, DMA) module. The DMA module is used for transferring data from the physical storage device to the on-chip memory or/and transferring data from the on-chip memory to the physical storage device.
In addition, the RAID engine also comprises a control register module, a RAID state machine and a data processing module.
For the write process, the RAID engine workflow is such that, for example, a user configures the RAID mode and the number of disks or designates a number of disks as desired.
The RAID processor transmits a control signal to the control register module through a first control interface. Specifically, the RAID processor transmits control signals to a control register module in the RAID engine through a first AMBA control interface.
The RAID processor stores the data to be written into the on-chip memory through the first AMBA data interface. The control signals include information indicating a RAID mode and a number of physical storage devices.
Illustratively, the control register module implements configuration of disk count and RAID mode based on the control signals. Optionally, the user may also change the number of disks and RAID mode as desired.
And the RAID state machine is combined with the information indicated by the data processing module, and jumps to the corresponding RAID data processing mode according to the RAID mode and the number of disks configured by the user. By way of example, the RAID data processing mode may be one of RAID-0, RAID-1, RAID-5, and RAID-10.
The data processing module processes the control signal to obtain a processed control signal. The data processing module transmits the processed control signal to the SATA core through a second control interface. Specifically, the processed control signal is transmitted to the SATA core through the second AMBA control interface. And the DMA module in the SATA core transmits the data to be written in the on-chip memory to the disk through the second AMBA data interface according to the processed control signal.
For example, if the user selects RAID-0 mode, the data to be written in the on-chip memory is striped among the corresponding plurality of disks.
Similarly, for the read process, the RAID engine workflow is such that the user decides on the RAID mode and the number of disks enabled as needed. The RAID processor transmits control signals to a control register module in the RAID engine through a first AMBA control interface.
The control register module realizes the configuration of the number of disks and RAID modes according to the control signals. And the RAID state machine is combined with the data processing module, and jumps to the corresponding RAID data processing mode according to the RAID mode and the number of disks configured by the user. By way of example, the RAID data processing mode may be one of RAID-0, RAID-1, RAID-5, and RAID-10.
The data processing module processes the control signal to obtain a processed control signal. The processed control signal is transmitted to the SATA core through a second AMBA control interface.
According to a RAID mode configured by a user, a DMA module in the SATA core transfers data to be transferred from the disk to the on-chip memory into the on-chip memory. After the data transmission is finished, the RAID processor receives a notice of reading the data from the on-chip memory, and then the data is read back to the RAID processor. Further, the RAID processor communicates the data back to the host device.
In conclusion, the invention realizes the data reading and writing of multiple RAID modes through the RAID engine. Compared with the prior art, the invention can avoid adding extra DDR SDRAM outside the RAID bridging chip, reduce the chip area, cost and the number of chip interfaces, and reduce the chip design and integration complexity.
Numerous specific details are set forth in the above description in order to provide a better illustration of the invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (5)
1. A RAID engine, characterized by:
the RAID engine includes on-chip memory;
transmitting data between the RAID processor and the on-chip memory through a first data interface;
Transmitting data between the SATA core and the on-chip memory through a second data interface;
the RAID engine is a circuit module in the RAID bridge chip;
A DMA module in the SATA core to transfer data from within a physical storage device to within the on-chip memory, or/and from within an on-chip memory to within a physical storage device;
the RAID engine further comprises a control register module for receiving control signals from a RAID processor;
the RAID engine further comprises a RAID state machine, wherein the RAID state machine is used for jumping to a corresponding RAID data processing mode according to the RAID mode and the information of the number of physical storage devices, which are acquired from the control register module;
The RAID processor transmits a control signal to the control register module through a first control interface;
The RAID engine further comprises a data processing module, wherein the data processing module processes the control signals to obtain processed control signals;
The data processing module transmits the processed control signal to the SATA core through a second control interface.
2. The RAID engine of claim 1, wherein:
the control signals include information indicating a RAID mode and a number of physical storage devices.
3. The RAID engine of claim 2, wherein:
the first data interface and the second data interface are both AMBA data interfaces.
4. A RAID engine according to claim 3 wherein:
the first control interface and the second control interface are AMBA control interfaces;
And when the RAID state machine determines the corresponding RAID data processing mode, the RAID state machine is also according to the information indicated by the data processing module.
5. A RAID bridge chip, characterized by:
The bridge chip comprising a RAID processor, a SATA core, and the RAID engine of any of claims 1-4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411299457.7A CN118820146B (en) | 2024-09-18 | 2024-09-18 | RAID engine and RAID bridge chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411299457.7A CN118820146B (en) | 2024-09-18 | 2024-09-18 | RAID engine and RAID bridge chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118820146A CN118820146A (en) | 2024-10-22 |
| CN118820146B true CN118820146B (en) | 2024-12-17 |
Family
ID=93079015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411299457.7A Active CN118820146B (en) | 2024-09-18 | 2024-09-18 | RAID engine and RAID bridge chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118820146B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103942007A (en) * | 2013-01-18 | 2014-07-23 | 索尼公司 | RAID controller and command processing method thereof |
| CN118567904A (en) * | 2024-06-13 | 2024-08-30 | 山东云海国创云计算装备产业创新中心有限公司 | Data read request processing method and device, electronic equipment and storage medium |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7062591B2 (en) * | 2001-09-28 | 2006-06-13 | Dot Hill Systems Corp. | Controller data sharing using a modular DMA architecture |
| CN100483325C (en) * | 2004-06-23 | 2009-04-29 | 马维尔国际贸易有限公司 | Bridge connecting circuit |
| US7818500B2 (en) * | 2007-11-01 | 2010-10-19 | Pubali Ray | Apparatus and method for using one core for RAID control in multi-core CPU |
| US8646054B1 (en) * | 2012-03-23 | 2014-02-04 | Western Digital Technologies, Inc. | Mechanism to manage access to user data area with bridged direct-attached storage devices |
| TWI719880B (en) * | 2019-12-16 | 2021-02-21 | 慧榮科技股份有限公司 | Apparatus and method for programming data of page groups into flash units |
| CN112612733B (en) * | 2020-12-17 | 2024-12-24 | 联想长风科技(北京)有限公司 | A device and method for multiple machines to share RAID function |
-
2024
- 2024-09-18 CN CN202411299457.7A patent/CN118820146B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103942007A (en) * | 2013-01-18 | 2014-07-23 | 索尼公司 | RAID controller and command processing method thereof |
| CN118567904A (en) * | 2024-06-13 | 2024-08-30 | 山东云海国创云计算装备产业创新中心有限公司 | Data read request processing method and device, electronic equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118820146A (en) | 2024-10-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP7121875B1 (en) | Data integrity, such as persistent memory systems | |
| US12153529B2 (en) | Memory system and computing system including the same | |
| US5937174A (en) | Scalable hierarchial memory structure for high data bandwidth raid applications | |
| CN114902198B (en) | Signaling for heterogeneous memory systems | |
| JP2007508601A (en) | Apparatus and method for direct memory access in a hub-based storage system | |
| KR102897605B1 (en) | Memory device and operating method thereof | |
| US20230125792A1 (en) | Error recovery for non-volatile memory modules | |
| TWI512477B (en) | Method to configure a data width of a memory component,memory component, and related non-transitory machine-readable storage medium | |
| KR102446677B1 (en) | A method of operating a storage controller and a method of operating a data storage device including the storage controller | |
| CN114902197A (en) | Command replay for non-volatile dual in-line memory modules | |
| CN118820146B (en) | RAID engine and RAID bridge chip | |
| KR20230091006A (en) | Address generation for adaptive double device data correction sparing | |
| US20060218313A1 (en) | DMA circuit and computer system | |
| EP4375840A1 (en) | Memory controller, electronic system including the same and method of controlling memory access | |
| CN110413233B (en) | A solid state hard disk controller | |
| CN114415985A (en) | Stored data processing unit based on numerical control separation architecture | |
| US8131893B2 (en) | Memory device that mediates mutual communication among a pluraliity of CPUs | |
| CN119557246B (en) | Data transmission method, device, equipment and medium for memory expansion module | |
| CN117724659A (en) | Memory rate improving device, method, equipment and storage medium | |
| KR20260008153A (en) | HBM or other types of memory with FLC system | |
| CN119003445A (en) | Microprocessor, information processing method in microprocessor and electronic equipment | |
| CN119311210A (en) | A chiplet-based SSD solid state drive and its implementation solution | |
| HK1136368B (en) | A main circuit board with an integrated flash memory storage unit | |
| HK1136368A1 (en) | A main circuit board with an integrated flash memory storage unit | |
| JPH08137782A (en) | Computer system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 610096 Sichuan Province, Chengdu City, No. 399, West Section of Fucheng Avenue, Chengdu High-tech Development Zone, China (Sichuan) Free Trade Pilot Zone, Building 7, Unit 3, 14th Floor, Room 1409 Patentee after: Chengdu Xingtuo Microelectronics Technology Co.,Ltd. Country or region after: China Address before: No. 1409, 14th Floor, Unit 3, Building 7, No. 399 Fucheng Avenue West Section, High tech Zone, Chengdu City, Sichuan Province Patentee before: Chengdu CETC Xingtuo Technology Co.,Ltd. Country or region before: China |
|
| CP03 | Change of name, title or address |