CN110413233B - Solid state disk controller - Google Patents

Abstract

The present invention discloses a solid state drive controller, which is integrated and packaged as a single chip, and at least includes a CPU, a main control interface controller, a flash memory controller and a cache unit, wherein the CPU is connected to the main control interface controller, the flash memory controller and the cache unit, and is used to control the operation of the solid state drive controller; the main control interface controller is connected to an external host, and is used to transmit data with the external host; the cache unit uses SRAM, and is used to cache data received by the main control interface controller; the flash memory controller is connected to FLASH, and is used to store data in the cache unit into FLASH. Compared with the prior art, the present invention proposes a new SSD main control cache architecture, which uses SRAM to replace DRAM, and integrates the cache into the main control chip, thereby optimizing the system structure of the chip, optimizing the layout and wiring of the PCB and reducing the size to a certain extent, and greatly reducing the hardware cost.

Description

A solid state hard disk controller

Technical Field

The present invention relates to the field of memory technology, and in particular to a solid state hard disk controller.

Background Art

Solid-state drives (SSDs) have become the mainstream storage devices and are widely used for data storage in various fields. At present, the mainstream SSD architecture is shown in Figure 1. The solid-state drive controller (SSD controller) is an integrated package chip (ASIC), which is equipped with a host interface controller, a flash memory controller and a DRAM controller. Among them, the host interface controller (HostInterface Controller) is used as the front end to deal with the host, and the interface can be PCEI, SATA, SAS and other interfaces; the flash memory controller (Flash Controller) is used as the back end to deal with the flash memory (FLASH) and complete data encoding and decoding and ECC verification. In addition, there is a DRAM controller that is interconnected with the independently packaged DRAM through the AXI bus for data caching.

In the above architecture, DRAM is externally connected to the SSD controller via PCB wiring. Data is transmitted through the host interface, and the DRAM controller then applies to the CPU for permission to transmit the bus, and then writes the data to the corresponding address of DRAM, and notifies the flash controller. The flash controller takes the data out of DRAM and stores it in FLASH, thus completing the data storage process. Since the interface bandwidth of DRAM is generally larger than the data transmission bandwidth, it can continuously receive and process the read and write data of the host interface at full speed.

However, DRAM is expensive, usually more expensive than the integrated packaged SSD controller chip, which undoubtedly increases the hardware cost of SSD. At the same time, since DRAM and chips use completely different processes, it is impossible to integrate them into the chip. Therefore, in the design of SSD, the PCB needs to reserve space for DRAM, and the main controller needs to design an interface for external DRAM, which makes it impossible to further reduce the size of SSD.

Therefore, in view of the defects of the prior art, it is necessary to propose a technical solution to solve the technical problems existing in the prior art.

Summary of the invention

In view of this, it is indeed necessary to provide a solid-state drive controller that adopts the idea of replacing DRAM with SRAM and integrates the cache unit inside the solid-state drive controller, thereby completely getting rid of the system's dependence on DRAM. There is no need for external DRAM in the solid-state drive design, and the size of the solid-state drive can be further reduced and the cost can be reduced.

In order to solve the technical problems existing in the prior art, the technical solution of the present invention is as follows:

A solid state hard disk controller is integrated and packaged as a single chip, comprising at least a CPU, a main control interface controller, a flash memory controller and a cache unit, wherein:

The CPU is connected to the main control interface controller, the flash memory controller and the cache unit, and is used to control the operation of the solid state drive controller;

The host interface controller is connected to an external host and is used for data transmission with the external host;

The cache unit adopts SRAM to cache the data received by the master interface controller;

The flash memory controller is connected to FLASH and is used to store the data in the cache unit into FLASH.

As a further improvement, a cache controller is further provided, which is connected to the CPU, the host interface controller, the flash memory controller and the cache unit, and is used to control the cache unit according to the instructions of the CPU.

As a further improvement, an AXI bus is used between the cache controller and the cache unit.

As a further improvement, the bandwidth of the cache unit is at least twice the data input bandwidth of the host interface.

As a further improvement, the bandwidth of the cache unit is 4 GB/s.

As a further improvement, the main control interface controller adopts a PCEI, SATA or SAS interface.

Compared with the prior art, the present invention proposes a new SSD master control cache architecture, which uses SRAM to replace the DRAM module and integrates the cache into the master control chip, thereby optimizing the system structure of the chip and simplifying the original three modules of master control, DRAM, and FLASH into two modules of master control and FLASH. It optimizes the layout and wiring of the PCB and reduces its size to a certain extent, greatly reducing the hardware cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a solid state drive in the prior art.

FIG. 2 is a functional block diagram of a solid state drive controller according to the present invention.

FIG. 3 is a schematic block diagram of a solid state drive controller according to another embodiment of the present invention.

The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings.

DETAILED DESCRIPTION

The technical solution provided by the present invention will be further described below in conjunction with the accompanying drawings.

In the prior art, SSDs must use DRAM during operation, which increases the cost of SSDs. In response to this technical defect, the present invention proposes a new SSD master cache architecture. See FIG2 , which is a principle block diagram of the SSD controller of the present invention. The SSD controller is integrated and packaged as a single chip, which includes at least a CPU, a master interface controller, a flash memory controller, and a cache unit.

The CPU is connected to the main control interface controller, the flash memory controller and the cache unit, and is used to control the operation of the solid state drive controller;

The main control interface controller adopts an interface such as PCEI, SATA or SAS to connect to an external host for data transmission with the external host;

The cache unit adopts SRAM to cache the data received by the master interface controller;

The flash memory controller is connected to FLASH and is used to store the data in the cache unit into FLASH.

In the above technical solution, SRAM is used to replace DRAM. Since SRAM and the main control chip adopt the same process, the cache can be integrated into the main control chip, and there is no need to add external DRAM in the solid-state hard drive design.

Referring to FIG3 , a principle block diagram of a solid state drive controller according to another embodiment of the present invention is shown, in which a cache controller is further provided, and the cache controller is connected to the CPU, the host interface controller, the flash memory controller and the cache unit, and is used to control the cache unit according to the instructions of the CPU. The cache unit can be more conveniently controlled by the cache controller, and the specific control mechanism is as follows:

Assuming that the bandwidth of the cache unit is 4GB/s, the write rate of the host interface is 1GB/s, and the data is transmitted from the host interface, the host interface controller is responsible for decoding and verifying the incoming data, and then notifies the cache unit controller that there is data to be transmitted. The cache unit controller applies to the CPU for the right to use the system bus. After the cache unit controller obtains the right to use the system bus, it directly stores the data to be transmitted into the cache unit and notifies the flash memory controller, and then the flash memory controller directly takes out the data from the cache unit and writes it into FLASH. Since the bandwidth of the cache unit is greater than 2 times the data transmission bandwidth of the host interface, this design will not reduce the data transmission performance of the hard disk. The well-simplified design and layout and wiring work reduce the design cost.

In a preferred embodiment, a cache unit structure is used to replace DRAM and the same high-speed AXI bus structure as the existing DRAM is used. The cache unit design is integrated inside the main control chip during design, and the same AXI transmission bus as DRAM is simulated in the SOC for mutual communication. The secondary cache unit has the same data bandwidth and data processing speed as DRAM. Due to the use of the AXI bus structure, the storage capacity can be expanded by connecting to an external DRAM through the bus, thereby eliminating the interface circuit of the external DRAM part and replacing the external DRAM with a cache unit, while maintaining compatibility with the original architecture.

The above embodiments are only used to help understand the method and core idea of the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims (3)

1. A solid state drive controller, characterized in that the solid state drive controller is integrated and packaged as a single chip, comprising at least a CPU, a host interface controller, a flash memory controller and a cache unit, wherein: The CPU is connected to the main control interface controller, the flash memory controller and the cache unit, and is used to control the operation of the solid state drive controller; The host interface controller is connected to an external host and is used for data transmission with the external host; The cache unit adopts SRAM to cache the data received by the master interface controller; The flash memory controller is connected to FLASH and is used to store the data in the cache unit into FLASH; A cache controller is also provided, which is connected to the CPU, the master interface controller, the flash memory controller and the cache unit, and is used to control the cache unit according to the instructions of the CPU; an AXI bus is used between the cache controller and the cache unit, wherein an AXI bus identical to a DRAM is simulated in the chip; the bandwidth of the cache unit is at least twice the data input bandwidth of the host interface. 2. The solid-state hard disk controller according to claim 1, wherein a bandwidth of the cache unit is 4 GB/s. 3. The solid-state hard disk controller according to claim 1, wherein the main control interface controller adopts a PCEI, SATA or SAS interface.