CN118363914B

CN118363914B - Data processing method, solid state disk device and host

Info

Publication number: CN118363914B
Application number: CN202410788412.XA
Authority: CN
Inventors: 娄博杰; 钟戟; 李瑞东; 曾昭贵; 张靖
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2024-06-19
Filing date: 2024-06-19
Publication date: 2024-08-30
Anticipated expiration: 2044-06-19
Also published as: CN118363914A

Abstract

The application discloses a data processing method, solid state disk equipment and a host, and belongs to the technical field of data storage. The data processing method comprises the following steps: the host responds to the data reading operation, writes a data reading instruction into the submitting queue and sends first address indicating data to the solid state disk equipment; the method comprises the steps that solid state disk equipment sends a first reading instruction to a host through a request channel supported by a computing interconnection standard-cache protocol; the host reads the data reading instruction and sends a target reading instruction to the solid state disk device through calculating a response channel supported by the interconnection standard-cache protocol; the solid state disk equipment reads target data from a flash memory medium of the solid state disk equipment; the solid state disk equipment initiates a first memory write transaction to the host; the host writes the target data into the memory; the solid state disk device writes the completion status information of the data reading instruction into a completion queue in the memory; the solid state disk equipment initiates an interrupt transaction to the host; the host consumes completion status information in the completion queue.

Description

Data processing method, solid state disk device and host

Technical Field

The application relates to a data processing method, solid state disk equipment and a host.

Background

PCI-Express (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCIE) is a high-speed serial computer expansion bus standard, and has the advantages of high data transmission rate, high utilization efficiency of Input/Output (I/O) ports, high expansion flexibility and the like. Therefore, solid state disk (Solid STATE DRIVE, SSD) based on PCIE interface is popular because of higher sequential read/write speed and random read/write performance.

However, in the PCIE data processing system under the current computer system, the cache structure in the host may not cache the PCIE related memory transaction. In this way, in the data reading/writing process between the host and the SSD based on the PCIE interface, participation of the host memory is required, so that frequent memory transaction read/write operations exist between the host memory and the SSD in the current data reading/writing process. Thus, the current data read/write process has a problem of high delay.

Disclosure of Invention

The embodiment of the application aims to provide a data processing method, solid state disk equipment and a host, which can solve the problem of higher delay in the current data reading/writing process.

In order to solve the technical problems, the application is realized as follows:

In a first aspect, an embodiment of the present application provides a data processing method, applied to a data processing system, where the data processing system includes: the system comprises a solid state disk device and a host, wherein the solid state disk device is communicated with the host through a computing interconnection standard-cache protocol (namely CXL.cache protocol) and a computing interconnection standard-input/output protocol (namely CXL.io protocol); the method comprises the following steps:

the host responds to data reading operation, writes a data reading instruction into a submitting queue in a memory, and sends first address indicating data to the solid state disk device through a channel supported by a computing interconnection standard-input-output protocol, wherein the first address indicating data indicates a first instruction address of the data reading instruction;

the solid state disk device sends a first reading instruction to the host through a request channel supported by a computing interconnection standard-cache protocol, wherein the first reading instruction carries the first instruction address;

The host reads the data reading instruction according to the first instruction address, and sends a target reading instruction to the solid state disk device through a response channel supported by a computing interconnection standard-cache protocol, wherein the target reading instruction is used for indicating the solid state disk device to read target data to be read indicated by the data reading instruction;

The solid state disk device reads the target data from a flash memory medium of the solid state disk device;

The solid state disk equipment initiates a first memory write transaction to the host through a channel supported by a computing interconnection standard-input-output protocol, wherein the first memory write transaction carries the target data;

the host writes the target data into the memory;

the solid state disk device writes the completion state information of the data reading instruction into a completion queue in the memory;

the solid state disk equipment initiates an interrupt transaction to the host through a channel supported by a computing interconnection standard-input-output protocol;

the host consumes the completion status information in the completion queue.

In a second aspect, an embodiment of the present application provides a data processing method, applied to a data processing system, where the data processing system includes: the system comprises solid state disk equipment and a host, wherein the solid state disk equipment and the host are communicated through a computing interconnection standard-cache protocol and a computing interconnection standard-input-output protocol; the method comprises the following steps:

The host responds to a data writing operation, writes a data writing instruction into a submitting queue in a memory, and sends second address indicating data to the solid state disk device through a channel supported by a computing interconnection standard-input-output protocol, wherein the second address indicating data indicates a second instruction address of the data writing instruction, and the data writing instruction carries a data address of writing data to be written into a flash memory medium in the memory;

The solid state disk device sends a second reading instruction to the host through a request channel supported by a computing interconnection standard-cache protocol, wherein the second reading instruction carries the second instruction address;

The host reads the data writing instruction according to the second instruction address, and sends the data writing instruction to the solid state disk equipment through calculating a response channel supported by an interconnection standard-cache protocol;

the solid state disk equipment initiates a memory read transaction to the host through a channel supported by a computing interconnection standard-input-output protocol, wherein the memory read transaction carries a data address of the written data;

the host reads the written data according to the data address, and initiates a completion transaction to the solid state disk equipment through a channel supported by a computing interconnection standard-input/output protocol, wherein the completion transaction carries the written data;

The solid state disk device writes the writing data into the flash memory medium, and writes the completion state information of the data writing instruction into a completion queue in the memory;

The host consumes the completion status information of the data write instruction in the completion queue.

In a third aspect, an embodiment of the present application provides a solid state disk device, including: the system comprises a solid state disk control chip and a flash memory medium, wherein the solid state disk control chip comprises a computing interconnection standard controller, a processor and a flash memory controller; the physical channel between the computing interconnection standard controller and the host supports data communication of the computing interconnection standard-cache protocol and the computing interconnection standard-input-output protocol;

The processor is configured to send, when receiving first address indication data through a channel supported by a computing interconnection standard-input-output protocol provided by a computing interconnection standard controller, a first read instruction to the host through a request channel supported by the computing interconnection standard-cache protocol provided by the computing interconnection standard controller, where the first address indication data is data indicating a first instruction address of the data read instruction sent to the solid state disk device through a channel supported by the computing interconnection standard-input-output protocol after the host writes the data read instruction to a commit queue in a memory in response to a data read operation, and send, to the solid state disk device, a target read instruction to instruct the solid state disk device to read target data to be read indicated by the data read instruction through a response channel supported by the computing interconnection standard-cache protocol;

the flash memory controller is used for reading the target data from the flash memory medium;

The processor is further configured to initiate a first memory write transaction to the host through a channel supported by a computing interconnect standard-input-output protocol provided by a computing interconnect standard controller, where the first memory write transaction is used for the host to write the target data into the memory;

the processor is further configured to write completion status information of the data read instruction into a completion queue in the memory, and initiate an interrupt transaction to the host through a channel supported by a computing interconnect standard-input-output protocol provided by a computing interconnect standard controller, where the interrupt transaction is used for the host to consume the completion status information in the completion queue.

In a fourth aspect, embodiments of the present application provide a host, the host including: the device comprises a processor, a memory and a root node, wherein the processor is connected with solid state disk equipment and the memory through the root node; the root node comprises a protocol multiplexer, an input-output controller, a cache memory controller and a memory controller; the physical channel between the protocol multiplexer and the solid state disk device supports data communication of a computing interconnection standard-cache protocol and a computing interconnection standard-input-output protocol;

The processor is used for responding to data reading operation, writing a data reading instruction into a submission queue in the memory, sending first address indication data to the solid state disk device through a channel supported by a computing interconnection standard-input-output protocol provided by the protocol multiplexer, wherein the first address indication data indicates a first instruction address of the data reading instruction, the first address indication data is used for enabling the solid state disk device to send a first reading instruction to the host through a request channel supported by the computing interconnection standard-cache protocol, and the first reading instruction carries the first instruction address;

The memory controller is used for receiving the first reading instruction through a request channel supported by a computing interconnection standard-cache protocol provided by the protocol multiplexer;

The memory controller is further configured to read the data read instruction according to the first instruction address, send a target read instruction to the solid state disk device through a response channel supported by a computation interconnection standard-cache protocol provided by the protocol multiplexer, where the target read instruction is used for the solid state disk device to read target data indicated by the data read instruction from a flash memory medium of the solid state disk device, and initiate a first memory write transaction to the host through a channel supported by the computation interconnection standard-input/output protocol, where the first memory write transaction carries the target data;

The memory controller is further configured to receive the first memory write transaction through a channel supported by a computational interconnect standard-input-output protocol provided by the protocol multiplexer;

The memory controller is further configured to write the target data into the memory;

The processor is further configured to receive an interrupt transaction initiated by the solid state disk device to the host through a channel supported by a computing interconnection standard-input-output protocol provided by the protocol multiplexer, where the interrupt transaction is initiated to the host through the channel supported by the computing interconnection standard-input-output protocol by writing completion status information of the data reading instruction into a completion queue in the memory by the solid state disk device;

The processor is further configured to consume the completion status information of the data read instruction in the completion queue.

In a fifth aspect, an embodiment of the present application provides a data processing method, applied to a solid state disk device of a data processing system, where the data processing system further includes a host, and the solid state disk device communicates with the host through a computing interconnection standard-cache protocol and a computing interconnection standard-input/output protocol; the method comprises the following steps:

Under the condition that first address indication data is received through a channel supported by a computing interconnection standard-input-output protocol, a first reading instruction is sent to the host through a request channel supported by the computing interconnection standard-cache protocol, the first address indication data is data read instructions which are written into a submitting queue in a memory by the host in response to data read operation, after the data read instructions are written into the submitting queue in a memory, the data which are sent to the solid state disk device and indicate the first instruction address of the data read instructions are sent through the channel supported by the computing interconnection standard-input-output protocol, the first reading instruction is used for enabling the host to read the data read instructions according to the first instruction address, and a target reading instruction is sent to the solid state disk device through a response channel supported by the computing interconnection standard-cache protocol, and is used for indicating the solid state disk device to read target data to be read indicated by the data read instructions;

Receiving the target reading instruction by calculating a response channel supported by an interconnection standard-cache protocol;

reading the target data from the flash memory medium;

Initiating a first memory write transaction to the host through a channel supported by a computing interconnection standard-input-output protocol, wherein the first memory write transaction is used for the host to write the target data into the memory;

And writing the completion state information of the data reading instruction into a completion queue in the memory, and initiating an interrupt transaction to the host through a channel supported by a computing interconnection standard-input-output protocol, wherein the interrupt transaction is used for the host to consume the completion state information in the completion queue.

In a sixth aspect, an embodiment of the present application provides a data processing method, applied to a solid state disk device of a data processing system, where the data processing system further includes a host, and the solid state disk device communicates with the host through a computing interconnection standard-cache protocol and a computing interconnection standard-input/output protocol; the method comprises the following steps:

Under the condition that second address indication data is received through a channel supported by a computing interconnection standard-input-output protocol, sending a second read instruction to the host through a request channel supported by the computing interconnection standard-cache protocol, wherein the second address indication data is data address of a second instruction address which is sent to the solid state disk device through the channel supported by the computing interconnection standard-input-output protocol after the host responds to a data write operation and writes a data write instruction into a commit queue in a memory, the second read instruction is used for enabling the host to read the data write instruction according to the second instruction address, and sending the data write instruction to the solid state disk device through a response channel supported by the computing interconnection standard-cache protocol, wherein the data write instruction carries a data address of write data to be written into a flash memory medium in the memory;

Receiving the data writing instruction through calculating a response channel supported by an interconnection standard-cache protocol;

Initiating a memory read transaction to the host through a channel supported by a computing interconnection standard-input-output protocol, wherein the memory read transaction is used for the host to read the write data according to the data address, and initiating a completion transaction to the solid state disk device through the channel supported by the computing interconnection standard-input-output protocol, and the completion transaction carries the write data;

Receiving the completion transaction by computing channels supported by an interconnection standard-input-output protocol;

writing the write data to the flash memory medium;

And writing the completion state information of the data writing instruction into a completion queue in a memory, and initiating an interrupt transaction to the host through a channel supported by a computing interconnection standard-input-output protocol, wherein the interrupt transaction is used for the host to consume the completion state information of the data writing instruction in the completion queue.

In a seventh aspect, an embodiment of the present application provides a data processing method, applied to a host of a data processing system, where the data processing system further includes a solid state disk device, where the solid state disk device communicates with the host through a computing interconnection standard-cache protocol and a computing interconnection standard-input/output protocol; the method comprises the following steps:

Responding to data reading operation, writing a data reading instruction into a submission queue in a memory, and sending first address indication data to the solid state disk equipment through a channel supported by a computing interconnection standard-input-output protocol, wherein the first address indication data indicates a first instruction address of the data reading instruction, the first address indication data is used for enabling the solid state disk equipment to send a first reading instruction to the host through a request channel supported by the computing interconnection standard-cache protocol, and the first reading instruction carries the first instruction address;

Receiving the first read instruction by calculating a request channel supported by an interconnection standard-cache protocol;

Reading the data reading instruction according to the first instruction address, sending a target reading instruction to the solid state disk device through a response channel supported by a calculation interconnection standard-cache protocol, wherein the target reading instruction is used for the solid state disk device to read target data indicated by the data reading instruction from a flash memory medium of the solid state disk device, and initiating a first memory writing transaction to the host through the channel supported by the calculation interconnection standard-input/output protocol, wherein the first memory writing transaction carries the target data;

Receiving the first memory write transaction by calculating a channel supported by an interconnection standard-input-output protocol;

writing the target data into the memory;

Receiving an interrupt transaction initiated by the solid state disk device to the host through a channel supported by a computing interconnection standard-input-output protocol, wherein the interrupt transaction is initiated to the host through the channel supported by the computing interconnection standard-input-output protocol, and the solid state disk device writes the completion state information of the data reading instruction into a completion queue in the memory;

consuming the completion status information of the data read instruction in the completion queue.

In an eighth aspect, an embodiment of the present application provides a data processing method, applied to a host of a data processing system, where the data processing system further includes a solid state disk device, where the solid state disk device communicates with the host through a computing interconnection standard-cache protocol and a computing interconnection standard-input/output protocol; the method comprises the following steps:

Responding to a data writing operation, writing a data writing instruction into a commit queue in a memory, sending second address indicating data to the solid state disk device through a channel supported by a computing interconnection standard-input-output protocol, wherein the second address indicating data indicates a second instruction address of the data writing instruction, the second address indicating data is used for enabling the solid state disk device to send a second reading instruction to the host through a request channel supported by the computing interconnection standard-cache protocol, the second reading instruction carries the second instruction address, and the data writing instruction carries a data address of writing data to be written into a flash memory medium in the memory;

receiving the second read instruction by calculating a request channel supported by an interconnection standard-cache protocol;

Reading the data writing instruction according to the second instruction address, and sending the data writing instruction to the solid state disk device through a response channel supported by a computing interconnection standard-cache protocol, wherein the data writing instruction is used for enabling the solid state disk device to initiate a memory reading transaction to the host through the channel supported by the computing interconnection standard-input-output protocol, and the memory reading transaction carries the data address of the writing data;

receiving the memory read transaction by calculating a channel supported by an interconnection standard-input-output protocol;

Reading the written data according to the data address, initiating a completion transaction to the solid state disk device through a channel supported by a computing interconnection standard-input/output protocol, wherein the completion transaction carries the written data, the completion transaction is used for the solid state disk device to write the written data into the flash memory medium, the completion state information of the data writing instruction is written into a completion queue in the memory, and initiating an interrupt transaction to the host through the channel supported by the computing interconnection standard-input/output protocol;

Receiving the interrupt transaction by calculating a channel supported by an interconnection standard-input-output protocol;

and consuming the completion state information of the data writing instruction in the completion queue.

In a ninth aspect, an embodiment of the present application provides an electronic device, including: a processor, a memory and a program or instruction stored on the memory and executable on the processor, the program or instruction implementing the data processing method according to any one of the first, second, fifth to eighth aspects when executed by the processor.

In a tenth aspect, an embodiment of the present application provides a readable storage medium, on which a program or an instruction is stored, which when executed by a processor, implements the data processing method according to any one of the first, second, fifth to eighth aspects.

In an eleventh aspect, an embodiment of the present application provides a chip, where the chip includes a processor and a communication interface, where the communication interface is coupled to the processor, and the processor is configured to execute a program or instructions to implement a data processing method according to any one of the first aspect, the second aspect, the fifth aspect to the eighth aspect.

In a twelfth aspect, an embodiment of the present application provides a computer program product comprising a computer program/instruction which, when executed by a processor, implements a data processing method according to any one of the first, second, fifth to eighth aspects.

In the embodiment of the application, a data processing system responds to data reading operation through a host, writes a data reading instruction into a commit queue in a memory, and sends first address indication data to SSD equipment through a channel supported by CXL.io protocol. And the SSD device sends a first reading instruction to the host through a request channel supported by CXL.cache protocol. And the host reads the data reading instruction according to the first instruction address, and sends a target reading instruction to the SSD device through a response channel supported by the CXL.cache protocol. The SSD device reads target data to be read indicated by a data reading instruction from a flash memory medium of the SSD device, and the SSD device initiates a first memory writing transaction to a host through a channel supported by CXL.io protocol so that the host writes the target data into a memory. The SSD device writes the completion state information of the data reading instruction into a completion queue in the memory, and initiates an interrupt transaction to the host through a channel supported by the CXL.io protocol, so that the host consumes the completion state information in the completion queue, and the host reads target data in the SSD device. In the technical scheme, as the SSD device can send the first reading instruction to the host through the request channel supported by the CXL.cache protocol, the host sends the target reading instruction to the SSD device through the response channel supported by the CXL.cache protocol, so as to read target data by the SSD. Therefore, compared with the scheme that the SSD device requests the target data read instruction by utilizing the channel supported by the CXL.io protocol/PCIE protocol, the time delay of the channel supported by the CXL.cache protocol for transmitting the transaction is lower than that of the channel supported by the CXL.io protocol/PCIE protocol, and the time delay of the data read process of the host and the SSD device is reduced.

And the data processing system responds to the data writing operation through the host, writes a data writing instruction into a commit queue in the memory, and sends second address indication data to the SSD device through a channel supported by the CXL.io protocol. And the SSD device sends a second reading instruction to the host through a request channel supported by the CXL.cache protocol, so that the host reads the data writing instruction according to the second instruction address, and sends the data writing instruction to the SSD device through a response channel supported by the CXL.cache protocol. And the SSD device initiates a memory read transaction to the host through a channel supported by the CXL.io protocol, so that the host reads the write data according to the data address, and initiates a completion transaction to the SSD device through the channel supported by the CXL.io protocol. The SSD device writes the written data into the flash memory medium, writes the completion state information of the data writing instruction into a completion queue in the memory, and initiates an interrupt transaction to the host through a channel supported by the CXL.io protocol, so that the host consumes the completion state information in the completion queue, and the host is enabled to write the data into the SSD device. In the technical scheme, the SSD device can send the second reading instruction to the host through the request channel supported by the CXL.cache protocol, so that the host can send the data writing instruction to the SSD device through the response channel supported by the CXL.cache protocol, and the data writing instruction is used for reading the data writing instruction by the SSD device. Therefore, compared with the scheme that the SSD device uses the channel supported by the CXL.io protocol/PCIE protocol to request the data writing instruction, the time delay of the channel supported by the CXL.cache protocol to transmit the transaction is lower than that of the channel supported by the CXL.io protocol/PCIE protocol, and the time delay of the data writing process of the host and the SSD device is reduced.

Drawings

FIG. 1 is a block diagram of an SSD device provided by an embodiment of the present application;

FIG. 2 is a schematic diagram of a data processing method according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a data processing method according to a second embodiment of the present application;

FIG. 4 is a block diagram of one of the data processing systems provided by embodiments of the present application;

FIG. 5 is one of the flowcharts of the data processing method provided by the embodiment of the present application;

FIG. 6 is a schematic diagram of a third embodiment of a data processing method according to the present application;

FIG. 7 is a schematic diagram of a data processing method according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a data processing method according to an embodiment of the present application;

FIG. 9 is a second flowchart of a data processing method according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a data processing method according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a data processing method according to an embodiment of the present application;

FIG. 12 is a second block diagram of an SSD device according to an embodiment of the present application;

FIG. 13 is one of the block diagrams of the host provided by the embodiment of the application;

FIG. 14 is a third flowchart of a data processing method according to an embodiment of the present application;

FIG. 15 is a fourth flowchart of a data processing method according to an embodiment of the present application;

FIG. 16 is a fifth flowchart of a data processing method according to an embodiment of the present application;

FIG. 17 is a flowchart of a data processing method according to an embodiment of the present application;

fig. 18 is one of the block diagrams of the electronic device provided by the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

However, in the PCIE data processing system under the current computer system, the cache structure in the host may not cache the PCIE related memory transaction. In this way, in the data reading/writing process between the host and the SSD based on the PCIE interface, participation of the host memory is required, so that frequent memory transaction read/write operations exist between the host memory and the SSD in the current data reading/writing process. Thus, the delay of the data read/write process of the PCIE link is high.

A computing interconnect standard (Compute Express Link, CXL) protocol is currently proposed, which is intended to solve the high latency problem and achieve cache consistency in the data read/write process of the PCIE link at present. Among these, the CXL protocols include a compute interconnect standard-input-output protocol (i.e., CXL.io protocol), a compute interconnect standard-cache protocol (i.e., CXL.cache protocol), and a compute interconnect standard-storage protocol (i.e., CXL.memory protocol, also known as CXL.mem protocol).

The cxl.io protocol is based on PCIE standards and may be used for flash device discovery, flash device status reporting, virtual address to physical address translation and direct memory access of flash media, etc. All flash devices based on PCIE interfaces (also called PCIE devices) need to support the cxl.io protocol.

The cxl.cache protocol is used to cache data of the memory of the host on the flash device side. PCIE devices may optionally support the cxl.cache protocol.

The cxl.mem protocol is used to support the ability of the CPU and other CXL devices in the host to access the memory on the flash device side, and to use the memory on the flash device side as cacheable memory. PCIE devices may optionally support the cxl.cache protocol.

PCIE devices can be divided into three types of CXL devices according to different specific CXL protocols supported by the PCIE devices, and the three types of CXL devices are used for meeting the requirements of various use models.

First class CXL device: accelerators such as intelligent network interface cards. Which uses coherency semantics and PCIE supported direct memory access transfers. This type of CXL device supports the cxl.io protocol and the cxl.cache protocol.

CXL devices of the second class: various types of dedicated accelerators such as general purpose graphics processors, field programmable gate arrays, and the like. The method can be provided with a local memory which is partially mapped to the memory of the host side, and can also be used for caching the data of the memory of the host side for processing. This type of CXL device supports the cxl.io protocol, the cxl.cache protocol, and the cxl.mem protocol.

Third class CXL device: it can be used for memory bandwidth and capacity expansion. Such devices may be used to connect memories of different memory types, including multiple memory layers supporting connection to the CXL device side. This type of CXL device supports the cxl.io protocol and the cxl.mem protocol.

Currently, in PCIE data processing systems, SSD devices supporting the CXL protocol (i.e., CXL-SSD devices, PCIE-SSD devices) typically communicate with hosts using the cxl.io protocol. Specifically, in PCIE data processing systems, the memory of the host is mapped in system space as part of the system memory. The memory of the SSD device is used as a cache for the flash memory to hide the long latency between the host and the SSD device. The data read/write process between the host and the SSD device requires the involvement of the host's memory. Thus, in the current data reading/writing process, frequent memory transaction read-write operations exist between the memory of the host and the SSD device. The data read/write process of the PCIE link between the host and the SSD device currently has a high latency.

For example, as shown in fig. 1, the SSD device includes: SSD master chip, memory, flash controller and flash memory (i.e., flash media). SSD master control chip includes: the system comprises a processor, a front-end module, a cache controller and a cache. The front-end module includes a bus module (i.e., PCIE EP (Endpoint) module), a nonvolatile memory host controller interface (Non Volatile Memory Express, NVMe) controller (abbreviated as memory host controller in the present figure), and a network card (Network Interface Controller, NIC). The flash controller includes an Open NAND flash memory interface (Open NAND FLASH INTERFACE, ONFI) control layer and an ONFI physical layer (ONFI is referred to simply as a flash memory interface in the present figures). The memory may be dynamic random access memory (Dynamic Random Access Memory, DRAM). The flash memory may be an SSD. The corresponding relation exists between the storage space of the memory and the storage space of the flash memory in the SSD device. The memory space of the memory in the SSD device is configured as a cache of the corresponding memory space on the flash memory. The flash memory may include a plurality of storage media storing a mapping table of Logical Block Addresses (LBAs) of a storage space on the flash memory and flash page addresses (i.e., physical Block addresses) of the storage space. The mapping table records the correspondence between LBAs and flash page addresses. LBA of a storage space on flash memory is the physical block address (Physical Block Address, PBA) of the storage space on memory corresponding to that storage space. Thus, the mapping table of the LBA of the storage space on the flash memory and the flash page address of the storage space may also be referred to as the mapping table of the LBA of the storage space on the flash memory and the PBA. The mapping table records the corresponding relation between LBA and PBA of the storage space on the flash memory.

As shown in fig. 2, the process of the host reading data to the SSD device includes:

step 201, the host writes a data reading instruction into a commit queue in the memory.

Step 202, a host initiates a memory write transaction to an SSD device to write a tail doorbell (Tail Doorbell) to a first register of the SSD device and to send an address of a data read instruction in a commit queue to the SSD device. The tail doorbell is used for informing the SSD device host to write instructions into the commit queue.

Step 203, the SSD device initiates a memory read transaction to the host. The memory read transaction is used to fetch a data read instruction from a commit queue in memory. The memory may be a dynamic random access memory (Dynamic Random Access Memory, DRAM).

Step 204, the host initiates a Completion transaction to the SSD device. The completion transaction carries a data read instruction. The data read instruction instructs the SSD device to read the data of the target LBA, storing it to the target physical area page (Physical Region Page, PRP) in memory.

Step 205, the SSD device obtains the mapping table of LBA and PBA in the memory. And searching a target PBA corresponding to the target LBA from the mapping table of the LBA and the PBA. The SSD device reads the data of the target PBA from the flash memory through the flash memory controller, and stores the data into a cache in the SSD device through the cache controller.

Step 206, the SSD device initiates a memory write transaction to the host to write the data of the target PBA in the cache inside the SSD device to the target PRP address in the memory of the host.

Step 207, the SSD device initiates a memory write transaction to the host to write completion status information of the data read instruction to a completion queue in the host. The completion status information indicates completion of execution of the data read instruction by the SSD device. For example, the completion status information indicates whether the SSD device is executing a completion condition normally for a data read instruction.

Step 208, the SSD device initiates an interrupt transaction to the host. The interrupt transaction is used to tell the host SSD device to write information into the completion queue.

Step 209, the host consumes the completion status information of the data read instruction in the completion queue under the condition that the interrupt transaction is received.

Step 210, the host initiates a memory write transaction to the SSD device to update a head doorbell of a completion queue in a second register of the SSD device (Head Doorbell). Wherein, the host and the SSD device can communicate through a channel supported by PCIE protocol/CXL.io protocol. It will be readily seen that in the process of a host reading data to an SSD device, the PCIE link between the host and the SSD device involves a total of 7 PCIE/CXL.io transactions. In fig. 2, steps 201 to 210 are shown in order of 1 to 10.

As shown in fig. 3, the process of writing data by the host to the SSD device includes:

step 301, the host writes a data writing instruction into a commit queue in the memory.

Step 302, a host initiates a memory write transaction to an SSD device to write a tail gate bell and an address of a data read instruction in a commit queue to a first register of the SSD device. The tail doorbell is used for informing the SSD device host to write instructions into the commit queue.

Step 303, the SSD device initiates a memory read transaction to the host. The memory read transaction is used to fetch a data write instruction from a commit queue in memory.

Step 304, the host initiates a completion transaction to the SSD device. The completion transaction carries a data write instruction. The data write instruction instructs the SSD device to write data of the target PRP address in the host's memory to the target LBA in the flash memory.

Step 305, the SSD device initiates a memory read transaction to the host. The memory read transaction is used to read the data of the target PRP address in the memory.

Step 306, the host initiates a completion transaction to the SSD device to write the data of the target PRP address to the cache of the SSD device. The completion transaction carries the data of the target PRP address.

Step 307, the SSD device reads the data of the target PRP address from the cache by the flash controller using the cache controller, and writes the data to the flash memory. The SSD device determines the PBA of the data written in the flash memory through the flash memory controller, records the corresponding relation between the PBA and the target LBA in the data writing instruction, and adds the corresponding relation to the mapping table of the LBA and the PBA. And updating the mapping table of the added LBA and PBA into the memory of the SSD device by the SSD device through the flash memory controller so as to facilitate subsequent use.

Step 308, the SSD device initiates a memory write transaction to the host to write completion status information of the data write instruction to a completion queue in the host. The completion status information indicates completion of execution of the data write instruction by the SSD device. For example, the completion status information indicates whether the SSD device is executing a completion normally for a data write instruction.

Step 309, the SSD device initiates an interrupt transaction to the host. The interrupt transaction is used to tell the host SSD device to write information into the completion queue.

Step 310, the host consumes the completion status information of the data writing instruction in the completion queue under the condition that the host receives the interrupt transaction.

Step 311, the host initiates a memory write transaction to the SSD device to update the head doorbell of the completion queue in the second register of the SSD device. It will be readily seen that in the process of a host writing data to an SSD device, the PCIE link between the host and the SSD device involves a total of 8 PCIE/CXL.io transactions. In fig. 3, steps 301 to 311 are shown in order of 1 to 11. In the process of writing/reading data to/from the SSD device by the host illustrated by the example, frequent memory transaction read/write operations exist between the memory of the host and the SSD device, and the data reading/writing process of the PCIE link between the host and the SSD device has a relatively high latency.

Referring to FIG. 4, a schematic diagram of a data processing system according to an embodiment of the present application is shown. As shown in FIG. 4, a data processing system, also known as a CXL-SSD system, includes: SSD devices and hosts. The SSD device communicates with the host via CXL.cache protocol and CXL.io protocol.

Wherein a CXL-blockchain (CXL-Fabric) architecture is supported between the host and the SSD device. Data is streamed between the host and the SSD device via CXL. The host includes a processor, a root node, and a memory. The processor comprises a three-level cache, and specifically comprises a first-level cache (L1 cache), a second-level cache (L2 cache) and a three-level shared cache (L3 cache). The root node includes an input-output (IO) controller, a local agent, a memory controller, and a protocol multiplexer that are interconnected. The home agent includes: NVMe controller (i.e., memory host controller) and Cache controller (i.e., cache controller). Memory supports a host memory buffer (Host Memory Buffer, HMB) mechanism. The SSD device includes a flash memory medium to store data. Alternatively, the flash media of the SSD device may be SSDs. The data processing system can execute the two data processing methods provided by the embodiment of the application, so that delay of a PCIE link between a host and SSD equipment in the process of data reading/writing is effectively reduced. The following describes two data processing methods provided in the embodiments of the present application in detail.

Referring to fig. 5, a flow of a data processing method according to an embodiment of the application is shown. The data processing method is applied to the data processing system shown in FIG. 4 for a host to read data of an SSD device. As shown in fig. 5, the data processing method includes:

And step 501, the host responds to the data reading operation, writes a data reading instruction into a commit queue in the memory, and sends first address indication data to the solid state disk device by calculating a channel supported by an interconnection standard-input-output protocol. The first address indication data indicates a first instruction address of the data read instruction.

Alternatively, if the host needs to read data in the flash media of the SSD device, the host may generate or receive a data read operation to write a data read instruction to a commit queue in memory in response to the data read operation. The data read instruction is used for instructing the SSD device to read target data to be read. The data reading instruction may carry an address of target data to be read in a flash memory medium of the SSD device. In one alternative, the data read instruction carries a target LBA of a first storage space in the flash medium storing the target data. In another alternative, the data read instruction also carries the target PRP address where the target data is to be stored in memory. In this case, the data read instruction is used to instruct to read the target data and store the target data to the target PRP address in the memory of the host.

Step 502, the solid state disk device sends a first read instruction to the host through calculating a request channel supported by the interconnection standard-cache protocol. The first read instruction carries a first instruction address.

In the embodiment of the present application, the cxl.cache protocol may enable the SSD device to cache the data in the memory of the host using a Modified, shared, AND INVALID, MESI. It will be appreciated that the cxl.cache protocol supports SSD devices including device caches to cache data in the host's memory.

Wherein the cxl.cache protocol defines three channels in each communication direction between the host and the SSD device. The communication direction of each channel includes a host-to-SSD device (H2D) and an SSD device-to-host (D2H). The three channels include: a Request channel, a Response channel, and a Data (Data) channel. Wherein the Request channel may transmit class 4 commands (also called instructions) for a total of 15 commands in the direction of the SSD device to host communication (D2H Request channel). Class 4 commands include: read, read0-Write, write.

The Read command allows the SSD device to request that data be Read, and a cache coherency state for a cache line (CACHE LINE) in the device cache corresponding to the storage space in memory that stores the data. Based on the Read command, the Response information that the Response channel can transmit in the host-to-SSD device communication direction (H2D Response channel) includes: the cache consistency state of the cache line corresponding to the request and the specific response data corresponding to the request.

The Read0 command allows the SSD device to request only the cache coherency state of the device cache, and not Read data. Based on the Read0 command, the Response information that the Response channel can transmit in the host-to-SSD device communication direction (H2D Response channel) includes: cache coherency state of device cache provided by the host.

The Read0-Write command allows the SSD device to Write data directly to the host without requiring a cache coherency state of the device cache. Based on the Read0-Write command, when the host is ready to receive data written by the SSD device, the Response channel can transmit "WritePull" information in the host-to-SSD device communication direction (H2D Response channel) indicating that the SSD device can transmit data to the host, and that the data processing system (host and SSD device) solves the cache coherency problem of the device cache at a target time before globally observing (Globally Observed, GO) the data. The Response channel is also used to transmit state change indication information (Snooping) in the direction of host-to-SSD device communication (H2D Response channel). The state change indication information indicates that the SSD device needs to change the cache coherency state of the device cache. It should be noted that, the time delay of the transmission of the transaction between the host and the SSD device through the request channel supported by the cxl.cache protocol is lower than the time delay of the transmission of the transaction through the channel supported by the cxl.io protocol/PCIE protocol. I.e., the latency of cxl.cache transactions is lower than the latency of pcie.io/PCIe transactions during communication between the host and the SSD device. Therefore, the time delay of the PCIE link can be effectively reduced by improving the duty ratio of CXL.cache transactions in the communication process of the host and the SSD device, and the delay of the PCIE link is further reduced.

In the embodiment of the application, the SSD device can send the first read instruction to the host through a request channel supported by CXL.cache protocol, namely, initiate the first read instruction transaction to the host. The first read instruction carries a first instruction address of the data read instruction in the commit queue. Alternatively, the first Read instruction may be a Read command. The SSD device may send Read commands to the host over a request channel (D2H Response channel) supported by CXL.cache protocol.

And 503, the host reads the data reading instruction according to the first instruction address, and sends a target reading instruction to the solid state disk device through calculating a response channel supported by the interconnection standard-cache protocol.

Optionally, the host may receive the first read instruction sent by the SSD device through a request channel supported by the cxl.cache protocol. The host computer analyzes the first reading instruction, acquires a first instruction address, reads the data reading instruction from the memory according to the first instruction address, and sends a target reading instruction to the SSD device through an H2D Response channel supported by the CXL.cache protocol. The target reading instruction is used for indicating the SSD device to read target data to be read indicated by the data reading instruction.

In one alternative, the target read instruction is a data read instruction. The target read instruction carries a target LBA of a first storage space in the flash memory medium storing target data. In this case, the SSD device includes memory. The third storage space of the memory of the SSD device has a corresponding relation with the first storage space of the flash memory. The third storage space of the memory in the SSD device is configured as a cache of the corresponding first storage space on the flash memory. The memory and the flash memory are both stored with the corresponding relation between LBA and PBA of the first storage space. The LBA of the first storage space is the PBA of the third storage space corresponding to the first storage space in the memory.

In another alternative, the target read instruction is a new instruction generated from the data read instruction. The target read instruction carries a target PBA of a first storage space in the flash memory medium for storing target data. A detailed description of this case is described later.

Step 504, the solid state disk device reads target data from the flash memory medium.

Optionally, the SSD device may receive the target read instruction sent by the host through a request channel supported by the cxl.cache protocol. The SSD device parses a read-target instruction, reads the read-target data from its flash media, the read-target read instruction indicating the read-target data.

In one alternative, the target read instruction is a data read instruction. The SSD device may obtain the corresponding relationship between LBA and PBA of the storage space on the flash memory from the memory. And the SSD device determines a target PBA corresponding to the target LBA carried by the target reading instruction according to the corresponding relation between the LBA and the PBA, and reads target data of the target PBA from the flash memory medium.

In another alternative, the target read instruction is a new instruction generated from the data read instruction. The target read instruction carries a target PBA of a first storage space in the flash memory medium for storing target data. The SSD device can read target data directly from its flash media after receiving the target read instruction without performing virtual address to physical address translation processing.

Step 505, the solid state disk device initiates a first memory write transaction to the host through a channel supported by the computing interconnection standard-input/output protocol.

The first memory write transaction is used for writing target data into a memory of the host. The first memory write transaction carries target data. Optionally, if the data read instruction further carries a target PRP address where the target data is to be stored in the memory, the first memory write transaction is configured to write the target data to the target PRP address in the memory of the host. The first memory write transaction carries target data and a target PRP address.

Step 506, the host writes the target data into the memory.

Optionally, the host may receive the first memory write transaction initiated by the SSD device through a channel supported by the cxl.io protocol. And analyzing the first memory write transaction to obtain target data. And writing the target data into the memory. In one alternative implementation, the first memory write transaction carries the target data and the target PRP address. The host may parse the first memory write transaction to obtain target data and a target PRP address, and write the target data to the target PRP address of the memory.

And step 507, the solid state disk device writes the completion status information of the data reading instruction into a completion queue in the memory.

In an alternative implementation, the process of writing completion status information of a data read instruction to a completion queue in memory by an SSD device may include: the SSD device sends a first write instruction to a host through a request channel supported by CXL.cache protocol, wherein the first write instruction carries completion state information; the host writes the completion status information into a completion queue of the memory.

Optionally, the first Write instruction is a Write command. The SSD device may send a Write command to the host over a CXL.cache protocol supported request channel after initiating the first memory Write transaction to the host, such that the host may receive the Write command over the CXL.cache protocol supported request channel. When receiving the Write command, the host can analyze the Write command and Write the completion status information of the data reading instruction into the completion queue of the memory.

In another alternative implementation, the process of writing completion status information of a data read instruction to a completion queue in memory by an SSD device may include: the SSD device initiates a seventh memory write transaction to the host over a channel supported by the CXL.io protocol. The seventh memory write transaction carries completion status information. The seventh memory write transaction is used for writing the completion status information of the data read instruction to the completion queue in the memory of the host.

Step 508, the solid state disk device initiates an interrupt transaction to the host through a channel supported by the computing interconnection standard-input-output protocol.

Wherein the interrupt transaction is used to tell the host SSD device to write completion status information for the data read instruction into the completion queue.

Step 509, the host consumes the completion status information of the data read instruction in the completion queue.

Alternatively, the host may receive an interrupt transaction initiated by the SSD device over a channel supported by the cxl.io protocol. And under the condition that the interrupt transaction is received, consuming the completion state information of the data reading instruction in the completion queue, and processing the completion state information of the data reading instruction.

In one alternative implementation, the host and SSD device support a host memory buffer (Host Memory Buffer, HMB) mechanism. The host may configure the second storage space in the memory as HMB of the SSD device, sending an address of the second storage space to the SSD device. After each time of writing data into the flash memory medium, the SSD device may determine a correspondence between the first storage space and the second storage space of the written data, and obtain a correspondence between the PBA and the LBA of the first storage space of the written data. The LBA of the first storage space is the address of a second storage space corresponding to the first storage space, and the second storage space is the storage space configured by the host for the HMB of the SSD device from the memory.

Based on this, the method further comprises step 011 and step 012.

In step 011, the SSD device initiates a second memory write transaction to the host over a channel supported by the CXL.io protocol.

The second memory write transaction carries the corresponding relation between the PBA and the LBA. The second memory write transaction is used for writing the corresponding relation between the PBA and the LBA to the memory of the host.

In step 012, the host stores the PBA-LBA correspondence to the memory.

Wherein, the corresponding relation between PBA and LBA is: after the SSD device writes data into the flash memory medium and determines the corresponding relation between the first storage space and the second storage space of the written data, the obtained corresponding relation between the PBA and the LBA of the first storage space of the written data. It should be noted that, because the mapping file recording the corresponding relationship between PBA and LBA in the host memory has a one-to-one correspondence with the SSD device. Thus, the mapped file is not accessed by other devices than its corresponding SSD device. Therefore, the host can set the cache consistency state of the cache line of the cache mapping file in the device cache to be a single exclusive (E) state, so as to reduce the complexity of managing the cache consistency by the host.

Optionally, the host may parse the second memory write transaction to obtain a corresponding relationship between the PBA and the LBA when receiving the second memory write transaction through a channel supported by the cxl.io protocol.

For example, as shown in FIG. 6, during a power-up initiation phase of a data processing system, enumeration of CXL devices is performed first, and CXL device configuration is performed. In the CXL device configuration process, the NVMe driver of the host may configure the second storage space in the memory as the HMB of the SSD device, and send the address of the second storage space to the SSD device. The SSD device may also transmit the corresponding relationship between the PBA and the LBA to the host through a channel supported by the cxl.io protocol at the initial stage of power-on, so that the subsequent host uses the corresponding relationship between the PBA and the LBA.

Correspondingly, optionally, in the case that the host stores the correspondence between the PBA and the LBA of the first storage space in the flash memory medium, in step 503, the host reads the data read instruction according to the first instruction address, and the process of sending the target read instruction to the SSD device through the response channel supported by the cxl.cache protocol may include:

in step 5031, the host reads a data read command according to the first command address, where the data read command carries a target LBA of the target data.

Optionally, the host may receive the first read instruction sent by the SSD device through a request channel supported by the cxl.cache protocol. The host computer analyzes the first reading instruction, obtains a first instruction address, and reads the data reading instruction from the memory according to the first instruction address.

In step 5032, the host determines a target PBA corresponding to the target LBA according to the corresponding relationship between the PBA and the LBA, and generates a target read instruction carrying the target PBA.

Optionally, the host may read the PBA to LBA correspondence from its memory. Searching the corresponding relation between the PBA and the LBA, and under the condition that the target LBA is searched (hit) in the corresponding relation, acquiring the target PBA corresponding to the target LBA, and generating a target reading instruction carrying the target PBA.

In the event that the target LBA is not found (missed) in the correspondence, the host may initiate an eighth memory write transaction to the SSD device. The eighth memory write transaction is used for updating the corresponding relationship between the PBA and the LBA in the memory of the host by the SSD device. After receiving the corresponding relation between the PBA and the LBA stored in the SSD device, the host computer can write the corresponding relation between the received PBA and the LBA into the memory, and search the corresponding relation between the received PBA and the LBA again, determine the target PBA corresponding to the target LBA, and generate the target reading instruction carrying the target PBA.

In step 5033, the host sends a target read instruction to the SSD device via a response channel supported by the cxl.cache protocol.

In this way, since the HMB mechanism is utilized, the second storage space in the memory is configured as HMB of the SSD device, and the corresponding relationship between PBA and LBA of the first storage space of the write data in the SSD device can be stored in the memory of the host. Therefore, the host can directly convert the LBA carried by the data reading instruction into the PBA according to the corresponding relation between the PBA and the LBA under the condition that the data reading instruction is obtained, and then package the PBA to the target reading instruction and send the target reading instruction to the SSD device. Thus, the SSD device can directly read data by utilizing the PBA carried by the target reading instruction without an on-board memory of the device. Therefore, the cost of the SSD device can be effectively reduced, and the universality of the SSD device is improved.

In an alternative implementation, the process of sending the first address indication data to the SSD device by the host over the channel supported by the cxl.io protocol may include: the host initiates a third memory write transaction to the SSD device over a channel supported by the CXL.io protocol to write a tail doorbell of the commit queue to a first register of the SSD device. The third memory write transaction carries the first address indication data and Tail Doorbell.

Based on this, the process of sending the first read instruction to the host by the SSD device through the request channel supported by the cxl.cache protocol may include: under the condition that the first register is written Tail Doorbell and the first address indication data is received, the SSD device sends a first read instruction to the host through a request channel supported by CXL.cache protocol.

Accordingly, after consuming the completion status information in the completion queue, the host may initiate a fourth memory write transaction to the SSD device over the channel supported by the cxl.io protocol. The SSD device updates a head doorbell of the completion queue in the second register. The fourth memory write transaction is used for updating a head doorbell of a completion queue in a second register of the SSD device. The SSD device can update the head doorbell of the completion queue in the second register upon receiving a fourth memory write transaction over a channel supported by the CXL.io protocol.

In order to better understand the technical solution of the present application, the following two examples are used to further describe the data reading process of the SSD device by the host in the data processing method provided in the embodiments of the present application.

As shown in fig. 7, the data processing method includes:

In step 701, the host responds to the data reading operation, and writes a data reading instruction into a commit queue in the memory.

Step 702, the host initiates a third memory write transaction to the SSD device to write a tail doorbell to a first register of the SSD device (Tail Doorbell), and sends an address of the data read instruction in a commit queue to the SSD device. The tail doorbell is used for informing the SSD device host to write instructions into the commit queue.

Step 703, the SSD device sends Read instruction to the host through a request channel supported by the cxl. The Read command is used to request a data Read instruction and a cache coherency state of a cache line storing the data Read instruction. The data read instruction is to instruct to store the data of the target LBA in the SSD device to the target PRP address in the host memory.

Step 704, the host obtains an address mapping table in the memory. If the corresponding relation between the LBA and the PBA recorded in the address mapping table has the target LBA, determining the target PBA corresponding to the target LBA according to the corresponding relation between the LBA and the PBA, and generating the target reading instruction. And if the corresponding relation between the LBA and the PBA recorded in the address mapping table does not contain the target LBA, re-requesting the address mapping table stored by the SSD device to re-search the target PBA corresponding to the target LBA.

Step 705, the host sends a target read instruction and a cache consistency state to the SSD device through a response channel supported by the cxl.

In step 706, the SSD device reads the data of the target PBA from the flash memory through the flash memory controller, and stores the data into the cache in the SSD device through the cache controller.

Step 707, the SSD device initiates a memory write transaction to the host to write the data of the target PBA in the cache inside the SSD device to the target PRP address in the memory of the host.

Step 708, the SSD device initiates a memory write transaction to the host to write completion status information of the data read instruction to a completion queue in the host. The completion status information indicates completion of execution of the data read instruction by the SSD device. For example, the completion status information indicates whether the SSD device is executing a completion condition normally for a data read instruction.

Step 709, the SSD device initiates an interrupt transaction to the host. The interrupt transaction is used to tell the host SSD device to write information into the completion queue.

Step 710, the host consumes the completion status information of the data reading instruction in the completion queue under the condition that the host receives the interrupt transaction.

Step 711, the host initiates a memory write transaction to the SSD device to update the head doorbell of the completion queue in the SSD device's second register (Head Doorbell). It is apparent that, in the process of reading data from the SSD device by the host, the PCIE link between the host and the SSD device involves 5 PCIE/cxl.io transactions and 2 cxl.io transactions altogether, which reduces PCIE/cxl.io transactions in the data reading process and reduces delay in the data reading process compared with the process shown in fig. 2. In fig. 7, steps 701 to 711 are shown in order of 1 to 11.

As shown in fig. 8, the data processing method includes:

step 801, the host responds to the data reading operation to write a data reading instruction into a commit queue in the memory.

Step 802, the host initiates a third memory write transaction to the SSD device to write the tail doorbell to the first register of the SSD device, and sends an address of the data read instruction in the commit queue to the SSD device. The tail doorbell is used for informing the SSD device host to write instructions into the commit queue.

Step 803, the SSD device sends Read instruction to the host through a request channel supported by the cxl. The Read command is used to request a data Read instruction and a cache coherency state of a cache line storing the data Read instruction. The data read instruction is to instruct to store the data of the target LBA in the SSD device to the target PRP address in the host memory.

Step 804, the host obtains the address mapping table in the memory. If the corresponding relation between the LBA and the PBA recorded in the address mapping table has the target LBA, determining the target PBA corresponding to the target LBA according to the corresponding relation between the LBA and the PBA, and generating the target reading instruction. And if the corresponding relation between the LBA and the PBA recorded in the address mapping table does not contain the target LBA, re-requesting the address mapping table stored by the SSD device to re-search the target PBA corresponding to the target LBA.

And step 805, the host sends a target reading instruction and a cache consistency state to the SSD device through a response channel supported by CXL.cache protocol.

Step 806, the SSD device reads the data of the target PBA from the flash memory through the flash memory controller, and stores the data into a cache in the SSD device through the cache controller.

Step 807, the SSD device initiates a memory write transaction to the host to write the data of the target PBA in the cache inside the SSD device to the target PRP address in the memory of the host.

Step 808, the SSD device sends a Write instruction to the host through a request channel supported by the cxl. The Write instruction is used to Write completion status information of the data read instruction to a completion queue in the host.

Step 809, the SSD device initiates an interrupt transaction to the host. The interrupt transaction is used to tell the host SSD device to write information into the completion queue.

Step 810, the host consumes the completion status information of the data reading instruction in the completion queue under the condition that the host receives the interrupt transaction.

In step 811, the host initiates a memory write transaction to the SSD device to update the head doorbell of the completion queue in the second register of the SSD device. As can be seen, in the process of reading data from the SSD device by the host, the PCIE link between the host and the SSD device involves 4 PCIE/cxl.io transactions and 3 cxl.io transactions altogether, which further reduces the PCIE/cxl.io transactions in the data reading process and more effectively reduces the delay in the data reading process compared with the process shown in fig. 2. In fig. 8, steps 801 to 811 are shown in order of 1 to 11.

Referring to fig. 9, a flow of a data processing method according to an embodiment of the application is shown. The data processing method is applied to the data processing system shown in fig. 4 for a host to write data of an SSD device. As shown in fig. 9, the data processing method includes:

Step 901, a host responds to a data writing operation, a data writing instruction is written into a submitting queue in a memory, second address indicating data is sent to a solid state disk device through a channel supported by a computing interconnection standard-input-output protocol, the second address indicating data indicates a second instruction address of the data writing instruction, and the data writing instruction carries a data address of writing data to be written into a flash memory medium in the memory.

Alternatively, if the host needs to write data to the flash media of the SSD device, the host may generate or receive a data write operation to write a data write instruction to a commit queue in memory in response to the data write operation. The data write instruction is used for indicating write data to be written into the SSD device. The data writing instruction may carry an address of writing data to be written in a memory of the host. In one alternative, the data write instruction carries a target PRP address in host memory where the write data is stored. In another alternative, the data read instruction also carries the target LBA of write data that is required to be stored in the flash media of the SSD device. In this case, the data write instruction is used to instruct to store the data of the target PRP address in the memory to the target LBA in the SSD device.

Step 902, the SSD device sends a second read instruction to the host through a request channel supported by the compute interconnect standard-cache protocol. The second read instruction carries a second instruction address.

In the embodiment of the application, the SSD device sends a second read instruction to the host, namely, sends a second read instruction transaction to the host through a request channel supported by CXL.cache protocol. Alternatively, the second Read instruction may be a Read command. The SSD device may send Read commands to the host over a request channel (D2H Response channel) supported by CXL.cache protocol. The Read command carries the second instruction address of the data write instruction in the commit queue.

And 903, the host reads the data writing instruction according to the second instruction address, and sends the data writing instruction to the solid state disk device through calculating a response channel supported by the interconnection standard-cache protocol.

Optionally, the host receives the second read instruction sent by the SSD device through a request channel supported by the cxl.cache protocol. The host analyzes the second read instruction, acquires a second instruction address, and reads the data write instruction from the memory according to the second instruction address. And the host sends a data writing instruction to the SSD device through an H2D Response channel supported by the CXL.cache protocol.

Step 904, the SSD device initiates a memory read transaction to the host through a channel supported by the compute interconnect standard-input-output protocol. The memory read transaction carries the data address of the write data.

The memory read transaction is used for reading the write data in the host memory. The memory read transaction carries the data address of the write data. Alternatively, the memory read transaction may carry the PRP address in the memory where the data is written.

In step 905, the host reads the write-in data according to the data address, and initiates a completion transaction to the solid state disk device through a channel supported by the computing interconnection standard-input/output protocol. The completion transaction carries the write data.

Optionally, the host receives a memory read transaction initiated by the SSD device through a channel supported by the cxl.io protocol. And the host analyzes the memory read transaction to obtain the data address. And the host reads the data stored by the data address from the memory to obtain the writing data to be written into the SSD device. The host initiates a completion transaction carrying the write data to the SSD device over a channel supported by the CXL.io protocol.

Step 906, the SSD device writes the write data into the flash memory medium, and writes completion status information of the data write instruction into a completion queue in the memory.

Alternatively, the SSD device can receive a host initiated completion transaction over a channel supported by the CXL.io protocol. And the SSD device analyzes the completed transaction to obtain the written data. The SSD device may write the write data to the flash memory through the flash memory controller. The SSD device obtains the PBA of the flash memory medium for storing the writing data, determines the LBA corresponding to the PBA, and obtains and stores the corresponding relation between the PBA and the LBA.

Wherein, in an alternative case, the SSD device includes memory. The third storage space of the memory of the SSD device has a corresponding relation with the first storage space of the flash memory. The third storage space of the memory in the SSD device is configured as a cache of the corresponding first storage space on the flash memory. After obtaining the PBA of the first storage space storing the writing data in the flash memory medium, the SSD device determines a third storage space corresponding to the first storage space, and obtains and stores the corresponding relation between the PBA and the LBA of the first storage space. The LBA corresponding to the PBA of the first storage space is the address of the third storage space corresponding to the first storage space.

In another alternative implementation, the host and SSD device support the HMB mechanism. The host configures the second storage space in the memory as HMB of the SSD device, and sends an address of the second storage space to the SSD device. After obtaining the PBA of the target first storage space for storing the writing data in the flash memory medium, the SSD device determines a target second storage space corresponding to the target first storage space in the host memory, and obtains and stores the corresponding relation between the PBA of the target first storage space and the LBA. The LBA of the target first storage space is the PRP address of the target second storage space. It should be noted that a detailed description of this case will be given later.

In the embodiment of the application, after writing the writing data into the flash memory medium, the SSD device can also write the completion status information of the data writing instruction into the completion queue in the memory.

In an alternative implementation, the process of writing completion status information of a data write instruction to a completion queue in memory by an SSD device may include: the SSD device sends a second write instruction to the host through a request channel supported by CXL.cache protocol, wherein the second write instruction carries completion state information; and the host writes the completion status information of the data writing instruction into a completion queue of the memory.

Optionally, the second Write instruction is a Write command. The SSD device may send a Write command to the host over a CXL.cache protocol supported request channel after writing the Write data to the flash memory medium, such that the host may receive the Write command over the CXL.cache protocol supported request channel. When receiving the Write command, the host can parse the Write command and Write the completion status information of the data writing instruction into the completion queue of the memory.

In another alternative implementation, the process of the SSD device writing completion status information of the data write instruction to the completion queue in the memory may include: the SSD device initiates a ninth memory write transaction to the host over a channel supported by the CXL.io protocol. The ninth memory write transaction carries completion status information for the data write instruction. The ninth memory write transaction is used for writing the completion status information of the data write instruction to the completion queue in the memory of the host.

Step 907, the SSD device initiates an interrupt transaction to the host by computing channels supported by the interconnect standard-input-output protocol.

Wherein the interrupt transaction is used to tell the host SSD device to write completion status information for the data write instruction into the completion queue.

Step 908, the host consumes the completion status information of the data write instruction in the completion queue.

Alternatively, the host may receive an interrupt transaction initiated by the SSD device over a channel supported by the cxl.io protocol. And under the condition that the interrupt transaction is received, consuming the completion state information of the data writing instruction in the completion queue, and processing the completion state information of the data writing instruction.

In the embodiment of the application, the data processing system responds to the data writing operation through the host computer, writes a data writing instruction into a commit queue in the memory, and sends second address indication data to the SSD device through a channel supported by the CXL.io protocol. And the SSD device sends a second reading instruction to the host through a request channel supported by the CXL.cache protocol, so that the host reads the data writing instruction according to the second instruction address, and sends the data writing instruction to the SSD device through a response channel supported by the CXL.cache protocol. And the SSD device initiates a memory read transaction to the host through a channel supported by the CXL.io protocol, so that the host reads the write data according to the data address, and initiates a completion transaction to the SSD device through the channel supported by the CXL.io protocol. The SSD device writes the written data into the flash memory medium, writes the completion state information of the data writing instruction into a completion queue in the memory, and initiates an interrupt transaction to the host through a channel supported by the CXL.io protocol, so that the host consumes the completion state information in the completion queue, and the host is enabled to write the data into the SSD device. In the technical scheme, the SSD device can send the second reading instruction to the host through the request channel supported by the CXL.cache protocol, so that the host can send the data writing instruction to the SSD device through the response channel supported by the CXL.cache protocol, and the data writing instruction is used for reading the data writing instruction by the SSD device. Therefore, compared with the scheme that the SSD device uses the channel supported by the CXL.io protocol/PCIE protocol to request the data writing instruction, the time delay of the channel supported by the CXL.cache protocol to transmit the transaction is lower than that of the channel supported by the CXL.io protocol/PCIE protocol, and the time delay of the data writing process of the host and the SSD device is reduced.

In one alternative implementation, the host and SSD device support the HMB mechanism. As previously described, the host may also configure the second storage space in the memory as HMB of the SSD device, sending the address of the second storage space to the SSD device. After each time of writing data into the flash memory medium, the SSD device may determine a correspondence between the first storage space and the second storage space of the written data, and obtain a correspondence between the PBA and the LBA of the first storage space of the written data. The LBA of the first storage space is the address of a second storage space corresponding to the first storage space, and the second storage space is the storage space configured by the host for the HMB of the SSD device from the memory.

Based on this, the foregoing process of writing the write data to the flash memory medium by the device in step 906 SSD, and writing the completion status information of the data write instruction to the completion queue in the memory may include: and the SSD device writes the writing data into the flash memory medium, determines the corresponding relation between the target first storage space and the target second storage space in the memory, and obtains and stores the corresponding relation between the PBA and the LBA of the target first storage space. The SSD device writes completion status information for the data write instruction to a completion queue in memory. The target first storage space is a first storage space for storing writing data in the flash memory medium; the LBA of the target first storage space is the address of the target second storage space;

the method further comprises, correspondingly optionally, steps 021 to 023.

In step 021, the host configures the second storage space in the memory as HMB of the SSD device, and sends the address of the second storage space to the SSD device.

Alternatively, the host may configure the second storage space in the memory as HMB of the SSD device through the NVMe driver, and send the address of the second storage space to the SSD device. For example, the host may configure the random second storage space in the memory as HMB of the SSD device through the NVMe driver, and send the address of the second storage space to the SSD device through the channel supported by the cxl.io protocol.

In step 022, the SSD device initiates a second memory write transaction to the host over a channel supported by the CXL.io protocol.

The second memory write transaction carries the corresponding relation between the PBA and the LBA of the first storage space in the flash memory medium. The second memory write transaction is used for writing the corresponding relation between the PBA and the LBA to the memory of the host.

For example, during a power-up initiation phase of a data processing system, enumeration of a CXL device may be performed first, followed by execution of a CXL device configuration. In the CXL device configuration process, the NVMe driver of the host may configure the second storage space in the memory as the HMB of the SSD device, and send the address of the second storage space to the SSD device. The SSD device may also transmit the corresponding relationship between the PBA and the LBA to the host through a channel supported by the cxl.io protocol at the initial stage of power-on, so that the subsequent host uses the corresponding relationship between the PBA and the LBA.

In step 023, the host stores the PBA to LBA correspondence to the memory. The corresponding relation is used for the host to read the data from the flash memory medium according to the LBA of the data to be read.

Alternatively, the host may receive the second memory write transaction through a channel supported by the cxl.io protocol. And the host analyzes the second memory write transaction to obtain the corresponding relation between the PBA and the LBA of the first memory space in the flash memory medium. It should be noted that, the implementation manner of the corresponding relationship for the host to read data from the flash memory medium according to the LBA of the data to be read specifically refers to the foregoing description of the host in the data reading process of the SSD device, which is not described herein in detail. Reference may be made, for example, to the relevant description of steps 701 to 703.

In yet another alternative implementation, the process of sending the second address indication data to the SSD device by the host over the channel supported by the cxl.io protocol may include: the host initiates a fifth memory write transaction to the SSD device over the channel supported by the CXL.io protocol to write Tail Doorbell of the commit queue to the first register of the SSD device. The fifth memory write transaction carries the second address indication data and Tail Doorbell.

Based on this, the process of sending the second read instruction to the host by the SSD device through the request channel supported by the cxl.cache protocol may include: and under the condition that the first register is written Tail Doorbell and the second address indication data is received, the SSD device sends a second reading instruction to the host through a request channel supported by the CXL.cache protocol.

Accordingly, after consuming the completion status information of the data writing instruction in the completion queue, the host may initiate a sixth memory writing transaction to the SSD device through a channel supported by the cxl.io protocol. The SSD device updates a head doorbell of the completion queue in the second register. The sixth memory write transaction is used to update a head doorbell of a completion queue in a second register of the SSD device. The SSD device can update the head doorbell of the completion queue in the second register upon receiving a sixth memory write transaction over a channel supported by the CXL.io protocol.

In order to better understand the technical solution of the present application, the following two examples are used to further describe the data writing process of the SSD device by the host in the data processing method provided in the embodiments of the present application.

As shown in fig. 10, the data processing method includes:

In step 1001, the host writes a data write instruction to a commit queue in the memory in response to a data write operation.

Step 1002, the host initiates a fifth memory write transaction to the SSD device to write the tail doorbell to the first register of the SSD device, and sends an address of the data write instruction in the commit queue to the SSD device. The tail doorbell is used for informing the SSD device host to write instructions into the commit queue.

Step 1003, the SSD device sends Read instruction to the host through a request channel supported by the cxl. The Read command is used to request a data write instruction and to store a cache coherency state of a cache line of the data write instruction. The data write instruction is to instruct write data of a target PRP address in the memory to a target LBA in the SSD device.

Step 1004, the host sends a data writing instruction and a cache consistency state to the SSD device through a response channel supported by CXL.cache protocol.

In step 1005, the SSD device initiates a memory read transaction to the host over a channel supported by CXLio protocols. The memory read transaction is used to read the write data of the target PRP address from the host memory.

In step 1006, the host initiates a completion transaction to the SSD device over the channel supported by CXLio protocol. The completion transaction is also used to write the write data of the target PRP address to a buffer inside the SSD device.

Step 1007, the SSD device stores the write data to the flash media through the flash controller. And acquiring the PBA for storing the writing data, and determining the corresponding relation between the PBA and the target LBA in the data writing instruction. And the SSD device writes the corresponding relation between the PBA and the target LBA in the data writing instruction into the address mapping table. The address mapping table is used for recording the corresponding relation between LBA and PBA of a first storage space for writing data in the flash memory medium.

In step 1008, the SSD device initiates a ninth memory write transaction to the host through a channel supported by CXLio protocol, so as to write the completion status information of the data write instruction to the completion queue in the host memory.

Step 1009, the SSD device initiates an interrupt transaction to the host. The interrupt transaction is used to tell the host SSD device to write information into the completion queue.

In step 1010, the host consumes the completion status information of the data write instruction in the completion queue when receiving the interrupt transaction.

In step 1011, the host initiates a sixth memory write transaction to the SSD device via a channel supported by the CXLio protocol, to update the head doorbell of the completion queue in the second register of the SSD device. It is apparent that in the process of writing data into the SSD device by the host, the PCIE link between the host and the SSD device involves 5 PCIE/cxl.io transactions and 2 cxl.io transactions altogether, which reduces PCIE/cxl.io transactions in the data reading process and reduces the delay of the data reading process compared with the process shown in fig. 3. In fig. 10, steps 1001 to 1011 are shown in order of 1 to 11.

As shown in fig. 11, the data processing method includes:

step 1101, the host writes a data write instruction to a commit queue in the memory in response to the data write operation.

In step 1102, the host initiates a fifth memory write transaction to the SSD device to write the tail doorbell to the first register of the SSD device, and sends an address of the data write instruction in the commit queue to the SSD device. The tail doorbell is used for informing the SSD device host to write instructions into the commit queue.

In step 1103, the SSD device sends a Read instruction to the host through a request channel supported by the cxl.cache protocol. The Read command is used to request a data write instruction and to store a cache coherency state of a cache line of the data write instruction. The data write instruction is to instruct write data of a target PRP address in the memory to a target LBA in the SSD device.

Step 1104, the host sends a data writing instruction and a cache consistency state to the SSD device through a response channel supported by the cxl.

In step 1105, the SSD device initiates a memory read transaction to the host through a channel supported by CXLio protocol. The memory read transaction is used to read the write data of the target PRP address from the host memory.

Step 1106, the host initiates a completion transaction to the SSD device over the channel supported by CXLio protocol. The completion transaction is also used to write the write data of the target PRP address to a buffer inside the SSD device.

Step 1107, the SSD device stores the write data to the flash media through the flash controller. And acquiring the PBA for storing the writing data, and determining the corresponding relation between the PBA and the target LBA in the data writing instruction. And the SSD device writes the corresponding relation between the PBA and the target LBA in the data writing instruction into the address mapping table. The address mapping table is used for recording the corresponding relation between LBA and PBA of a first storage space for writing data in the flash memory medium.

In step 1108, the SSD device sends a Write instruction to the host through a request channel supported by the cxl. Write instruction is used to Write completion status information of a data Write instruction to a completion queue in a host

Step 1109, the SSD device initiates an interrupt transaction to the host. The interrupt transaction is used to tell the host SSD device to write information into the completion queue.

Step 1110, the host consumes the completion status information of the data write instruction in the completion queue when receiving the interrupt transaction.

And 1111, the host initiates a sixth memory write transaction to the SSD device via a channel supported by the CXLio protocol, so as to update the head doorbell of the completion queue in the second register of the SSD device. As can be seen, in the process of writing data to the SSD device by the host, the PCIE link between the host and the SSD device involves 4 PCIE/cxl.io transactions and 3 cxl.io transactions altogether, which further reduces PCIE/cxl.io transactions in the data reading process and further reduces the delay in the data reading process compared with the process shown in fig. 3. In fig. 11, steps 1101 to 1111 are shown in order of 1 to 11.

Based on the foregoing method side description, the following describes a host and an SSD device in a data processing system according to an embodiment of the application.

Fig. 12 is a schematic structural diagram of an SSD device according to an embodiment of the application. SSD devices may also be referred to as being cache-less type 1CXL-SSD devices. As shown in fig. 12, the SSD device includes: SSD control chip and flash memory medium. The SSD control chip comprises a CXL controller, a processor and a flash memory controller. The physical channel between the CXL controller and the host supports the CXL.cache protocol and the CXL.io protocol data communication.

The processor is used for sending a first reading instruction to the host through a CXL.cache protocol supported request channel provided by the CXL controller under the condition that the first address indication data is received through the CXL.io protocol supported channel provided by the CXL controller. The first address indicating data is data of a first instruction address, which is sent to the SSD device through a channel supported by the CXL.io protocol after a data reading instruction is written into a commit queue in a memory by a host in response to a data reading operation. The first reading instruction carries the first instruction address, and is used for enabling the host to read the data reading instruction according to the first instruction address, and sending a target reading instruction to the SSD device through a response channel supported by the CXL.cache protocol. The target read instruction is used for indicating the SSD device to read target data to be read indicated by the data read instruction.

The flash controller is used for reading target data from a flash memory medium thereof.

The processor is further configured to initiate a first memory write transaction to the host over a channel supported by a cxl.io protocol provided by the CXL controller. The first memory write transaction carries target data. The first memory write transaction is used for the host to write target data into the memory.

The processor is further configured to write completion status information of the data read instruction into a completion queue in the memory, initiate an interrupt transaction to the host through a channel supported by a cxl.io protocol provided by the CXL controller, the interrupt transaction being configured to consume the completion status information in the completion queue by the host.

Optionally, the CXL controller includes a protocol multiplexer, an NVMe controller, and a NIC bus. The CXL controller is used for providing two protocol access paths of CXL.io protocol and CXL.cache protocol. The protocol multiplexer is used for providing two protocol access paths of CXL.io protocol and CXL.cache protocol. A protocol multiplexer can be understood as a protocol module of a first type CXL device. The protocol multiplexer includes: a Physical (PHY) layer and a control (Ctrl) layer. The PHY layer may be used to provide serial-to-parallel conversion of data, clock recovery, and the like. The Ctrl layer is used to provide the implementation logic of the protocol stack of the cxl.io protocol and the cxl.cache protocol. Wherein two protocol stacks may multiplex the PHY layer for transmitting/receiving data. In one alternative, the NVMe controller may only retain basic command parsing functions, as well as support HMB functions. The command parsing function may be used to parse various types of transactions (e.g., memory read data, completion transactions, etc.) and commands (e.g., first instructions, second instructions, etc.).

Optionally, the processor is further configured to send a second read instruction to the host through a channel supported by the cxl.io protocol provided by the CXL controller, and a request channel supported by the cxl.cache protocol provided by the CXL controller when the second address indication data is received. The second address indicating data is address indicating data of a second instruction address, which is sent to the SSD device through a channel supported by the CXL.io protocol after the host responds to the data writing operation and writes the data writing instruction into a commit queue in the memory. The second read instruction carries an instruction address of a data read instruction indicated by the second address indication data. The second read instruction is used for the host to read a data write-in instruction according to the second instruction address, and the data write-in instruction is sent to the SSD device through a response channel supported by the CXL.cache protocol, wherein the data write-in instruction carries a data address of write-in data to be written in the flash memory medium in the memory.

The processor is further configured to initiate a memory read transaction to the host over a channel supported by the cxl.io protocol provided by the CXL controller. The memory read transaction carries the data address of the write data. The memory read transaction is used for a host to read the write-in data according to the data address, and initiates a completion transaction to the SSD device through a channel supported by the CXL.io protocol, wherein the completion transaction carries the write-in data;

the flash memory controller is also used to write the write data to the flash memory medium.

The processor is further configured to write completion status information of the data write instruction into a completion queue in the memory, initiate an interrupt transaction to the host through a channel supported by a cxl.io protocol provided by the CXL controller, the interrupt transaction being configured to consume the completion status information of the data write instruction in the completion queue by the host.

Optionally, the processor is further configured to send the first write instruction to the host through a request channel supported by a cxl.cache protocol provided by the CXL controller. The first write instruction carries completion status information of the data read instruction. The first write instruction is used for writing the completion status information of the data read instruction into the completion queue by the host.

Optionally, the processor is further configured to send a second write instruction to the host through a request channel supported by a cxl.cache protocol provided by the CXL controller. The second write instruction carries completion status information of the data write instruction. The second write instruction is used for the host to write the completion status information of the data write instruction into the completion queue.

Alternatively, the host and SSD device support HMB mechanisms. The processor is further configured to initiate a second memory write transaction to the host over a channel supported by the cxl.io protocol provided by the CXL controller. The second memory write transaction is used for enabling the host to store the corresponding relation between the PBA and the LBA of the first storage space in the flash memory medium. The LBA of the first storage space is the address of the second storage space corresponding to the first storage space. The second storage space is a storage space configured by the host for the HMB of the SSD device from the memory, and the data read instruction carries a target LBA of the target data.

The first reading instruction is further used for enabling the host to read the data reading instruction according to the first instruction address, determining a target PBA corresponding to the target LBA according to the corresponding relation between the PBA and the LBA, generating a target reading instruction carrying the target PBA, and sending the target reading instruction to the SSD device through a response channel supported by the CXL.cache protocol.

The flash memory controller is further configured to write the write data into the flash memory medium, determine a correspondence between the target first storage space and the target second storage space in the memory, and obtain and store a correspondence between the PBA and the LBA of the target first storage space. The target first storage space is a first storage space in the flash memory medium for storing the write data. The LBA of the target first storage space is the address of the target second storage space.

Optionally, the processor is further configured to send a first read instruction to the host through a request channel supported by a cxl.cache protocol provided by the CXL controller, when the first register of the SSD device writes Tail Doorbell and the first address indication data is received. Tail Doorbell and the first address indicate that the data is data carried by a third memory write transaction initiated by the host to the SSD device over a channel supported by the cxl.io protocol.

The processor is further configured to update Head DoorBell the completion queue in the second register of the SSD device if the fourth memory write transaction is received. The fourth memory write transaction is initiated by the host to the SSD device through the channel supported by the cxl.io protocol after consuming the completion status information of the data read instruction in the completion queue.

Optionally, the processor is further configured to send a second read instruction to the host through a request channel supported by a cxl.cache protocol provided by the CXL controller, when the first register of the SSD device writes Tail Doorbell and the second address indication data is received. Tail Doorbell and the second address indicate that the data is carried by a fifth memory write transaction initiated by the host to the SSD device over the channel supported by the cxl.io protocol.

The processor is further configured to update Head DoorBell the completion queue in the second register of the SSD device upon receiving the sixth memory write transaction. The sixth memory write transaction is initiated by the host to the SSD device through the channel supported by the cxl.io protocol after consuming the completion status information of the data write instruction in the completion queue.

It should be noted that, the explanation and implementation of the functions of each component in the SSD device may refer to the explanation and implementation of the related steps executed by the SSD device in the foregoing method-side embodiment, which is not described herein.

In the embodiment of the application, a host responds to data reading operation, a data reading instruction is written into a submission queue in a memory, and first address indication data is sent to SSD equipment through a channel supported by CXL.io protocol. And the SSD device sends a first reading instruction to the host through a request channel supported by CXL.cache protocol. And the host reads the data reading instruction according to the first instruction address, and sends a target reading instruction to the SSD device through a response channel supported by the CXL.cache protocol. The SSD device reads target data to be read indicated by a data reading instruction from a flash memory medium of the SSD device, and the SSD device initiates a first memory writing transaction to a host through a channel supported by CXL.io protocol so that the host writes the target data into a memory. The SSD device writes the completion state information of the data reading instruction into a completion queue in the memory, and initiates an interrupt transaction to the host through a channel supported by the CXL.io protocol, so that the host consumes the completion state information in the completion queue, and the host reads target data in the SSD device. In the technical scheme, as the SSD device can send the first reading instruction to the host through the request channel supported by the CXL.cache protocol, the host sends the target reading instruction to the SSD device through the response channel supported by the CXL.cache protocol, so as to read target data by the SSD. Therefore, compared with the scheme that the SSD device requests the target data read instruction by utilizing the channel supported by the CXL.io protocol/PCIE protocol, the time delay of the channel supported by the CXL.cache protocol for transmitting the transaction is lower than that of the channel supported by the CXL.io protocol/PCIE protocol, and the time delay of the data read process of the host and the SSD device is reduced.

Fig. 13 is a schematic structural diagram of a host according to an embodiment of the present application. As shown in fig. 4 and 13, the host includes: processor, memory and root node. The processor is connected with the SSD device and the memory through the root node. The root node includes a protocol multiplexer, an Input/Output (IO) controller, a cache controller, and a memory controller. The physical channel between the protocol multiplexer and the SSD device supports data communication of the CXL.cache protocol and the CXL.io protocol. Optionally, the IO controller may support PCIE protocols and cxl.io protocols. The protocol multiplexer of the host may refer to the protocol multiplexer of the SSD device.

The processor is used for responding to the data reading operation, writing a data reading instruction into a submitting queue in the memory, and sending first address indication data to the SSD device through a channel supported by the CXL.io protocol provided by the protocol multiplexer. The first address indication data indicates a first instruction address of the data read instruction. The first address indication data is used for a request channel supported by the SSD device through CXL.cache protocol, and a first read instruction is sent to the host. The first read instruction carries a first instruction address.

The memory controller is used for receiving a first reading instruction through a request channel supported by CXL.cache protocol provided by the protocol multiplexer.

The memory controller is further configured to read a data read instruction according to the first instruction address, and send a target read instruction to the SSD device through a response channel supported by the cxl.cache protocol provided by the protocol multiplexer. The target read instruction is used for enabling the SSD device to read target data indicated by the data read instruction from the flash memory medium, and a first memory write transaction is initiated to the host through a channel supported by the CXL.io protocol, wherein the first memory write transaction carries the target data.

The memory controller is further configured to receive a first memory write transaction through a channel supported by the cxl.io protocol provided by the protocol multiplexer.

The memory controller is also used for writing target data into the memory.

The processor is further configured to receive an interrupt transaction initiated by the SSD device to the host over a channel supported by the cxl.io protocol provided by the protocol multiplexer. The interrupt transaction is initiated by the SSD device writing completion status information for the data read instruction to a completion queue in memory, through a channel supported by the CXL.io protocol, to the host.

The processor is also configured to consume completion status information for the data read instruction in the completion queue.

In the embodiment of the application, the host responds to the data writing operation, writes a data writing instruction into a commit queue in the memory, and sends second address indication data to the SSD device through a channel supported by the CXL.io protocol. And the SSD device sends a second reading instruction to the host through a request channel supported by the CXL.cache protocol, so that the host reads the data writing instruction according to the second instruction address, and sends the data writing instruction to the SSD device through a response channel supported by the CXL.cache protocol. And the SSD device initiates a memory read transaction to the host through a channel supported by the CXL.io protocol, so that the host reads the write data according to the data address, and initiates a completion transaction to the SSD device through the channel supported by the CXL.io protocol. The SSD device writes the written data into the flash memory medium, writes the completion state information of the data writing instruction into a completion queue in the memory, and initiates an interrupt transaction to the host through a channel supported by the CXL.io protocol, so that the host consumes the completion state information in the completion queue, and the host is enabled to write the data into the SSD device. In the technical scheme, the SSD device can send the second reading instruction to the host through the request channel supported by the CXL.cache protocol, so that the host can send the data writing instruction to the SSD device through the response channel supported by the CXL.cache protocol, and the data writing instruction is used for reading the data writing instruction by the SSD device. Therefore, compared with the scheme that the SSD device uses the channel supported by the CXL.io protocol/PCIE protocol to request the data writing instruction, the time delay of the channel supported by the CXL.cache protocol to transmit the transaction is lower than that of the channel supported by the CXL.io protocol/PCIE protocol, and the time delay of the data writing process of the host and the SSD device is reduced.

Optionally, the processor is further configured to, in response to a data write operation, write a data write instruction to the commit queue, and send second address indication data to the SSD device over the channel supported by the cxl.io protocol provided by the protocol multiplexer. The second address indication data indicates a second instruction address of the data write instruction. The second address indicating data is used for a request channel supported by the SSD device through CXL.cache protocol, and a second reading instruction is sent to the host. The second read instruction carries a second instruction address, and the data write instruction carries a data address of write data to be written into the flash memory medium in the memory.

The memory controller is also used for receiving a second read instruction through a request channel supported by CXL.cache protocol.

The memory controller is also used for reading a data writing instruction according to the second instruction address, and sending the data writing instruction to the SSD device through a response channel supported by the CXL.cache protocol provided by the protocol multiplexer. The data writing instruction is used for enabling the SSD device to initiate a memory reading transaction to the host through a channel supported by the CXL.io protocol, and the memory reading transaction carries a data address for writing data.

The memory controller is further configured to receive a memory read transaction through a channel supported by the cxl.io protocol provided by the protocol multiplexer.

The memory controller is further configured to read the write data according to the data address, initiate a completion transaction to the SSD device through a channel supported by the cxl.io protocol provided by the protocol multiplexer, the completion transaction carrying the write data. The completion transaction is used for enabling the SSD device to write the writing data into the flash memory medium, writing the completion state information of the data writing instruction into a completion queue in the memory, and initiating an interrupt transaction to the host through a channel supported by the CXL.io protocol.

The processor is further configured to receive an interrupt transaction via a channel supported by the cxl.io protocol provided by the protocol multiplexer.

The processor is also configured to consume completion status information for the data write instruction in the completion queue.

Optionally, the memory controller is further configured to receive, through a request channel supported by the cxl.cache protocol provided by the protocol multiplexer, a first write instruction sent by the SSD device after initiating a first memory write transaction to the host, where the first write instruction carries completion status information of the data read instruction.

The memory controller is also configured to write completion status information of the data read instruction to a completion queue of the memory.

Optionally, the completion transaction is used for enabling the SSD device to write the write data into the flash memory medium, send a second write instruction to the host through a request channel supported by the cxl.cache protocol, and initiate an interrupt transaction to the host through a channel supported by the cxl.io protocol. The second write instruction carries completion status information of the data write instruction.

The memory controller is also used for receiving a second write instruction through a request channel supported by CXL.cache protocol provided by the protocol multiplexer.

The memory controller is also configured to write completion status information of the data write instruction to the completion queue.

Alternatively, the host and SSD device support HMB mechanisms. The host computer still includes: NVMe controller. The memory stores the corresponding relation between PBA and LBA of the first storage space in the flash memory medium of the SSD device. The LBA of the first storage space is the address of the second storage space corresponding to the first storage space. The second storage space is a storage space in the memory configured as HMB of the SSD device.

The NVMe controller is used for reading a data reading instruction according to the first instruction address, wherein the data reading instruction carries a target LBA of target data.

The NVMe controller is further used for determining a target PBA corresponding to the target LBA according to the corresponding relation between the PBA and the LBA and generating a target reading instruction carrying the target PBA.

The NVMe controller is also used for sending a target reading instruction to the SSD device through a response channel supported by CXL.cache protocol provided by the protocol multiplexer.

Optionally, the NVMe controller is further configured to configure the second storage space in the memory as HMB of the SSD device, and send an address of the second storage space to the SSD device.

The NVMe controller is also used for receiving a second memory write transaction initiated by the SSD device through a channel supported by the CXL.io protocol provided by the protocol multiplexer. The second memory write transaction carries the correspondence between the PBA and the LBA of the first storage space in the flash memory medium. The corresponding relation between PBA and LBA is: after the SSD device writes data into the flash memory medium and determines the corresponding relation between the first storage space and the second storage space of the written data, the obtained corresponding relation between the PBA and the LBA of the first storage space of the written data. The LBA of the first storage space is the address of the second storage space corresponding to the first storage space.

The NVMe controller is also used for storing the corresponding relation between the PBA and the LBA to the memory.

Optionally, the processor is further configured to initiate a third memory write transaction to the SSD device over the channel supported by the cxl.io protocol to write Tail Doorbell of the commit queue to the first register of the SSD device. The third memory write transaction carries the first address indication data and Tail Doorbell. The third memory write transaction is used for enabling the SSD device to write Tail Doorbell in the first register, and when the first address indication data is received through a channel supported by the CXL.io protocol, a first read instruction is sent to the host through a request channel supported by the CXL.cache protocol.

The processor is further configured to initiate a fourth memory write transaction to the SSD device over the channel supported by the cxl.io protocol after consuming the completion status information of the data read instruction in the completion queue. The fourth memory write transaction is for use by the SSD device to update Head DoorBell the completion queue in the second register.

Optionally, the processor is further configured to initiate a fifth memory write transaction to the SSD device over the channel supported by the cxl.io protocol to write Tail Doorbell of the commit queue to the first register of the SSD device. The fifth memory write transaction carries Tail Doorbell and second address indication data. The fifth memory write transaction is used for enabling the SSD device to write Tail Doorbell in the first register, and when the second address indication data is received through a channel supported by the CXL.io protocol, a second read instruction is sent to the host through a request channel supported by the CXL.cache protocol.

The processor is further configured to initiate a sixth memory write transaction to the SSD device over the channel supported by the cxl.io protocol after consuming the completion status information of the data write instruction in the completion queue. The sixth memory write transaction is for use by the SSD device to update Head DoorBell the completion queue in the second register.

It should be noted that, the explanation and implementation of the functions of each component in the host may refer to the explanation and implementation of the relevant steps executed by the host in the foregoing method-side embodiment, which is not repeated herein.

Referring to fig. 14, a flowchart of a data processing method according to an embodiment of the application is shown. The data processing method may be applied to an SSD device of a data processing system. The data processing system also includes a host, with which the SSD device communicates via a CXL.cache protocol and a CXL.io protocol. As shown in fig. 14, the data processing method includes:

Step 1401, in the case of receiving the first address indication data by calculating a channel supported by the interconnection standard-input-output protocol, sending a first read instruction to the host by calculating a request channel supported by the interconnection standard-cache protocol.

The first address indicating data is data of a first instruction address, which is sent to the SSD device through a channel supported by the CXL.io protocol after a data reading instruction is written into a commit queue in a memory by a host in response to a data reading operation. The first read instruction carries a first instruction address. The first reading instruction is used for enabling the host to read the data reading instruction according to the first instruction address, and the target reading instruction is sent to the SSD device through a response channel supported by the CXL.cache protocol. The target read instruction is used for indicating the SSD device to read target data to be read indicated by the data read instruction.

Step 1402, receiving a target read instruction by calculating a response channel supported by an interconnection standard-cache protocol.

Step 1403, the target data is read from its flash media.

Step 1404, initiating a first memory write transaction to the host by computing channels supported by the interconnect standard-input-output protocol. The first memory write transaction carries target data. The first memory write transaction is used for the host to write target data into the memory.

In step 1405, the completion status information of the data read instruction is written into the completion queue in the memory, and an interrupt transaction is initiated to the host through the channel supported by the computing interconnection standard-input-output protocol, where the interrupt transaction is used for the host to consume the completion status information in the completion queue.

In the embodiment of the application, as the SSD device can send the first reading instruction to the host through the request channel supported by the CXL.cache protocol, the host sends the target reading instruction to the SSD device through the response channel supported by the CXL.cache protocol, so as to read the target data by the SSD. Therefore, compared with the scheme that the SSD device requests the target data read instruction by utilizing the channel supported by the CXL.io protocol/PCIE protocol, the time delay of the channel supported by the CXL.cache protocol for transmitting the transaction is lower than that of the channel supported by the CXL.io protocol/PCIE protocol, and the time delay of the data read process of the host and the SSD device is reduced.

Optionally, writing completion status information of the data read instruction to a completion queue in the memory, including: and sending a first write instruction to the host through a request channel supported by CXL.cache protocol. The first write instruction carries completion status information. The first write instruction is used for the host to write the completion status information into a completion queue of the memory.

Alternatively, the host and SSD device support HMB mechanisms. The host computer stores the corresponding relation between the physical block address PBA and the logical block address LBA of the first storage space in the flash memory medium. The LBA of the first storage space is the address of the second storage space corresponding to the first storage space. The second storage space is storage space configured by the host from memory for HMB of the SSD device. The first reading instruction is further used for enabling the host to read the data reading instruction according to the first instruction address, determining a target PBA corresponding to the target LBA according to the corresponding relation between the PBA and the LBA, generating a target reading instruction carrying the target PBA, and sending the target reading instruction to the SSD device through a response channel supported by the CXL.cache protocol.

Optionally, the data processing method further comprises: the SSD device initiates a second memory write transaction to the host over a channel supported by the CXL.io protocol. The second memory write transaction carries the correspondence of the PBA and the LBA. The second memory write transaction is used for the host to store the corresponding relation between the PBA and the LBA to the memory.

Optionally, sending a first read instruction to the host through a request channel supported by the cxl.cache protocol includes: under the condition that the first register is written Tail Doorbell and the first address indication data is received, the SSD device sends a first read instruction to the host through a request channel supported by CXL.cache protocol. Wherein Tail Doorbell and the first address indicate that the data is a channel supported by the host through the cxl.io protocol, and initiate data carried in the third memory write transaction to the SSD device. The third memory write transaction is to write Tail Doorbell of the commit queue to the first register of the SSD device.

The data processing method further comprises the following steps: the SSD device updates Head DoorBell the completion queue in the second register upon receiving a fourth memory write transaction over a channel supported by the CXL.io protocol. The fourth memory write transaction is initiated by the host to the SSD device over the channel supported by the cxl.io protocol after consuming the completion status information in the completion queue.

Referring to fig. 15, a flowchart of a data processing method according to an embodiment of the application is shown. The data processing method may be applied to an SSD device of a data processing system. The data processing system also includes a host, with which the SSD device communicates via a CXL.cache protocol and a CXL.io protocol. As shown in fig. 15, the data processing method includes:

Step 1501, in the case that the second address indication data is received by calculating a channel supported by the interconnection standard-input-output protocol, a second read instruction is sent to the host by calculating a request channel supported by the interconnection standard-cache protocol.

The second address indicating data is address indicating data of a second instruction address, which is sent to the SSD device through a channel supported by the CXL.io protocol after the host responds to the data writing operation and writes the data writing instruction into a commit queue in the memory. The second read instruction is used for the host to read the data write instruction according to the second instruction address, and the data write instruction is sent to the SSD device through a response channel supported by the CXL.cache protocol. The data write command carries a data address in the memory of write data to be written to the flash memory medium.

Step 1502, a data write instruction is received by computing a response channel supported by an interconnection standard-cache protocol.

In step 1503, a memory read transaction is initiated to the host by computing channels supported by the interconnect standard-input-output protocol. The memory read transaction is used for the host to read the written data according to the data address, and initiates a completion transaction to the solid state disk device through a channel supported by the computing interconnection standard-input/output protocol, wherein the completion transaction carries the written data.

Step 1504, receiving a completion transaction by computing channels supported by an interconnect standard-input-output protocol.

Step 1505, writing the write data into the flash memory medium.

Step 1506, writing the completion status information of the data writing instruction into the completion queue in the memory, and initiating an interrupt transaction to the host by calculating the channel supported by the interconnection standard-input-output protocol. The interrupt transaction is used for the host to consume the completion status information of the data write instruction in the completion queue.

Optionally, writing completion status information of the data write instruction to a completion queue in the memory, including: and sending a second write instruction to the host through a request channel supported by CXL.cache protocol. The second write instruction carries completion status information of the data write instruction. The second write instruction is used for the host to write the completion status information of the data write instruction into the completion queue.

Alternatively, the host and SSD device support HMB mechanisms. The data processing method further comprises the following steps:

And initiating a second memory write transaction to the host through a channel supported by the CXL.io protocol. The second memory write transaction carries the correspondence between the PBA and the LBA of the first storage space in the flash memory medium. The second memory write transaction is used for the host to store the corresponding relation between the PBA and the LBA to the memory. The corresponding relation is used for the host to read the data from the flash memory medium according to the LBA of the data to be read.

Writing the writing data into the flash memory medium, writing the completion status information of the data writing instruction into a completion queue in the memory, comprising: and writing the written data into the flash memory medium, determining the corresponding relation between the target first storage space and the target second storage space in the memory, and obtaining and storing the corresponding relation between the PBA and the LBA of the target first storage space. The SSD device writes completion status information for the data write instruction to a completion queue in memory. The target first storage space is a first storage space in the flash memory medium for storing the write data. The LBA of the target first storage space is the address of the target second storage space.

Optionally, sending, through a request channel supported by the cxl.cache protocol, a second read instruction to the host, including: and under the condition that the first register is written Tail Doorbell and the second address indication data is received, sending a second read instruction to the host through a request channel supported by CXL.cache protocol. Tail Doorbell and the second address indicate that the data is a channel supported by the host through the cxl.io protocol, and initiate data carried by the fifth memory write transaction to the SSD device. The fifth memory write transaction is used to write Tail Doorbell of the commit queue to the first register of the SSD device.

The data processing method further comprises the following steps: the SSD device updates Head DoorBell the completion queue in the second register upon receiving a sixth memory write transaction over a channel supported by the CXL.io protocol. The sixth memory write transaction is initiated by the host to the SSD device through the channel supported by the cxl.io protocol after consuming the completion status information of the data write instruction in the completion queue.

Referring to fig. 16, a flowchart of a data processing method according to an embodiment of the application is shown. The data processing method may be applied to a data processing system host. The data processing system also includes an SSD device. The SSD device communicates with the host via CXL.cache protocol and CXL.io protocol. As shown in fig. 16, the data processing method includes:

and 1601, responding to a data reading operation, writing a data reading instruction into a commit queue in a memory, and sending first address indication data to the solid state disk device by calculating a channel supported by an interconnection standard-input-output protocol.

The first address indication data indicates a first instruction address of the data read instruction. The first address indication data is used for a request channel supported by the SSD device through CXL.cache protocol, and a first read instruction is sent to the host. The first read instruction carries a first instruction address.

Step 1602, a first read instruction is received by computing a request channel supported by an interconnect standard-cache protocol.

And step 1603, reading a data reading instruction according to the first instruction address, and sending a target reading instruction to the solid state disk device through calculating a response channel supported by the interconnection standard-cache protocol.

The target read instruction is used for enabling the SSD device to read target data indicated by the data read instruction from the flash memory medium of the SSD device, and a first memory write transaction is initiated to the host through a channel supported by the CXL.io protocol. The first memory write transaction carries target data.

Step 1604, a first memory write transaction is received by computing channels supported by an interconnect standard-input-output protocol.

Step 1605, writing the target data into the memory.

In step 1606, an interrupt transaction initiated by the solid state disk device to the host is received through a channel supported by the computing interconnection standard-input/output protocol. The interrupt transaction is initiated to the host by the solid state disk device writing the completion status information of the data read instruction into the completion queue in the memory and calculating a channel supported by the interconnection standard-input-output protocol.

Step 1607, consuming the completion status information of the data read instruction in the completion queue.

In the embodiment of the application, the SSD device can send the second reading instruction to the host through the request channel supported by the CXL.cache protocol, so that the host can send the data writing instruction to the SSD device through the response channel supported by the CXL.cache protocol, and the data writing instruction is used for reading the data writing instruction by the SSD device. Therefore, compared with the scheme that the SSD device uses the channel supported by the CXL.io protocol/PCIE protocol to request the data writing instruction, the time delay of the channel supported by the CXL.cache protocol to transmit the transaction is lower than that of the channel supported by the CXL.io protocol/PCIE protocol, and the time delay of the data writing process of the host and the SSD device is reduced.

Optionally, before receiving an interrupt transaction initiated by the SSD device to the host through a channel supported by the cxl.io protocol, the data processing method further includes:

receiving a first write instruction sent by SSD equipment after initiating a first memory write transaction to a host through a request channel supported by CXL.cache protocol, wherein the first write instruction carries the completion state information of a data read instruction;

and writing the completion status information of the data reading instruction into a completion queue of the memory.

Optionally, the host and SSD device support an HMB mechanism; the host computer stores the corresponding relation between the physical block address PBA and the logical block address LBA of the first storage space in the flash memory medium. The LBA of the first storage space is the address of the second storage space corresponding to the first storage space. The second storage space is storage space configured by the host from memory for HMB of the SSD device. According to the first instruction address, reading a data reading instruction, and sending a target reading instruction to SSD equipment through a response channel supported by CXL.cache protocol, wherein the method comprises the following steps:

Reading a data reading instruction according to the first instruction address, wherein the data reading instruction carries a target LBA of target data;

determining a target PBA corresponding to the target LBA according to the corresponding relation between the PBA and the LBA, and generating a target reading instruction carrying the target PBA;

And sending a target reading instruction to the SSD device through a response channel supported by the CXL.cache protocol.

Optionally, the data processing method further comprises:

Receiving a second memory write transaction initiated by the SSD device through a channel supported by the CXL.io protocol, wherein the second memory write transaction carries the corresponding relation between the PBA and the LBA;

And storing the corresponding relation between the PBA and the LBA to the memory. Wherein, the corresponding relation between PBA and LBA is: after the SSD device writes data into the flash memory medium and determines the corresponding relation between the first storage space and the second storage space of the written data, the obtained corresponding relation between the PBA and the LBA of the first storage space of the written data.

Optionally, sending the first address indication data to the SSD device via a channel supported by the cxl.io protocol, including: and initiating a third memory write transaction to the SSD device via a channel supported by the CXL.io protocol to write Tail Doorbell of the commit queue to the first register of the SSD device. The third memory write transaction carries the first address indication data and Tail Doorbell. The third memory write transaction is used for enabling the SSD device to write Tail Doorbell in the first register, and when the first address indication data is received through a channel supported by the CXL.io protocol, a first read instruction is sent to the host through a request channel supported by the CXL.cache protocol.

The data processing method further comprises the following steps: after consuming the completion status information of the data read instruction in the completion queue, a fourth memory write transaction is initiated to the SSD device over the channel supported by the cxl.io protocol. The fourth memory write transaction is for use by the SSD device to update Head DoorBell the completion queue in the second register.

Referring to fig. 17, a flowchart of a data processing method according to an embodiment of the application is shown. The data processing method may be applied to a data processing system host. The data processing system also includes an SSD device. The SSD device communicates with the host via CXL.cache protocol and CXL.io protocol. As shown in fig. 17, the data processing method includes:

And 1701, responding to the data writing operation, writing a data writing instruction into a commit queue, and sending second address indicating data to the solid state disk device through calculating a channel supported by an interconnection standard-input-output protocol.

The second address indication data indicates a second instruction address of the data write instruction. The second address indicating data is used for a request channel supported by the SSD device through CXL.cache protocol, and a second reading instruction is sent to the host. The second read instruction carries a second instruction address. The data write command carries a data address in the memory of write data to be written to the flash memory medium.

Step 1702, receiving a second read instruction by computing a request channel supported by an interconnect standard-cache protocol.

And 1703, reading a data writing instruction according to the second instruction address, and sending the data writing instruction to the solid state disk device through calculating a response channel supported by the interconnection standard-cache protocol. The data writing instruction is used for enabling the solid state disk device to initiate a memory reading transaction to the host through a channel supported by the computing interconnection standard-input-output protocol, and the memory reading transaction carries a data address of writing data.

Step 1704, receiving a memory read transaction by computing a channel supported by an interconnect standard-input-output protocol.

And 1705, reading the written data according to the data address, and initiating a completion transaction to the solid state disk device through a channel supported by the computing interconnection standard-input/output protocol.

The completion transaction carries the write data. The completion transaction is used for enabling the SSD device to write the writing data into the flash memory medium, writing the completion state information of the data writing instruction into a completion queue in the memory, and initiating an interrupt transaction to the host through a channel supported by the CXL.io protocol;

Step 1706, receive an interrupt transaction by computing a channel supported by an interconnect standard-input-output protocol.

Step 1707, consuming the completion status information of the data writing instruction in the completion queue.

Optionally, the completion transaction is used for enabling the SSD device to write the write data into the flash memory medium, send a second write instruction to the host through a request channel supported by the cxl.cache protocol, and initiate an interrupt transaction to the host through a channel supported by the cxl.io protocol. The second write instruction carries completion status information of the data write instruction. The data processing method further comprises the following steps:

receiving a second write instruction through a request channel supported by CXL.cache protocol;

and writing the completion state information of the data writing instruction into a completion queue.

Sending second address indication data to the SSD device through a channel supported by CXL.io protocol, including: a fifth memory write transaction is initiated to the SSD device over the channel supported by the cxl.io protocol to write Tail Doorbell of the commit queue to the first register of the SSD device. The fifth memory write transaction carries Tail Doorbell and second address indication data. The fifth memory write transaction is used for enabling the SSD device to write Tail Doorbell in the first register, and when the second address indication data is received through a channel supported by the CXL.io protocol, a second read instruction is sent to the host through a request channel supported by the CXL.cache protocol.

The data processing method further comprises the following steps: after the completion status information of the data write instruction in the completion queue is consumed, a sixth memory write transaction is initiated to the SSD device through a channel supported by the cxl.io protocol. The sixth memory write transaction is for use by the SSD device to update Head DoorBell the completion queue in the second register.

Alternatively, the host and SSD device support HMB mechanisms. The data processing method further comprises the following steps: configuring a second storage space in the memory as HMB of the SSD device, and sending an address of the second storage space to the SSD device;

and storing the corresponding relation between the PBA and the LBA to the memory under the condition that the second memory write transaction sent by the SSD device is received through a channel supported by the CXL.io protocol. The second memory write transaction carries the correspondence between the PBA and the LBA of the first storage space in the flash memory medium.

Optionally, as shown in fig. 18, an embodiment of the present application further provides an electronic device. The electronic device 1800 includes a processor 1801, a memory 1802, and a program or instructions stored in the memory 1802 and executable on the processor 1801, where the program or instructions when executed by the processor 1801 implement the processes of the foregoing data processing method embodiments, and achieve the same technical effects, and are not repeated herein.

It should be noted that, the functions of each component in the electronic device 1800 in the embodiment of the present application may refer to the functions of each corresponding portion in the electronic device 1800 provided in the foregoing embodiment, and are not described herein.

The embodiment of the application also provides a readable storage medium, on which a program or an instruction is stored, which when executed by a processor, implements each process of the above-mentioned data processing method embodiment, and can achieve the same technical effects, and in order to avoid repetition, the description is omitted here.

Wherein the processor is a processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium such as a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and the like.

The embodiment of the application further provides a chip, which comprises a processor and a communication interface, wherein the communication interface is coupled with the processor, and the processor is used for running programs or instructions to realize the processes of the data processing method embodiment, and can achieve the same technical effects, so that repetition is avoided, and the description is omitted here.

It should be understood that the chips referred to in the embodiments of the present application may also be referred to as system-on-chip chips, chip systems, or system-on-chip chips, etc.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present application.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.

Claims

1. A data processing method, applied to a data processing system, the data processing system comprising: the system comprises solid state disk equipment and a host, wherein the solid state disk equipment and the host are communicated through a computing interconnection standard-cache protocol and a computing interconnection standard-input-output protocol; the method comprises the following steps:

the host writes the target data into the memory;

the host consumes the completion status information in the completion queue.

2. The method of claim 1, wherein the solid state disk device writing completion status information of the data read instruction to a completion queue in the memory comprises:

The solid state disk device sends a first write instruction to the host through a request channel supported by a computing interconnection standard-cache protocol, wherein the first write instruction carries the completion state information;

and the host writes the completion status information into the completion queue of the memory.

3. The method of claim 1 or 2, wherein the host and the solid state disk device support a host memory buffer mechanism; the host computer stores the corresponding relation between the physical block address and the logical block address of a first storage space in the flash memory medium, wherein the logical block address of the first storage space is the address of a second storage space corresponding to the first storage space, and the second storage space is a storage space configured by the host computer from the memory for a host memory buffer of the solid state disk device; the host reads the data reading instruction according to the first instruction address, and sends a target reading instruction to the solid state disk device by calculating a response channel supported by an interconnection standard-cache protocol, wherein the method comprises the following steps:

The host reads the data reading instruction according to the first instruction address, wherein the data reading instruction carries a target logic block address of the target data;

the host determines a target physical block address corresponding to the target logical block address according to the corresponding relation between the physical block address and the logical block address, and generates the target reading instruction carrying the target physical block address;

And the host sends the target reading instruction to the solid state disk equipment through a response channel supported by a computing interconnection standard-cache protocol.

4. A method according to claim 3, characterized in that the method further comprises:

The solid state disk equipment initiates a second memory write transaction to the host through a channel supported by a computing interconnection standard-input-output protocol, wherein the second memory write transaction carries the corresponding relation between a physical block address and a logical block address;

The host stores the corresponding relation between the physical block address and the logical block address into the memory, wherein the corresponding relation between the physical block address and the logical block address is as follows: and after the solid state disk device writes data into the flash memory medium and determines the corresponding relation between the first storage space and the second storage space of the written data, the obtained corresponding relation between the physical block address and the logical block address of the first storage space of the written data.

5. The method of claim 1, wherein the sending the first address indication data to the solid state disk device via the channel supported by the computing interconnect standard-input-output protocol comprises: the host initiates a third memory write transaction to the solid state disk device through a channel supported by a computing interconnection standard-input-output protocol so as to write a tail doorbell of the commit queue into a first register of the solid state disk device, wherein the third memory write transaction carries the first address indication data and the tail doorbell;

The solid state disk device sends a first reading instruction to the host through a request channel supported by a computing interconnection standard-cache protocol, and the method comprises the following steps: the solid state disk device writes the tail doorbell in the first register, and sends a first reading instruction to the host through a request channel supported by a computing interconnection standard-cache protocol under the condition that the first address indication data is received;

the method further comprises the steps of:

After the host consumes the completion state information in the completion queue, initiating a fourth memory write transaction to the solid state disk device through a channel supported by a computing interconnection standard-input-output protocol;

And the solid state disk equipment updates the head doorbell of the completion queue in the second register.

6. A data processing method, applied to a data processing system, the data processing system comprising: the system comprises solid state disk equipment and a host, wherein the solid state disk equipment and the host are communicated through a computing interconnection standard-cache protocol and a computing interconnection standard-input-output protocol; the method comprises the following steps:

7. The method of claim 6, wherein writing completion status information of the data write instruction to a completion queue in the memory comprises:

the solid state disk device sends a second write instruction to the host through a request channel supported by a computing interconnection standard-cache protocol, wherein the second write instruction carries the completion state information of the data write instruction;

and the host writes the completion status information of the data writing instruction into the completion queue.

8. The method of claim 6 or 7, wherein the host and the solid state disk device support a host memory buffer mechanism; the method further comprises the steps of:

The host configures a second storage space in the memory as a host memory buffer of the solid state disk device, and sends an address of the second storage space to the solid state disk device;

The solid state disk equipment initiates a second memory write transaction to the host through a channel supported by a computing interconnection standard-input-output protocol, wherein the second memory write transaction carries the corresponding relation between a physical block address and a logical block address of a first storage space in the flash memory medium;

The host stores the corresponding relation between the physical block address and the logical block address into the memory, wherein the corresponding relation is used for the host to read data from the flash memory medium according to the logical block address of the data to be read;

the solid state disk device writes the writing data into the flash memory medium, writes the completion status information of the data writing instruction into a completion queue in the memory, and includes:

The solid state disk device writes the writing data into the flash memory medium, and determines the corresponding relation between a target first storage space and a target second storage space in the memory, so as to obtain and store the corresponding relation between a physical block address and a logical block address of the target first storage space, wherein the target first storage space is the first storage space storing the writing data in the flash memory medium; the logical block address of the target first storage space is the address of the target second storage space;

and the solid state disk device writes the completion state information of the data writing instruction into a completion queue in the memory.

9. The method of claim 6, wherein the sending the second address indication data to the solid state disk device via the channel supported by the computing interconnect standard-input-output protocol comprises:

The host initiates a fifth memory write transaction to the solid state disk device through a channel supported by a computing interconnection standard-input-output protocol so as to write a tail doorbell of the commit queue into a first register of the solid state disk device, wherein the fifth memory write transaction carries the second address indication data and the tail doorbell;

The solid state disk device sends a second reading instruction to the host through a request channel supported by a computing interconnection standard-cache protocol, and the method comprises the following steps: the solid state disk device sends a second reading instruction to the host through a request channel supported by a computing interconnection standard-cache protocol under the condition that the first register writes the tail doorbell and the second address indication data is received;

the method further comprises the steps of:

after consuming the completion state information of the data writing instruction in the completion queue, the host initiates a sixth memory writing transaction to the solid state disk device by calculating a channel supported by an interconnection standard-input-output protocol;

10. A solid state disk device, characterized in that the solid state disk device comprises: the system comprises a solid state disk control chip and a flash memory medium, wherein the solid state disk control chip comprises a computing interconnection standard controller, a processor and a flash memory controller; the physical channel between the computing interconnection standard controller and the host supports data communication of the computing interconnection standard-cache protocol and the computing interconnection standard-input-output protocol;

11. The solid state disk device of claim 10 wherein,

The processor is further configured to send, when receiving second address instruction data through a channel supported by a computing interconnection standard-input/output protocol provided by a computing interconnection standard controller, a second read instruction to the host through a request channel supported by the computing interconnection standard-cache protocol provided by the computing interconnection standard controller, where the second address instruction data is data address of a second instruction address indicating the data write instruction sent to the solid state disk device through a channel supported by the computing interconnection standard-input/output protocol after the host writes the data write instruction to a commit queue in a memory in response to a data write operation, and send the data write instruction to the solid state disk device through a response channel supported by the computing interconnection standard-cache protocol, where the second read instruction is used for the host to read the data write instruction according to the second instruction address, and the data write instruction carries a data address of write data to be written into a flash memory medium in the memory;

The processor is further configured to initiate a memory read transaction to the host through a channel supported by a computing interconnection standard-input/output protocol provided by the computing interconnection standard controller, where the memory read transaction is used for the host to read the write data according to the data address, and initiate a completion transaction to the solid state disk device through the channel supported by the computing interconnection standard-input/output protocol, where the completion transaction carries the write data;

the flash memory controller is further configured to write the write data to the flash memory medium;

The processor is further configured to write completion status information of the data write instruction into a completion queue in the memory, and initiate an interrupt transaction to the host through a channel supported by a computing interconnect standard-input-output protocol provided by the computing interconnect standard controller, where the interrupt transaction is used for the host to consume the completion status information of the data write instruction in the completion queue.

12. The solid state disk device of claim 10 or 11,

The processor is further configured to send a first write instruction to the host through a request channel supported by a computation interconnect standard-cache protocol provided by a computation interconnect standard controller, where the first write instruction is used for the host to write completion status information of the data read instruction into the completion queue.

13. The solid state disk device of claim 11 wherein,

The processor is further configured to send a second write instruction to the host through a request channel supported by a computation interconnect standard-cache protocol provided by the computation interconnect standard controller, where the second write instruction is used for the host to write completion status information of the data write instruction into the completion queue.

14. The solid state disk device of claim 10 or 11, wherein the host and the solid state disk device support a host memory buffer mechanism;

The processor is further configured to initiate a second memory write transaction to the host through a channel supported by a computing interconnection standard-input/output protocol provided by the computing interconnection standard controller, where the second memory write transaction is used for the host to store, to the memory, a correspondence between a physical block address and a logical block address of a first storage space in the flash memory medium, where the logical block address of the first storage space is an address of a second storage space corresponding to the first storage space, where the second storage space is a storage space configured by the host from the memory for a host memory buffer of the solid state hard disk device, and the data read instruction carries a target logical block address of the target data,

The first reading instruction is further used for the host to read the data reading instruction according to the first instruction address, a target physical block address corresponding to the target logical block address is determined according to the corresponding relation between the physical block address and the logical block address, the target reading instruction carrying the target physical block address is generated, and the target reading instruction is sent to the solid state disk device through a response channel supported by a calculation interconnection standard-cache protocol;

The flash memory controller is further configured to write the write data into the flash memory medium, determine a correspondence between a target first storage space and a target second storage space in the memory, and obtain and store a correspondence between a physical block address and a logical block address of the target first storage space, where the target first storage space is a first storage space in the flash memory medium in which the write data is stored; and the logical block address of the target first storage space is the address of the target second storage space.

15. The solid state disk device of claim 10 or 11,

The processor is further configured to send, when the tail doorbell is written in the first register of the solid state disk device and the first address indication data is received, the first read instruction to the host through a request channel supported by a computation interconnection standard-cache protocol provided by a computation interconnection standard controller, where the tail doorbell and the first address indication data are data carried by a third memory write transaction initiated by the host through a channel supported by the computation interconnection standard-input-output protocol;

And the processor is further configured to update a head doorbell of the completion queue in the second register of the solid state disk device under the condition that a fourth memory write transaction is received, where the fourth memory write transaction is initiated to the solid state disk device by the host after consuming the completion status information of the data read instruction in the completion queue through a channel supported by a computing interconnection standard-input-output protocol.

16. The solid state disk device of claim 11 wherein,

The processor is further configured to send, when the first register of the solid state disk device writes a tail doorbell and receives the second address indication data, the second read instruction to the host through a request channel supported by a computation interconnection standard-cache protocol provided by a computation interconnection standard controller, where the tail doorbell and the second address indication data are data carried by a fifth memory write transaction initiated by the host through a channel supported by the computation interconnection standard-input/output protocol;

And the processor is further configured to update a head doorbell of the completion queue in the second register of the solid state disk device under the condition that a sixth memory write transaction is received, where the sixth memory write transaction is initiated to the solid state disk device by the host after consuming the completion status information of the data write instruction in the completion queue through a channel supported by a computing interconnection standard-input-output protocol.

17. A host, the host comprising: the device comprises a processor, a memory and a root node, wherein the processor is connected with solid state disk equipment and the memory through the root node; the root node comprises a protocol multiplexer, an input-output controller, a cache memory controller and a memory controller; the physical channel between the protocol multiplexer and the solid state disk device supports data communication of a computing interconnection standard-cache protocol and a computing interconnection standard-input-output protocol;

18. The host machine of claim 17, wherein the host machine comprises a host computer,

The processor is further configured to write a data write instruction to the commit queue in response to a data write operation, send second address indication data to the solid-state disk device through a channel supported by a computation interconnect standard-input-output protocol provided by the protocol multiplexer, where the second address indication data indicates a second instruction address of the data write instruction, where the second address indication data is used for the solid-state disk device to send a second read instruction to the host through a request channel supported by the computation interconnect standard-cache protocol, where the second read instruction carries the second instruction address, and where the data write instruction carries a data address of write data to be written to a flash memory medium in the memory;

The memory controller is further configured to receive the second read instruction by calculating a request channel supported by an interconnection standard-cache protocol;

The memory controller is further configured to read the data writing instruction according to the second instruction address, and send the data writing instruction to the solid state disk device through a response channel supported by a computing interconnection standard-cache protocol provided by the protocol multiplexer; the data writing instruction is used for the solid state disk device to initiate a memory reading transaction to the host through a channel supported by a computing interconnection standard-input/output protocol, and the memory reading transaction carries a data address of the writing data;

The memory controller is further configured to receive the memory read transaction through a channel supported by a computational interconnect standard-input-output protocol provided by the protocol multiplexer;

The memory controller is further configured to read the write data according to the data address, initiate a completion transaction to the solid state disk device through a channel supported by a computing interconnection standard-input/output protocol provided by the protocol multiplexer, where the completion transaction carries the write data, and the completion transaction is used for the solid state disk device to write the write data into the flash memory medium, write completion status information of the data write instruction into a completion queue in the memory, and initiate an interrupt transaction to the host through the channel supported by the computing interconnection standard-input/output protocol;

The processor is further configured to receive the interrupt transaction through a channel supported by a computational interconnect standard-input-output protocol provided by the protocol multiplexer;

The processor is further configured to consume completion status information of the data write instruction in the completion queue.

19. The host machine of claim 17 or 18, wherein the host machine comprises a host computer,

The memory controller is further configured to receive, through a request channel supported by a computing interconnection standard-cache protocol provided by the protocol multiplexer, a first write instruction sent by the solid-state disk device after initiating a first memory write transaction to the host, where the first write instruction carries completion status information of the data read instruction;

The memory controller is further configured to write completion status information of the data read instruction to the completion queue of the memory.

20. The host of claim 18, wherein the completion transaction is configured to allow the solid state disk device to write the write data to the flash memory medium, send a second write instruction to the host via a request channel supported by a compute interconnect standard-cache protocol, and initiate an interrupt transaction to the host via a channel supported by a compute interconnect standard-input-output protocol, the second write instruction carrying completion status information of the data write instruction;

the memory controller is further configured to receive the second write instruction through a request channel supported by a computation interconnect standard-cache protocol provided by the protocol multiplexer;

The memory controller is further configured to write completion status information of the data write instruction into the completion queue.

21. The host of claim 17 or 18, wherein the host and the solid state disk device support a host memory buffer mechanism; the host further comprises: a nonvolatile memory host controller interface controller, wherein the memory stores the corresponding relation between the physical block address and the logical block address of a first storage space in a flash memory medium of the solid state disk device, the logical block address of the first storage space is the address of a second storage space corresponding to the first storage space, and the second storage space is a storage space configured as a host memory buffer of the solid state disk device in the memory;

The non-volatile memory host controller interface controller is configured to read the data read instruction according to the first instruction address, where the data read instruction carries a target logical block address of the target data;

the non-volatile memory host controller interface controller is further configured to determine a target physical block address corresponding to the target logical block address according to the correspondence between physical block addresses and logical block addresses, and generate the target read instruction carrying the target physical block address;

the nonvolatile memory host controller interface controller is further configured to send the target read instruction to the solid state disk device through a response channel supported by a computing interconnection standard-cache protocol provided by the protocol multiplexer.

22. The host machine of claim 21, wherein the host machine comprises a host computer,

The non-volatile memory host controller interface controller is further configured to configure a second storage space in the memory as a host memory buffer of the solid state disk device, and send an address of the second storage space to the solid state disk device;

The interface controller of the non-volatile memory host controller is further configured to receive a second memory write transaction initiated by the solid state disk device through a channel supported by a computing interconnection standard-input/output protocol provided by the protocol multiplexer, where the second memory write transaction carries a correspondence between a physical block address and a logical block address of the first storage space in the flash memory medium, and the correspondence between the physical block address and the logical block address is: after the solid state disk device writes data into the flash memory medium and determines the corresponding relation between the first storage space and the second storage space of the written data, the obtained corresponding relation between the physical block address and the logical block address of the first storage space of the written data, wherein the logical block address of the first storage space is the address of the second storage space corresponding to the first storage space;

The non-volatile memory host controller interface controller is further configured to store the correspondence between physical block addresses and logical block addresses to the memory.

23. The host machine of claim 17 or 18, wherein the host machine comprises a host computer,

The processor is further configured to initiate a third memory write transaction to the solid state disk device through a channel supported by a computing interconnection standard-input/output protocol, so as to write a tail doorbell of the commit queue to a first register of the solid state disk device, where the third memory write transaction carries the first address indication data and the tail doorbell, the third memory write transaction is used for the solid state disk device to write the tail doorbell in the first register, and send the first read instruction to the host through a request channel supported by the computing interconnection standard-cache protocol when the first address indication data is received through the channel supported by the computing interconnection standard-input/output protocol;

And the processor is further configured to initiate a fourth memory write transaction to the solid state disk device through a channel supported by a computing interconnection standard-input-output protocol after the consuming of the completion status information of the data read instruction in the completion queue, where the fourth memory write transaction is used for the solid state disk device to update a head doorbell of the completion queue in a second register.

24. The host machine of claim 18, wherein the host machine comprises,

The processor is further configured to initiate a fifth memory write transaction to the solid state disk device through a channel supported by a computing interconnection standard-input/output protocol, so as to write a tail doorbell of the commit queue to a first register of the solid state disk device, where the fifth memory write transaction carries the tail doorbell and the second address indication data, where the fifth memory write transaction is used for the solid state disk device to write the tail doorbell in the first register, and send the second read instruction to the host through a request channel supported by the computing interconnection standard-cache protocol when the second address indication data is received through the channel supported by the computing interconnection standard-input/output protocol;

And the processor is further used for initiating a sixth memory write transaction to the solid state disk device through a channel supported by a computing interconnection standard-input-output protocol after consuming the completion state information of the data write instruction in the completion queue, wherein the sixth memory write transaction is used for updating a head doorbell of the completion queue in a second register by the solid state disk device.

25. The data processing method is characterized by being applied to solid state disk equipment of a data processing system, wherein the data processing system further comprises a host, and the solid state disk equipment is communicated with the host through a computing interconnection standard-cache protocol and a computing interconnection standard-input-output protocol; the method comprises the following steps:

reading the target data from the flash memory medium;

26. The data processing method is characterized by being applied to solid state disk equipment of a data processing system, wherein the data processing system further comprises a host, and the solid state disk equipment is communicated with the host through a computing interconnection standard-cache protocol and a computing interconnection standard-input-output protocol; the method comprises the following steps:

writing the write data to the flash memory medium;

27. The data processing method is characterized by being applied to a host of a data processing system, wherein the data processing system further comprises solid state disk equipment, and the solid state disk equipment is communicated with the host through a computing interconnection standard-cache protocol and a computing interconnection standard-input-output protocol; the method comprises the following steps:

writing the target data into the memory;

28. The data processing method is characterized by being applied to a host of a data processing system, wherein the data processing system further comprises solid state disk equipment, and the solid state disk equipment is communicated with the host through a computing interconnection standard-cache protocol and a computing interconnection standard-input-output protocol; the method comprises the following steps:

29. A readable storage medium having stored thereon a program or instructions which when executed by a processor performs the method of any one of claims 1 to 5, or the method of any one of claims 6 to 9, or the method of claim 25, or the method of claim 26, or the method of claim 27, or the method of claim 28.

30. A computer program product comprising computer program/instructions which, when executed by a processor, implement the method of any one of claims 1 to 5, or the method of any one of claims 6 to 9, or the method of claim 25, or the method of claim 26, or the method of claim 27, or the method of claim 28.