CN114415985A - Stored data processing unit based on numerical control separation architecture - Google Patents

Abstract

The invention discloses a storage data processing unit based on a numerical control separation architecture, which comprises: a processor and a hardware acceleration engine; the hardware acceleration engine is used for realizing protocol unloading operation and data processing operation of a data plane; the processor is used for realizing software processing operation of the control plane and processing operation except data processing operation in the data plane; therefore, in the scheme, the storage data processing unit can distinguish the data stream and the control stream from hardware based on a numerical control separation architecture, so that the mutual influence between the control stream and the data stream is avoided, and the influence on the storage performance is reduced; in addition, in the scheme, a hardware acceleration engine special for executing data processing operation is also independent in the storage data processing unit, so that the data processing operation is realized more efficiently, and the processing performance of the storage data processing unit in the data storage field is improved.

Description

A Storage Data Processing Unit Based on Numerical Control Separation Architecture

technical field

The invention relates to the technical field of data storage, and more particularly, to a storage data processing unit based on a numerical control separation architecture.

Background technique

The current market demand drives the global storage data volume to surge at the level of ZB (Zettabyte, one trillion gigabytes). The bandwidth has also been significantly improved, and customers have also put forward higher requirements for the I/O (Input/Output) performance of the storage system, such as higher bandwidth and IOPS (Input/Output Operations Per Second, the number of reads and writes per second). ), lower latency, etc. However, the development of semiconductor processes in the post-Moore era has slowed down, and the single computing power stagflation (52%->3.5%) has brought huge performance improvement challenges to the design of storage systems.

The current mainstream storage system framework is based on the CPU computing-centric (Compute Centric) architecture, which is suitable for traditional storage device usage scenarios. With the CPU as the center, the front-end interface cards (such as network cards, FC (FibreChannel, optical fiber) Cards), graphics processing unit (GPU), memory and other computing, storage, and communication devices are mounted under the CPU. All calculations and controls are initiated by the CPU, and the CPU plays a key role in the control of the core. However, with the advent of the post-Moore era, the single-core computing power of the CPU has stagnant, making the CPU a bottleneck for improving the performance of storage systems.

Therefore, how to improve the processing performance of the processor in the field of data storage is a problem to be solved by those skilled in the art.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a storage data processing unit based on the numerical control separation architecture, so as to improve the processing performance of the processor in the field of data storage.

In order to achieve the above object, the present invention provides a storage data processing unit based on a numerical control separation architecture, comprising:

Processor and hardware acceleration engine;

The hardware acceleration engine is used to implement protocol offloading operations and data processing operations of the data plane; the processor is used to implement software processing operations of the control plane and processing operations other than the data processing operations in the data plane .

Wherein, the hardware acceleration engine includes a protocol acceleration engine, and the protocol acceleration engine is used to implement protocol processing operations and hardware acceleration operations of data consistency.

Wherein, the protocol acceleration engine is specifically used to implement TCP protocol processing operations and NVMe over Fabric protocol processing operations.

Wherein, the hardware acceleration engine includes a data stream acceleration engine, and the data stream acceleration engine is used to implement at least one of data handling operations, data encoding operations, data transcoding operations, memory comparison operations, data query operations, and data insertion operations. one.

Wherein, the processor is an ARM processor.

The software processing operations implemented by the ARM processor include: at least one of storage configuration service operations, chassis management operations, log collection operations, exception handling operations, firmware upgrade operations, user security operations, and production diagnostic operations.

The processing operations implemented by the ARM processor in the data plane include: at least one of NVMe oF Target management operations, IO multipath management operations, cache management operations, Disk management operations, and protocol processing operations.

Wherein, the processor implements software processing operations of the control plane and processing operations other than the data processing operations in the data plane through different processor cores.

Wherein, the user state of the storage data processing unit includes the data plane, the control plane and the common module.

Wherein, the common module is used to implement: task scheduling management operation, memory management operation and driver management operation.

It can be seen from the above solutions that a storage data processing unit based on a numerically controlled separation architecture provided by an embodiment of the present invention includes: a processor and a hardware acceleration engine; wherein, the hardware acceleration engine is used to implement protocol offloading operations and data processing of the data plane operation; the processor is used to realize the software processing operations of the control plane and the processing operations other than the data processing operations in the data plane; it can be seen that in this solution, the storage data processing unit can perform data flow and The control flow is distinguished, so as to avoid the mutual influence between the control flow and the data flow, thereby reducing the impact on the storage performance; in addition, in the storage data processing unit, this solution also separates a hardware acceleration engine dedicated to executing data processing operations. , so as to realize the data processing operation more efficiently and improve the processing performance of the storage data processing unit in the data storage field.

Description of drawings

In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that are used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative efforts.

FIG. 1 is a storage data processing unit based on a numerical control separation architecture disclosed in an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a system disclosed in an embodiment of the present invention;

3a is a schematic diagram of a control flow of a control plane disclosed in an embodiment of the present invention;

FIG. 3b is a schematic diagram of a data flow of a data plane disclosed in an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The embodiment of the present invention discloses a storage data processing unit based on a numerical control separation architecture, so as to improve the processing performance of a processor in the field of data storage.

Referring to FIG. 1 , a storage data processing unit based on a numerically controlled separation architecture provided by an embodiment of the present invention includes: a processor 11 and a hardware acceleration engine 12;

The hardware acceleration engine 12 is used to implement protocol offloading operations and data processing operations on the data plane; the processor 11 is used to implement software processing operations on the control plane and processing operations other than data processing operations on the data plane.

The storage data processing unit in this solution is SPU (Storage Processing Unit), which is applied in a new data-centric storage architecture. The SPU includes a processor and a hardware acceleration engine, and adopts a numerical control separation architecture design. Implementing a variety of I/O hardware acceleration technologies, combined with CPU processing software control flow, GPU processing AI (Artificial Intelligence) and graphics operations, and SSD processing storage, it can achieve sustainable linear growth in the performance of the storage system.

Specifically, in this embodiment, since the ARM processor is used more in the CPU environment, the application is relatively mature, and it has the advantages of low power consumption, etc., in this solution, the ARM processor can be used to implement the software of the control plane Processing operations, and processing operations other than data processing operations in the data plane, but this solution is not limited to the use of ARM processors, and other processors can also be selected according to requirements in practical applications; hardware acceleration engine refers to the storage data processing unit the IP core in.

In this embodiment, the hardware acceleration engine is hardware specially used for data acceleration processing provided for storage application scenarios. When a traditional CPU performs data processing operations, the core of the CPU must be used for processing, and the data processing efficiency is low. In this solution, after the hardware acceleration engine is independent, specialized hardware can be used to implement data processing operations more efficiently, thereby improving the processing performance of the storage data processing unit in the data storage field.

Further, in the traditional solution, both the data flow and the control flow are performed by the CPU to perform related operations, that is, the CPU core needs to perform operations on the data flow and the control flow at the same time. If there is a hardware failure, there will be a problem with the control flow. The core that will affect the CPU cannot process the data stream normally, thereby affecting the overall storage performance, and in this application, the storage data processing unit is mainly based on the numerical control separation architecture, and the processor implements the software processing operations of the control plane through different processor cores, and Processing operations other than data processing operations in the data plane, this numerical control separation method can distinguish the data flow and control flow from the hardware, so as to avoid the mutual influence between the control flow and the data flow, thereby reducing the storage performance. Impact.

From the above, it can be seen that in this solution, the storage data processing unit can distinguish the data flow and the control flow from the hardware based on the numerical control separation architecture, so as to avoid the mutual influence between the control flow and the data flow, thereby reducing the impact on the storage performance. In order to optimize the internal I/O performance of the storage data processing unit to the greatest extent, this solution also separates a hardware acceleration engine specially used to perform data processing operations in the storage data processing unit, so as to realize data processing operations more efficiently. With a large number of IO processing requirements in the storage field, the separation architecture and hardware acceleration engine can realize the rapid flow of data, support parallel processing of multiple concurrent I/O, improve the processing performance of the storage data processing unit in the data storage field, and improve the I/O O processing efficiency, saving equipment cost.

In this embodiment, the hardware acceleration engine includes a protocol acceleration engine, which is used to implement protocol processing operations and hardware acceleration operations of data consistency; wherein, the protocol acceleration engine is specifically used to implement TCP protocol processing operations and NVMe The over Fabric protocol handles operations.

It should be noted that the network card itself has communication capabilities. In this embodiment, a protocol acceleration engine is set in the network card, and the protocol acceleration engine supports protocol offloading features, such as implementing the TCP (Transmission Control Protocol, Transmission Control Protocol) protocol. Offload operation, NVMe over Fabric protocol (Network Efficient Storage Protocol) offload operation, and data consistency T10-DIF (Data Integrity Field, Data Consistency Protection) operation hardware offload, that is to say: this application uses software in the traditional solution to do For processing operations, use hardware (protocol acceleration engine) instead to save software computing resources and improve processing speed. For example, TCP packets have headers, check data, etc. The traditional solution needs to be processed by CPU using software (such as removing headers, checking data consistency, etc.), but in this application, the protocol acceleration engine in the network card can be directly used This process is equivalent to offloading protocol processing operations to hardware, thereby saving processor processing resources.

Further, the hardware acceleration engine in this embodiment further includes a data stream acceleration engine, and the data stream acceleration engine is used to implement data handling operations, data encoding operations, data transcoding operations, memory comparison operations, data query operations, and data insertion operations. at least one of the operations.

Specifically, when the above-mentioned six operations are implemented by the data stream acceleration engine in the present application, each data stream acceleration engine can be set to implement different operations, thereby improving data processing efficiency and thus improving data storage performance; Executing data transfer operations can accelerate data copying, thus replacing the traditional CPU to complete the memcpy operation, and transfer data of a certain size through the data stream acceleration engine. The supported media include: memory, non-volatile memory, etc.; Data encoding operations include data erasure operations, data encryption, data compression, etc. The erasure operations are implemented through the data stream acceleration engine, replacing the original architecture that uses CPU to calculate data. Due to the use of high-speed interconnection shared buses The technology makes the data transfer between different modules in the erasure coding process very small, the overhead is extremely low, and the fast access to the I/O path is realized; when the data encryption and data compression functions are implemented through the data stream acceleration engine, the data encryption and data compression functions can be carried out on the data path. Combination, that is, if both data encryption and data compression are required, the I/O paths can be combined for processing. Compared with the previous separate processing logic, the path is shorter and better. Performing memory comparison operations through the data stream acceleration engine can accelerate data comparison, replacing the traditional CPU to complete the memcmp operation, and compare data of a certain size through the data stream acceleration engine. The supported comparisons include: all-zero detection, all-one detection, and memory comparison The comparison operation also includes data deduplication, data consistency protection, etc.

In summary, it can be seen that this solution can efficiently implement data handling operations, data encoding operations, data transcoding operations, memory comparison operations, data query operations, and data insertion operations by setting up an independent data stream acceleration engine, reducing I. The delay of the /O path is down to microseconds, and this way of processing the data stream specially by the data stream acceleration engine can reduce the impact of hardware resources on the control flow in the control plane, thereby improving the storage data processing unit in the field of data storage. processing performance.

Referring to FIG. 2 , it is a schematic structural diagram of a system provided by an embodiment of the present invention. It can be seen from this figure that the user state of the storage data processing unit in this embodiment includes a control plane 21 , a data plane 22 and a common module 23 . The control plane 21 includes various software processing operations implemented by the ARM processor, specifically including: storage configuration service operations, chassis management operations, log collection operations, exception handling operations, firmware upgrade operations, user security operations, and production diagnostic operations. The data plane 22 includes six-level accelerated cooperative processing operations implemented by the data stream acceleration engine, and NVMe oFTarget management operations, IO multi-path management operations, cache management operations, Disk management operations, and protocol processing operations implemented by the ARM processor. Common modules are used to implement: task scheduling management operations, memory management operations and driver management operations.

Specifically, the core of the ARM processor in the storage data processing unit is mainly used to complete the task of the control plane, and the computing power of the core of the ARM processor is used to perform relatively complex storage operations; among them, the storage configuration service operation mainly involves human complex logical tasks such as computer user interface, configuration file reading and writing; chassis management operations mainly involve the management of some or all of the chassis, shared or non-shared hardware devices, exception handling, and alarm reporting; log collection operations mainly involve FW dump in the SPU (Firmware dump, firmware dump) collection, dump, SPU internal OS (operating system, operating system) and hardware accelerator internal log files collection; exception handling operations mainly involve the handling of various software and hardware exception scenarios; firmware The upgrade operation is mainly responsible for upgrading the internal FW of the SPU; the user security operation mainly involves the security strategy and security mechanism of the software and hardware co-design; the production diagnosis operation is mainly responsible for the software diagnosis system in the production stage.

In the data plane 22, the six-level accelerated cooperative processing operations implemented by the data stream acceleration engine specifically include: data handling operations, data encoding operations, data transcoding operations, memory comparison operations, data query operations, and data insertion operations; NVMe oF Target operations (Destination end) management operation refers to: at the destination end (receiving node) of the NVMe over Fabric protocol, perform protocol parsing operations on NVMe (non-volatile memory express, non-volatile memory host controller interface specification) protocol packets Processing operation; IO multi-path management operation refers to sending the received data to the corresponding storage medium through the corresponding IO path during data transmission; cache management operation refers to the frequently read data from the bottom layer in order to improve storage performance The storage medium is read into the memory, so that the upper-layer application can directly read the corresponding data from the memory without reading from the underlying storage medium; the Disk management operation refers to the management of the storage medium; the protocol processing operation refers to the NVMe protocol The initiator of the /SAS protocol/SATA protocol is equivalent to the data sender, which packages and encapsulates the data according to the protocol type, writes it to the kernel driver through the driver layer, and finally writes it to the hardware medium.

In the common module 23, the task scheduling management operation is used to manage the task scheduling strategy, such as: task conflict management, task priority management, etc.; the memory management operation is used for memory management. Operations including memory resource pools, memory sharing, and zero-copy data can be implemented through memory management operations; driver management operations are used to manage user-mode drivers, involving all dedicated drivers for hardware in the chip, which are used to drive hardware acceleration engines. , network card, etc. to realize data read, write and control functions; and, in the traditional scheme, task scheduling management operations, memory management operations and driver management operations are implemented in the kernel mode, but in this scheme, in order to store the data processing unit More efficient, the common module is implemented in user mode, such as: the driver management operation in the traditional scheme is implemented in the kernel mode, so the driver needs to communicate between the kernel mode and the user mode through interrupt processing, which is inefficient. , and in this solution, since the driver is set in the user mode, it can process data through a non-blocking and non-interrupted polling method, thereby completing the task efficiently.

Referring to FIG. 3a, it is a schematic diagram of a control flow of a control plane provided by an embodiment of the present invention, and referring to FIG. 3b, it is a schematic diagram of a data flow of a data plane provided by an embodiment of the present invention. In Figure 3a and Figure 3b, RNIC (RDMA-aware network interface controller) is a network interface controller supporting RDMA (Remote Direct Memory Access, Remote Direct Data Access), and the protocol acceleration engine includes offloading the TCP protocol and NVMe over Fabric. Protocol offload operation, and hardware acceleration operation of data consistency protocol T10-DIF (Data Integrity Field, data consistency protection), Core is the core of ARM processor, L3Cache is L3 cache, DRAM is (Dynamic Random Access Memory) is dynamic Random access memory, data stream acceleration engine is used to implement data handling operations, data encoding operations, data transcoding operations, memory comparison operations, data query operations, data insertion operations, SATA (Serial ATA, Serial ATA) interface, PCIe (peripheral component interconnect express, high-speed serial computer expansion bus standard) interface, SAS (Serial Attached SCSI, serial SCSI) interface is used to connect with other storage media, such as: SSD (Solid State Disk, solid-state drive) and HDD (Hard Disk Drive).

In Figure 3a, the control plane mainly controls the configuration and operation of the relevant modules (cache, memory, network card, etc.) through the Core. For example, when configuring the network card, it is necessary to control the network card through the relevant software on the Core to perform initialization or configuration. When performing these operations, memory processing will be involved. This process is the first control flow line in Figure 3a. In the second control flow line in Figure 3a, initialization work or configuration work is performed on the acceleration engine. Or when configuring the controller of the storage medium, it also needs to be processed by the Core, and this process also involves the processing of the memory. In the data flow shown in Figure 3b, it is necessary to obtain data packets from the front end through the network card, the protocol acceleration engine performs protocol processing on the data packets to obtain the corresponding data and stores them in the memory, and the data flow acceleration engine performs data processing operations on the data. The processed data is written into the storage medium through the corresponding interface to complete the data writing process, and the data reading process is the reverse direction process, which will not be described in detail again.

From the above, it can be seen that the storage data processing unit in this solution can distinguish the data flow and the control flow from the hardware based on the numerical control separation architecture, so as to avoid the mutual influence between the control flow and the data flow, thereby reducing the impact on the storage performance. , in order to optimize the internal I/O performance of the storage data processing unit to the greatest extent; through the hardware acceleration engine, data processing operations can be efficiently realized, and under the large number of IO processing requirements in the storage field, the separation architecture and hardware acceleration engine can realize the rapid flow of data , supports parallel processing of multiple concurrent I/Os, improves the processing performance of the storage data processing unit in the field of data storage, improves I/O processing efficiency, and saves equipment costs. Moreover, implementing the common module in the user mode can further improve the processing efficiency of the storage data processing unit.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other.

The above description of the disclosed embodiments enables any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. a storage data processing unit based on numerical control separation architecture, is characterized in that, comprises: Processor and hardware acceleration engine; The hardware acceleration engine is used to implement protocol offloading operations and data processing operations of the data plane; the processor is used to implement software processing operations of the control plane and processing operations other than the data processing operations in the data plane . 2 . The storage data processing unit according to claim 1 , wherein the hardware acceleration engine comprises a protocol acceleration engine, and the protocol acceleration engine is used to implement protocol processing operations and hardware acceleration operations of data consistency. 3 . 3 . The storage data processing unit according to claim 2 , wherein the protocol acceleration engine is specifically used to implement TCP protocol processing operations and NVMe over Fabric protocol processing operations. 4 . 4. storage data processing unit according to claim 3, is characterized in that, described hardware acceleration engine comprises data stream acceleration engine, and described data stream acceleration engine is used to realize data handling operation, data encoding operation, data transcoding operation , at least one of a memory comparison operation, a data query operation, and a data insertion operation. 5. The storage data processing unit according to claim 1, wherein the processor is an ARM processor. 6. The storage data processing unit according to claim 5, characterized in that, The software processing operations implemented by the ARM processor include: at least one of storage configuration service operations, chassis management operations, log collection operations, exception processing operations, firmware upgrade operations, user security operations, and production diagnostic operations. 7. The storage data processing unit according to claim 6, characterized in that, The processing operations implemented by the ARM processor in the data plane include: at least one of NVMe oF Target management operations, IO multipath management operations, cache management operations, Disk management operations, and protocol processing operations. 8 . The storage data processing unit according to claim 1 , wherein the processor implements software processing operations of the control plane through different processor cores, and the data processing operations in the data plane other than the data processing operations are implemented by the processor. 9 . Handling operations. 9 . The storage data processing unit according to claim 1 , wherein the user state of the storage data processing unit includes the data plane, the control plane, and a common module. 10 . 10 . The storage data processing unit according to claim 9 , wherein the common module is used to implement: task scheduling management operations, memory management operations, and driver program management operations. 11 .

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