CN118802046A - Time synchronization method, device, electronic device and storage medium - Google Patents

Abstract

The disclosure relates to a time synchronization method, a device, an electronic device and a storage medium, wherein the method comprises the following steps: obtaining a plurality of groups of transmission information obtained by calculation between a master device and a slave device; based on multiple groups of transmission information, obtaining average time deviation and average network delay between the master device and the slave device; adjusting the system time of the slave device based on the average time deviation, acquiring the adjusted network delay between the master device and the slave device, and acquiring the time deviation between the master device and the slave device under the condition that the difference value between the network delay and the average network delay is smaller than a first threshold value; and acquiring the deviation between the system time and the master clock, adjusting the system time based on the deviation, and synchronizing the system time of the slave device based on the time deviation in the case that the time deviation between the master device and the slave device is smaller than a second threshold. By counteracting the introduced predictable deviation and the deviation in the link, the time synchronization accuracy can be improved.

Description

Time synchronization method, device, electronic device and storage medium

Technical Field

The present disclosure relates to the field of computer technology, and in particular to a time synchronization method, device, electronic device and storage medium.

Background Art

In the communication network, the normal operation of most telecommunications services requires that the time difference between the devices in the entire network be kept within a reasonable error level, that is, time synchronization. However, due to the certain accuracy of the equipment (for example, +/-20ns), in the actual transmission network time synchronization application, the transmission equipment mainly bears the intermediate BC (Boundary Clock) unit, and there are usually 10 to 20 hops of transmission equipment. For example, when the number of equipment increases to 20 hops, the deviation will increase hop by hop. Theoretically, the deviation may reach about 400ns. As the number of hops increases, the accuracy deviation value will gradually increase.

In the related art, if the accuracy of the equipment is improved, the time synchronization accuracy of the single-hop equipment is improved by improving the hardware capabilities, which will have high hardware requirements and high hardware costs; and it cannot solve the problem of reduced time synchronization accuracy as the number of equipment hops increases. If the end-to-end time deviation is measured first when the time synchronization application is actually deployed, and the time deviation is compensated to the system to improve the time synchronization accuracy, then in the case of increasing the number of devices, changing the optical fiber length, etc., various network networking changes need to be re-measured, and the project implementation is difficult and costly. Therefore, the related art is less efficient in solving the problem of reduced time synchronization accuracy.

Summary of the invention

The present disclosure provides a time synchronization method, device, electronic device and storage medium.

According to a first aspect of the present disclosure, a time synchronization method is provided, the method comprising:

Acquire multiple sets of transmission information calculated between the master device and the slave device; wherein the transmission information includes time deviation and network delay;

Based on the multiple groups of transmission information, obtain an average time deviation and an average network delay between the master device and the slave device;

Adjusting the system time of the slave device based on the average time deviation, and obtaining the adjusted network delay between the master device and the slave device; and obtaining the time deviation between the master device and the slave device when the difference between the network delay and the average network delay is less than a first threshold;

Obtain a deviation between the system time and a master clock, adjust the system time based on the deviation, and synchronize the system time of the slave device based on the time deviation when the time deviation between the master device and the slave device is less than a second threshold.

According to a second aspect of the present disclosure, a time synchronization device is provided, the device comprising:

A first information acquisition module, used to acquire multiple sets of transmission information calculated between the master device and the slave device; wherein the transmission information includes time deviation and network delay;

A second information acquisition module, configured to obtain an average time deviation and an average network delay between the master device and the slave device based on the multiple sets of transmission information;

a third information acquisition module, configured to adjust the system time of the slave device based on the average time deviation, and obtain the adjusted network delay between the master device and the slave device; and obtain the time deviation between the master device and the slave device when the difference between the network delay and the average network delay is less than a first threshold;

A time synchronization module is used to obtain the deviation between the system time and the master clock, adjust the system time based on the deviation, and synchronize the system time of the slave device based on the time deviation when the time deviation between the master device and the slave device is less than a second threshold.

According to a third aspect of the present disclosure, an electronic device is provided, which includes a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the program, the method described above is implemented.

According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, the above method of the present disclosure is implemented.

The time synchronization method, device, electronic device and storage medium provided by the embodiments of the present disclosure obtain multiple groups of transmission information containing time deviation and network delay between the master device and the slave device, and based on the multiple groups of transmission information, obtain the average time deviation and average network delay between the master device and the slave device, and adjust the system time of the slave device based on the average time deviation, and obtain the adjusted network delay between the master device and the slave device; and obtain the time deviation between the master device and the slave device when the difference between the network delay and the average network delay is less than a first threshold. Obtain the deviation between the system time and the master clock, adjust the system time based on the deviation, and synchronize the system time of the slave device based on the time deviation when the time deviation between the master device and the slave device is less than a second threshold. By offsetting the introduced predictable deviation with the deviation in the link, the time synchronization accuracy can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

FIG1 is a schematic diagram of interaction between master and slave devices provided by an exemplary embodiment of the present disclosure;

FIG2 is a schematic diagram of correcting system time through offset provided by an exemplary embodiment of the present disclosure;

FIG3 is a schematic diagram of an offset value range in a multi-hop process provided by an exemplary embodiment of the present disclosure;

FIG4 is a schematic block diagram of a time synchronization method according to an exemplary embodiment of the present disclosure;

FIG5 is a schematic block diagram of functional modules of a time synchronization device provided by an exemplary embodiment of the present disclosure;

FIG6 is a structural block diagram of an electronic device provided by an exemplary embodiment of the present disclosure;

FIG. 7 is a structural block diagram of a computer system provided by an exemplary embodiment of the present disclosure.

DETAILED DESCRIPTION

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and/or in parallel. In addition, the method embodiments may include additional steps and/or omit the steps shown. The scope of the present disclosure is not limited in this respect.

The term "including" and its variations used in this document are open inclusions, that is, "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions of other terms will be given in the description below. It should be noted that the concepts of "first", "second", etc. mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

It is understandable that before using the technical solutions disclosed in the embodiments of the present disclosure, the types, scope of use, usage scenarios, etc. of the personal information involved in the present disclosure should be informed to the user and the user's authorization should be obtained in an appropriate manner in accordance with relevant laws and regulations.

For example, in response to receiving an active request from a user, a prompt message is sent to the user to clearly prompt the user that the operation requested to be performed will require obtaining and using the user's personal information. Thus, the user can autonomously choose whether to provide personal information to software or hardware such as an electronic device, application, server, or storage medium that performs the operation of the technical solution of the present disclosure according to the prompt message.

As an optional but non-limiting implementation, in response to receiving an active request from the user, the method of sending a prompt message to the user may be, for example, a pop-up window, in which the prompt message may be presented in text. In addition, the pop-up window may also carry a selection control for the user to choose "agree" or "disagree" to provide personal information to the electronic device. It is understandable that the above notification and the process of obtaining user authorization are only illustrative and do not constitute a limitation on the implementation of the present disclosure. Other methods that meet relevant laws and regulations may also be applied to the implementation of the present disclosure.

According to the basic principle of IEEE1588 synchronization, the device uses a fixed step to adjust the time accuracy. Taking the current mainstream accuracy Class B as an example, the accuracy of each hop device is +/-20ns. Therefore, after the time accuracy of this device is adjusted to +/-20ns, it will no longer be adjusted. Then when the device increases to 20 hops, the deviation increases hop by hop. Theoretically, the deviation should reach about 400ns. As the number of hops increases, the accuracy deviation value will gradually increase. Therefore, time synchronization is required to reduce the accuracy deviation.

Among them, the 1588 protocol is defined by IEEE, and its full name is "Precision Clock Synchronization Protocol for Networked Measurement and Control Systems", or PTP (Precision Time Protocol) for short. 1588 is divided into two versions: 1588v1 and 1588v2. 1588v1 can only achieve sub-millisecond time synchronization accuracy, while 1588v2 can achieve sub-microsecond synchronization accuracy. 1588v2 is defined as a time synchronization protocol that can be used for high-precision time synchronization between devices.

A network that uses time synchronization can be called a time synchronization network. The time synchronization network can be divided into two levels, where the first-level nodes can use level 1 time synchronization equipment, and the second-level nodes can use level 2 time synchronization equipment. Devices that need time synchronization, including servers or clients, can be included below the second-level nodes.

The disclosed embodiment supports 1588v2 (including derivative protocols such as ITU-T G.8275.1), which can improve the time synchronization accuracy of the entire network of devices and solve the problem of gradual degradation of network clock accuracy in multi-hop scenarios. In addition, the disclosed embodiment automatically calculates and adjusts the master-slave device deviation based on the 1588v2 synchronization principle, thereby achieving the effect of offsetting the time deviation of the entire synchronization link.

Depending on whether the message carries a timestamp, 1588v2 messages can be divided into two categories: event messages and general messages. Among them, event messages are time-concept messages, which will be accurately timestamped when entering and exiting the device port, and are used to calculate the time offset and path delay between the master and slave clocks. Event messages include: Sync, Delay_Req, and Delay_Resp. In the embodiment, event messages can be used to more conveniently obtain the time corresponding to the timestamp. As shown in Figure 1, t1, t2, t3, and t4 can be obtained. The Master in Figure 1 is the master device, and the Slave is the slave device. The Master and Slave are in a master-slave relationship.

As shown in Figure 1, the master device sends a Sync message at time t1. If the master device is in one-step mode, t1 is transmitted to the slave device along with the Sync message. The slave device receives the Sync message at time t2 and obtains t1 from the Sync message. The slave device sends a delay request message Delay_Req to the master device at time t3. The master device receives the Delay_Req message at time t4. The master device then sends t4 to the slave device through a delay reply message Delay_Resp.

The basic principle of 1588v2 time synchronization is that the master and slave devices (Master-Slave) send and receive time synchronization messages in both directions. The total round-trip delay between the two devices is calculated based on the sending and receiving timestamps of the messages. If the delays in both directions are the same, the total round-trip delay divided by 2 is the one-way delay, based on which the time deviation from the slave to the master can be obtained.

In the embodiment, offset represents the time deviation between the master and slave devices, and delay represents the delay time caused by network transmission. If the delays of the sending and receiving paths in FIG1 are consistent, the following relationship exists:

delay = [(t2 - t1) + (t4 - t3)] / 2 (1)

offset = [(t2 - t1) - (t4 - t)] / 2 (2)

As shown in Figure 2, the device calculates the time offset between the local clock and the master clock source through the 1588v2 protocol, and then corrects the local clock. This repetitive and continuous synchronization process ensures that the Slave is synchronized with the Master.

If the path delay between the Master and Slave is asymmetric, a synchronization error will be introduced, and the size of the error is half of the difference in the path delays in the two directions. Therefore, the key to 1588v2 high-precision time synchronization is that the delay between the two nodes is as stable as possible, without jitter. Link delays can generally meet this condition, but the forwarding delay jitter of the device is large. Therefore, in the IEEE standard 1588v2 protocol, the delay correction field needs to be involved in the calculation of the Delay method to obtain the correct average path delay Delay and time offset Offset. In the embodiment, assuming that △ is the delay difference between the Master's Tx path (transmitting path) and the Rx path (receiving path), then the following relationship exists:

delay = ((t2 –t1) + (t4–t3)) / 2-△ / 2 (3)

offset = ((t2 –t1) - (t4–t3)) / 2 -△ / 2 (4)

Therefore, under the premise of frequency synchronization, the time deviation caused by link asymmetry is half of the link asymmetric delay. As long as the deviation caused by link asymmetry is offset, the time accuracy of the entire network can be greatly improved, so that ordinary precision equipment can achieve the effect of a high-precision network.

In the embodiment, regarding the calculation of Δ, the device will not accurately calculate the value of Δ at each hop, but can adjust a certain amount of offset in the positive direction or negative direction through the device, so as to offset part of the Δ deviation at the end of the link. The Δ in the embodiment may refer to the deviation introduced by the asymmetry of the transceiver link. The larger the deviation, the worse the time accuracy of 1588. In the embodiment of the present disclosure, the Δ of different devices offset each other, so that the Δ of the entire link approaches 0, thereby providing the time accuracy of 1588 for the entire link.

In an embodiment, methods for obtaining Δ may include: obtaining it through measurement with a dedicated instrument; it may also be calculated through conversion of the optical fiber length of the transmitting and receiving paths. Different optical fibers, wavelengths, and refractive indices result in slightly different delays per meter, but the deviation is not large; it may also be calculated within the device, and Δ may be obtained by reversely calculating through two time-synchronized devices (at this time, the offset is known to be 0) using the offset formula.

In the embodiment, in order to eliminate the deviation caused by link asymmetry and improve the time accuracy of the device, the embodiment may include the following steps:

Step 1: After the entire network is configured with 1588, the BMC (Best Master Clock) algorithm negotiates the result. After the state decision is completed, the slave device begins to extract t1, t2, t3, and t4, and calculates the offset and delay between the master and slave devices in the above manner. At this time, the system time on the slave end is not adjusted. Each group of t1, t2, t3, and t4 can calculate the delay and offset once, and the values calculated for the first group of t1, t2, t3, and t4 can be discarded to eliminate the error introduced by the first message negotiation, and this operation does not affect the calculation speed.

Step 2: For each group of t1, t2, t3, and t4, a delay and offset can be calculated once, and the calculated delay and offset are cached. In the embodiment, after at least 3 calculations, the delay and offset of 3 consecutive times can be compared. If the difference between the 3 results is 5ns, that is, the difference between the delay obtained 3 times and the difference between the offset obtained 3 times are respectively less than the threshold, it is considered that a stable delay and offset are obtained, and the average value of 3 times is calculated, and the delay and offset values of this average value are recorded as the result, otherwise the calculation of the 3 groups is discarded and step 2 is re-executed. Among them, the threshold depends on the system accuracy. The more stable the system clock is, the smaller this value can be set. The embodiment takes the threshold of 5ns as an example for explanation, and the embodiment is not limited to this.

Step 3: Adjust the system time of the slave end according to the offset value calculated in the above steps. After stopping the adjustment, recalculate the delay and offset values according to step 2. Compare the delay with the delay recorded in step 2. If the difference is within 5ns, the system is considered normal and the offset value is recorded. Otherwise, the system is considered abnormal and recalculated according to step 3.

Step 4: According to the positive or negative value of the offset value obtained in the above steps, determine the time deviation between the time corresponding to the current system and the master clock. If the time deviation is positive, it means that the first offset adjustment is too little, and it is necessary to continue to adjust in the positive direction. If the time deviation is negative, it means that the first offset adjustment is too much, and it is necessary to adjust in the reverse direction. Repeat step 3 until the offset calculation result approaches 0 within 20ns, and finally obtain a stable offset of the system. It should be noted that the final offset value can be obtained according to the empirical value. This value is the value of the time error adjustment. For example, a more reasonable value can be obtained according to the actual measurement of the system, and the embodiment is not limited to this. After the above steps, it is equivalent to artificially introducing some predictable deviations, which are roughly offset by the deviations introduced by the link asymmetry, thereby automatically improving the time synchronization accuracy. After spreading to the entire network, the goal of controllable accuracy can be achieved.

Based on the above embodiments, in the embodiments provided by the present disclosure, in order to make the time synchronization accuracy of the entire network further controllable, a step mechanism may be used to perform time synchronization on the entire network.

In the embodiment, time synchronization can be realized by the clock interface module and the clock processing module. The clock interface module is used to extract and insert clock messages and clock information, such as t1, t2, t3 and t4 mentioned above, while the service is accessed; the clock processing module is responsible for parsing the clock information extracted by the interface module and performing calculations, adjusting the clock of the device according to the calculation results, and passing the clock information downward.

In the embodiment, after the clock processing module receives the clock information extracted by the clock interface module, it detects that the step value in the information is an odd number. When adjusting the clock, it adjusts in the positive direction of the offset, and controls the interval for stopping the adjustment to be 0ns to 20ns. The value of the offset can be obtained specifically in the above manner. When it is detected that the step in the information is an even number, it adjusts in the negative direction of the offset, that is, the interval for stopping the adjustment is -20ns to 0ns. After such calculation and adjustment, the clock tracking situation is shown in Figure 3, and T-BC represents the boundary clock. Among them, step represents a jump in the network. A jump refers to the unit of measurement of a path in a network. It can be a data packet transferred from a device with an IP address to another adjacent device with an IP address, that is, it takes a step on the network.

In an embodiment, the entire network may include multiple nodes, such as node 1, node 2, node 3... During time synchronization, odd nodes are uniformly biased toward the positive direction, that is, the offset takes a positive value; even nodes are uniformly biased toward the negative direction, that is, the offset takes a negative value; therefore, the end-to-end deviation is the sum of all odd nodes plus the sum of all even nodes, and the positive and negative deviations can offset each other for the most part, so that the end-to-end time deviation remains normal, which is far lower than the average level of 20-hop network elements, and will not exceed the limit value of 400ns of deviation in related technologies, which can greatly improve the end-to-end time synchronization accuracy.

In this way, the deviation between the two devices can be mostly offset. Therefore, no matter how much the number of hops increases, the deviation will not increase linearly, but will be controlled within the deviation of one hop network element. Taking the mainstream accuracy Class B as an example, the accuracy is about +/-20ns, which is much higher than the +/-1us required by actual business needs.

Based on the above embodiment, in another embodiment provided by the present disclosure, a time synchronization method is provided. As shown in FIG4 , the method may include the following steps:

In step S410, multiple groups of transmission information calculated between the master device and the slave device are obtained.

The transmission information includes time deviation and network delay.

In an embodiment, multiple groups of transmission information including time deviations and network delays may be obtained, and each group of transmission information may include a time deviation and a network delay.

In step S420, based on multiple groups of transmission information, the average time deviation and average network delay between the master device and the slave device are obtained.

In an embodiment, the time deviation and network delay between the master device and the slave device can be calculated according to the method provided in the above embodiment. For example, the target message and the link delay difference transmitted between the master device and the slave device can be obtained, and the time deviation and network delay can be obtained based on the timestamp and the link delay difference. The target message carries a timestamp. The target message can include the Sync, Delay_Req and Delay_Resp messages in the above embodiment.

In an embodiment, offset and delay calculated from at least three groups of messages may be obtained, and the three groups of offsets and delays may be averaged to obtain average time deviation and average network delay, ie, average offset and average delay, respectively.

In step S430, the system time of the slave device is adjusted based on the average time deviation, the adjusted network delay between the master device and the slave device is obtained, and when the difference between the network delay and the average network delay is less than a first threshold, the time deviation between the master device and the slave device is obtained.

In the embodiment, the first threshold value may be set to 5 ns, and may be set as required, but the embodiment is not limited thereto.

The time difference between the system time of the slave device and the time corresponding to the master clock can be obtained, and the first time deviation can be adjusted based on the time difference to obtain the adjusted time deviation, and the system time of the slave device can be adjusted based on the adjusted time deviation.

In step S440, the deviation between the system time and the master clock is obtained, the system time is adjusted based on the deviation, and when the time deviation between the master device and the slave device is less than a second threshold, the system time of the slave device is synchronized based on the time deviation.

In the embodiment, the system time of the slave device can be adjusted according to the offset obtained above, and the offset and delay between the master and slave devices can be recalculated after the adjustment is completed. The absolute value of the difference between the delay and the delay can be compared to see whether it is less than a second threshold value. The second threshold value can be 5ns, which can be set as needed, and the embodiment is not limited thereto. If the absolute value of the difference between the delay and the delay is less than the second threshold value, it is confirmed that the system is normal, otherwise it is determined that the system is abnormal, and the delay and offset can be recalculated.

In the embodiment, when the time deviation is not less than a threshold, the system time of the slave device is adjusted until the time deviation is less than a second threshold, so that the system time of the slave device can be synchronized based on the time deviation to achieve time synchronization.

The time synchronization method provided in the embodiment provided in the present disclosure obtains multiple groups of transmission information including time deviation and network delay between the master device and the slave device, and based on the multiple groups of transmission information, obtains the average time deviation and average network delay between the master device and the slave device, and adjusts the system time of the slave device based on the average time deviation, and obtains the adjusted network delay between the master device and the slave device; and when the difference between the network delay and the average network delay is less than a first threshold, obtains the time deviation between the master device and the slave device. Obtain the deviation between the system time and the master clock, adjust the system time based on the deviation, and when the time deviation between the master device and the slave device is less than a second threshold, synchronize the system time of the slave device based on the time deviation. By introducing some predictable deviations, the deviations introduced by link asymmetry are offset, thereby improving the accuracy of time synchronization.

Based on the above embodiment, in another embodiment provided by the present disclosure, the above target message includes at least N groups of messages, and the N groups of messages respectively carry timestamps; the above step S410 may include the following steps:

Step S411, obtaining multiple groups of messages transmitted between the master device and the slave device.

The message carries a timestamp.

Step S412: obtaining multiple groups of transmission information between the master device and the slave device based on the timestamps respectively carried by the multiple groups of messages, and discarding the first group of transmission information among the multiple groups of transmission information.

In the embodiment, multiple groups of time deviations and network delays transmitted between the master device and the slave device can be obtained, the first group of the multiple groups of time deviations and network delays can be discarded, and the remaining groups are used as multiple groups of transmission information calculated between the master device and the slave device. Specifically, in the embodiment, multiple groups of time deviations and network delays can be obtained, and each group of time deviations and network delays can obtain a group of time, such as t1, t2, t3 and t4. Each group of time can be calculated to obtain a time deviation offset and a network delay delay respectively. Since the first message negotiation will introduce errors, the offset and delay calculated from the first group of messages can be discarded, that is, the offset and delay calculated based on the first group of t1, t2, t3 and t4 are discarded to obtain multiple groups of transmission information including time deviations and network delays.

In the embodiment provided by the present disclosure, based on the above embodiment, the above step S420 may further include the following steps:

Step S421, determining whether the difference between any two time offsets and the difference between any two network delays in the plurality of groups of transmission information are both smaller than a first threshold.

Step S422, when the difference between any two time deviations and the difference between any two network delays in multiple groups of transmission information are both less than the first threshold, calculate the average value of multiple time deviations and the average value between multiple network delays in the multiple groups of transmission information to obtain the average time deviation and the average network delay respectively.

Furthermore, in an embodiment, when the difference between any two time deviations and the difference between any two network delays in multiple groups of transmission information are not both less than a first threshold, the multiple groups of transmission information can be discarded, and the multiple groups of transmission information between the master device and the slave device can be recalculated until the difference between any two time deviations and the difference between any two network delays in the multiple groups of transmission information are both less than the first threshold.

In the embodiment provided by the present disclosure, each of the above groups of t1, t2, t3 and t4 can calculate a delay and offset. After at least 3 calculations, the delay and offset of 3 consecutive times are compared. If the difference between the 3 results is less than the first threshold, for example, less than 5ns, it is considered that a stable delay and offset are obtained, and the average value of 3 times is calculated, and the delay and offset values of this average value are recorded as the result. Otherwise, the calculation of the 3 groups is discarded, and the delay and offset are recalculated. In this way, the offset obtained by the 3 averages can be used as the first time deviation, and the delay obtained by the 3 averages can be used as the first network delay, so that the delay and offset obtained are more accurate.

In the embodiments provided in the present disclosure, the method may further include the following steps:

In step S450, clock information is obtained, where the clock information includes a step value;

In step S460, when the step value is an odd number, the system time of the slave device is adjusted, and when the time deviation is within a first preset range, the system time adjustment is stopped; or, when the step value is an even number, the system time of the slave device is adjusted, and when the time deviation is within a second preset range, the system time adjustment is stopped.

In the embodiment, time synchronization can be realized by the clock interface module and the clock processing module. The clock interface module is used to extract and insert clock messages and clock information, such as t1, t2, t3 and t4 mentioned above, while the service is accessed; the clock processing module is responsible for parsing the clock information extracted by the interface module and performing calculations, adjusting the clock of the device according to the calculation results, and passing the clock information downward. This can be combined with the description of the above FIG. 3 and the corresponding embodiment, which will not be repeated here.

Based on the above embodiment, in another embodiment provided by the present disclosure, the method may further include the following steps:

In step S470, the parity of the node number corresponding to the slave device is obtained.

In the embodiment, the values of delay and offset between different master and slave devices calculated in the above manner may be different, but in order to offset the deviation caused by link asymmetry between different devices, it is necessary to determine the positive and negative offsets of different slave devices so as to offset them in the positive network.

In step S480, the positive and negative values corresponding to the second time deviation are determined based on the parity of the node number, wherein each slave device includes a corresponding node number, and the positive and negative values corresponding to the time deviations of two slave devices with adjacent node numbers are different.

In the embodiment, the offset corresponding to the node with an odd number is a positive value, and the offset corresponding to the node with an even number is a negative value by obtaining the node number. For example, the offset values corresponding to node 1, node 2, node 3, etc. are 20ns, -30ns, 15ns, etc. respectively. In this way, the end-to-end deviation is the sum of all odd-numbered nodes plus the sum of all even-numbered nodes. The positive and negative deviations can offset each other for the most part, and the end-to-end deviation remains normal, which is far lower than the average level of 20-hop network elements, and the limit value of 400ns will not appear, which can greatly improve the end-to-end time synchronization accuracy.

In the case of dividing each functional module according to each function, an embodiment of the present disclosure provides a time synchronization device, which can be a server or a chip applied to a server. FIG5 is a schematic block diagram of the functional modules of a time synchronization device provided by an exemplary embodiment of the present disclosure. As shown in FIG5, the time synchronization device includes:

The first information acquisition module 10 is used to acquire multiple sets of transmission information calculated between the master device and the slave device; wherein the transmission information includes time deviation and network delay;

A second information acquisition module 20, configured to obtain an average time deviation and an average network delay between the master device and the slave device based on the multiple sets of transmission information;

A third information acquisition module 30 is used to adjust the system time of the slave device based on the average time deviation, obtain the adjusted network delay between the master device and the slave device, and obtain the time deviation between the master device and the slave device when the difference between the network delay and the average network delay is less than a first threshold;

The time synchronization module 30 is used to obtain the deviation between the system time and the master clock, adjust the system time based on the deviation, and synchronize the system time of the slave device based on the time deviation when the time deviation between the master device and the slave device is less than a second threshold.

In another embodiment provided by the present disclosure, the first information acquisition module is specifically used to:

Acquire multiple groups of messages transmitted between the master device and the slave device, the messages carrying timestamps;

Based on the timestamps respectively carried by the multiple groups of messages, multiple groups of transmission information between the master device and the slave device are obtained, and the first group of transmission information among the multiple groups of transmission information is discarded.

In another embodiment provided by the present disclosure, the second information acquisition module is specifically used to:

Determine whether a difference between any two time deviations and a difference between any two network delays in the plurality of groups of transmission information are both less than a first threshold;

When the difference between any two time deviations and the difference between any two network delays in the multiple groups of transmission information are both smaller than a first threshold, the average values of multiple time deviations and the average values of multiple network delays in the multiple groups of transmission information are calculated to obtain the average time deviation and the average network delay, respectively.

In another embodiment provided by the present disclosure, the device further includes:

A processing module is used to discard the multiple groups of transmission information and recalculate the multiple groups of transmission information between the master device and the slave device when the difference between any two time deviations and the difference between any two network delays in the multiple groups of transmission information are not both less than a first threshold value, until the difference between any two time deviations and the difference between any two network delays in the multiple groups of transmission information are both less than the first threshold value.

In another embodiment provided by the present disclosure, the time synchronization module is specifically used to:

When the deviation between the system time and the master clock is a positive number, adjusting the system time in a positive direction;

Alternatively, when the deviation between the system time and the master clock is a negative number, the system time is adjusted in the reverse direction;

When the time deviation between the master device and the slave device is less than a second threshold, stop adjusting the system time.

In another embodiment provided by the present disclosure, the device further includes:

A clock information acquisition module, used to acquire clock information, wherein the clock information includes a step value;

The adjustment module is used to adjust the system time of the slave device when the step value is an odd number, and stop adjusting the system time when the time deviation is within a first preset range; or, when the step value is an even number, adjust the system time of the slave device, and stop adjusting the system time when the time deviation is within a second preset range.

In another embodiment provided by the present disclosure, the device further includes:

A number acquisition module, used to obtain the parity of the node number corresponding to the slave device;

A range determination module is used to determine the positive and negative values corresponding to the second time deviation based on the parity of the node number; wherein each slave device includes a corresponding node number, and the positive and negative values corresponding to the time deviations of two slave devices with adjacent node numbers are different.

The time synchronization device provided by the embodiment of the present disclosure obtains multiple groups of transmission information including time deviation and network delay between the master device and the slave device, and based on the multiple groups of transmission information, obtains the average time deviation and average network delay between the master device and the slave device, and adjusts the system time of the slave device based on the average time deviation, and obtains the adjusted network delay between the master device and the slave device; and obtains the time deviation between the master device and the slave device when the difference between the network delay and the average network delay is less than a first threshold. Obtain the deviation between the system time and the master clock, adjust the system time based on the deviation, and synchronize the system time of the slave device based on the time deviation when the time deviation between the master device and the slave device is less than a second threshold. By introducing some predictable deviations and offsetting the deviations in the link, the accuracy of time synchronization can be improved.

An embodiment of the present disclosure also provides an electronic device, comprising: at least one processor; and a memory for storing instructions executable by the at least one processor; wherein the at least one processor is configured to execute the instructions to implement the above method disclosed in the embodiment of the present disclosure.

Fig. 6 is a schematic diagram of the structure of an electronic device provided by an exemplary embodiment of the present disclosure. As shown in Fig. 6, the electronic device 1800 includes at least one processor 1801 and a memory 1802 coupled to the processor 1801, and the processor 1801 can execute the corresponding steps in the above method disclosed in the embodiment of the present disclosure.

The processor 1801 may also be referred to as a central processing unit (CPU), which may be an integrated circuit chip having signal processing capabilities. Each step in the method disclosed in the embodiment of the present disclosure may be completed by an integrated logic circuit of hardware in the processor 1801 or by instructions in the form of software. The processor 1801 may be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present disclosure may be directly embodied as being executed by a hardware decoding processor, or may be executed by a combination of hardware and software modules in a decoding processor. The software module may be located in a memory 1802, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, or other mature storage media in the art. The processor 1801 reads the information in the memory 1802 and completes the steps of the method in combination with its hardware.

In addition, when various operations/processes according to the present disclosure are implemented by software and/or firmware, the programs constituting the software can be installed from a storage medium or a network to a computer system with a dedicated hardware structure, such as the computer system 1900 shown in FIG. 7. When various programs are installed, the computer system can perform various functions, including functions such as those described above. FIG. 7 is a block diagram of a computer system provided by an exemplary embodiment of the present disclosure.

Computer system 1900 is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic devices can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and/or claimed herein.

As shown in FIG7 , the computer system 1900 includes a computing unit 1901, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1902 or a computer program loaded from a storage unit 1908 into a random access memory (RAM) 1903. In the RAM 1903, various programs and data required for the operation of the computer system 1900 can also be stored. The computing unit 1901, the ROM 1902, and the RAM 1903 are connected to each other via a bus 1904. An input/output (I/O) interface 1905 is also connected to the bus 1904.

A plurality of components in the computer system 1900 are connected to the I/O interface 1905, including: an input unit 1906, an output unit 1907, a storage unit 1908, and a communication unit 1909. The input unit 1906 may be any type of device capable of inputting information to the computer system 1900, and the input unit 1906 may receive input digital or character information, and generate key signal inputs related to user settings and/or function control of the electronic device. The output unit 1907 may be any type of device capable of presenting information, and may include, but is not limited to, a display, a speaker, a video/audio output terminal, a vibrator, and/or a printer. The storage unit 1908 may include, but is not limited to, a disk, an optical disk. The communication unit 1909 allows the computer system 1900 to exchange information/data with other devices over a network such as the Internet, and may include, but is not limited to, a modem, a network card, an infrared communication device, a wireless communication transceiver, and/or a chipset, such as a Bluetooth™ device, a WiFi device, a WiMax device, a cellular communication device, and/or the like.

The computing unit 1901 may be a variety of general and/or special processing components with processing and computing capabilities. Some examples of the computing unit 1901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 1901 performs the various methods and processes described above. For example, in some embodiments, the above methods disclosed in the embodiments of the present disclosure may be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as a storage unit 1908. In some embodiments, part or all of the computer program may be loaded and/or installed on the electronic device 1900 via the ROM 1902 and/or the communication unit 1909. In some embodiments, the computing unit 1901 may be configured to perform the above methods disclosed in the embodiments of the present disclosure in any other appropriate manner (e.g., by means of firmware).

The embodiment of the present disclosure further provides a computer-readable storage medium, wherein when instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the above method disclosed in the embodiment of the present disclosure.

The computer-readable storage medium in the disclosed embodiments may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. The computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. More specifically, the computer-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

The embodiments of the present disclosure further provide a computer program product, including a computer program, wherein when the computer program is executed by a processor, the above method disclosed in the embodiments of the present disclosure is implemented.

In embodiments of the present disclosure, computer program codes for performing the operations of the present disclosure may be written in one or more programming languages or combinations thereof, including but not limited to object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" language or similar programming languages. The program code may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer.

The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and/or flow chart, and the combination of the square boxes in the block diagram and/or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

The modules, components or units involved in the embodiments described in the present disclosure may be implemented by software or hardware, wherein the names of the modules, components or units do not, in some cases, limit the modules, components or units themselves.

The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chip (SOCs), complex programmable logic devices (CPLDs), and the like.

The above descriptions are only some embodiments of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, a technical solution formed by replacing the above features with the technical features with similar functions disclosed in the present disclosure (but not limited to).

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims (10)

1. A method of time synchronization, the method comprising:

obtaining a plurality of groups of transmission information obtained by calculation between a master device and a slave device; wherein the transmission information comprises time deviation and network delay;

based on the multiple sets of transmission information, obtaining average time deviation and average network delay between the master device and the slave device;

Adjusting the system time of the slave device based on the average time deviation, acquiring the adjusted network delay between the master device and the slave device, and acquiring the time deviation between the master device and the slave device under the condition that the difference value between the network delay and the average network delay is smaller than a first threshold value;

And acquiring a deviation between the system time and a master clock, adjusting the system time based on the deviation, and synchronizing the system time of the slave device based on the time deviation when the time deviation between the master device and the slave device is smaller than a second threshold.

2. The method of claim 1, wherein the obtaining the plurality of sets of transmission information calculated between the master device and the slave device comprises:

Acquiring a plurality of groups of messages transmitted between the master device and the slave device, wherein the messages carry time stamps;

and obtaining multiple groups of transmission information between the master device and the slave device based on the time stamps carried by the multiple groups of messages respectively, and discarding a first group of transmission information in the multiple groups of transmission information.

3. The method of claim 2, wherein the obtaining an average time offset and an average network delay between the master device and the slave device comprises:

Judging whether the difference value between any two time deviations and the difference value between any two network delays in the multiple sets of transmission information are smaller than a first threshold value or not;

And under the condition that the difference value between any two time deviations and the difference value between any two network delays in the multiple groups of transmission information are smaller than a first threshold value, calculating the average value of the multiple time deviations and the average value of the multiple network delays in the multiple groups of transmission information, and respectively obtaining the average time deviation and the average network delay.

4. A method according to claim 3, characterized in that the method further comprises:

And discarding the plurality of sets of transmission information under the condition that the difference value between any two time deviations and the difference value between any two network delays in the plurality of sets of transmission information are not equal to the first threshold value, and recalculating the plurality of sets of transmission information between the master device and the slave device until the difference value between any two time deviations and the difference value between any two network delays in the plurality of sets of transmission information are all smaller than the first threshold value.

5. The method of claim 4, wherein said adjusting the system time based on the deviation comprises:

in the case that the deviation between the system time and the master clock is a positive number, the system time is adjusted in the forward direction;

or reversely adjusting the system time under the condition that the deviation between the system time and the master clock is negative;

and stopping adjusting the system time under the condition that the time deviation between the master device and the slave device is smaller than a second threshold value.

6. The method of claim 5, wherein the method further comprises:

acquiring clock information, wherein the clock information comprises step values;

When the step value is odd, adjusting the system time of the slave equipment, and stopping adjusting the system time when the time deviation is within a first preset range;

or when the step value is even, adjusting the system time of the slave device, and when the time deviation is within a second preset range, stopping adjusting the system time.

7. The method according to any one of claims 1 to 6, further comprising:

acquiring parity of a node number corresponding to the slave device;

Determining a positive value and a negative value corresponding to the time deviation based on the parity of the node number; each slave device comprises a corresponding node number, and the positive and negative values corresponding to the time deviation of two slave devices of adjacent node numbers are different.

8. A time synchronization device, the device comprising:

the first information acquisition module is used for acquiring a plurality of groups of transmission information obtained by calculation between the master equipment and the slave equipment; wherein the transmission information comprises time deviation and network delay;

the second information acquisition module is used for acquiring average time deviation and average network delay between the master equipment and the slave equipment based on the multiple groups of transmission information;

A third information obtaining module, configured to adjust a system time of the slave device based on the average time deviation, obtain a network delay between the master device and the slave device after adjustment, and obtain a time deviation between the master device and the slave device when a difference between the network delay and the average network delay is smaller than a first threshold;

And the time synchronization module is used for acquiring the deviation between the system time and the master clock, adjusting the system time based on the deviation, and synchronizing the system time of the slave device based on the time deviation under the condition that the time deviation between the master device and the slave device is smaller than a second threshold value.

9. An electronic device, comprising:

at least one processor;

A memory for storing the at least one processor-executable instruction;

wherein the at least one processor is configured to execute the instructions to implement the method of any of claims 1-7.

10. A computer readable storage medium, characterized in that instructions in the computer readable storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the method of any one of claims 1-7.