CN114389735A - A Clock Synchronization Method Based on IEEE802.1AS Redundant Master Clock - Google Patents

Abstract

The invention relates to the technical field of industrial time-sensitive network communication, in particular to a clock synchronization method based on an IEEE802.1AS redundant master clock, which comprises the steps that a synchronous centralized control node receives clock source parameter information reported by each time-sensitive in a clock synchronization domain to obtain a redundant clock sequence table and a current optimal master clock; the synchronous centralized control node issues the redundant clock sequence list and the current optimal master clock to other nodes, and the nodes determine the master-slave state of the local clock according to the issued master clock sequence list information; the node adopts a hardware timestamp as clock counting, and simultaneously adopts a timestamp precision compensation mechanism to compensate the timestamp; each time-sensitive node in the clock synchronization domain considers the adjacent frequency ratio and the asymmetry to model and solve a time delay error for time delay measurement, and clock synchronization is completed; the invention reduces the synchronization error accumulated in the time consumed by reselection, improves the reliability of clock synchronization, and reduces the synchronization error caused by factors such as adjacent frequency ratio, asymmetry and the like.

Description

A Clock Synchronization Method Based on IEEE802.1AS Redundant Master Clock

technical field

The invention relates to the technical field of industrial time-sensitive network communication, in particular to a clock synchronization method based on an IEEE802.1AS redundant master clock.

Background technique

The Industrial Internet is the core of smart manufacturing and smart factories, connecting all aspects of industrial manufacturing, aiming to improve manufacturing efficiency, optimize production management, and promote the transformation and upgrading of industrial manufacturing and the sustained and rapid development of the national economy. The requirement of deterministic delay of data transmission for emerging time-sensitive services poses no small challenge to the existing Ethernet. The IEEE802.1 working group proposed the time-sensitive networking (TSN) protocol. TSN is based on the wired Ethernet based on IEEE802.3, and adds and expands a series of functions and protocol standards to improve the ability of Ethernet to support real-time applications. It can not only provide time-sensitive services with bounded and highly reliable data transmission services, but also provide high-speed but best-effort transmission services for non-time-sensitive services.

IEEE 802.1AS works on the data link layer of full-duplex Ethernet as the premise of TSN technology, and realizes high-precision clock synchronization by means of time stamp transmission. Compared with the traditional NTP and SNTP synchronization protocols, the IEEE802.1AS protocol unifies the clock types and adopts a peer-to-peer delay mechanism, which can provide sub-microsecond synchronization accuracy.

The precision of the time stamp determines the precision of synchronization. In the IEEE802.1AS protocol that uses time stamps for information transmission and calculation, high precision time stamps play a crucial role in improving the synchronization precision. For example, when the function is called to extract the time count in the software implementation, because the function extraction requires a certain time, the extracted time count has a large deviation from the actual time, so the clock synchronization accuracy realized by software is mostly not as good as the synchronization accuracy realized by hardware. At the same time, the asymmetry of the link is also one of the main factors affecting the synchronization accuracy of the IEEE802.1AS protocol. Since the protocol adopts the peer-to-peer delay mechanism, and the actual link has different configurations and different data processing delays between nodes, the round-trip link delay between nodes is often asymmetric, resulting in a certain delay error and This error increases as the asymmetry deepens. In addition, ideally, the real-time clock does not change with the passage of time and the influence of the external environment, but in fact, the crystal oscillator has problems such as temperature drift and inherent jitter, which may cause the instability of the clock source and cause errors. For example, a clock crystal oscillator with a stability of ±100ppm can theoretically generate a maximum cumulative error of 12.5μs when synchronizing every 125ms. Therefore, when the master clock node fails, the synchronization error of the master and slave nodes will also accumulate in the long time required for each node to re-execute BMCA to select the best master clock. Before the best master clock is selected, the master and slave nodes may even exceed The synchronization error of 1us affects the deterministic delay transmission of time-sensitive services.

To sum up, the existing clock synchronization technology lacks a specific reliability scheme to reduce the clock error in the time consumed by re-selection after the failure of the master clock node, and the premise of the protocol for measuring path delay on the basis of symmetric links is not practical. sex. Therefore, improving synchronization reliability and reducing errors caused by link asymmetry to improve synchronization accuracy have become the focus of research.

SUMMARY OF THE INVENTION

Based on the problems existing in the existing protocols, the present invention provides a clock synchronization method based on the IEEE802.1AS redundant master clock, which specifically includes the following steps:

The synchronization centralized control node receives the clock source parameter information reported by each time-sensitive in the clock synchronization domain to obtain the redundant clock sequence list and the current best master clock;

The synchronization centralized control node sends the redundant clock sequence list and the current best master clock to other nodes, and the node determines the master-slave state of the local clock according to the information of the master clock sequence list sent;

The node uses the hardware timestamp as the clock count, and uses the timestamp precision compensation mechanism to compensate the timestamp;

In the clock synchronization domain, each time-sensitive node considers the adjacent frequency ratio and asymmetry to model the delay measurement to solve the delay error and complete the clock synchronization.

Further, the process of generating the redundant clock sequence list and selecting the current best master clock includes:

The synchronization centralized control node receives the clock source parameter information reported by each time-sensitive node in the clock synchronization domain, and the clock source parameter information at least includes the clock source type, the estimated clock error value, and the clock identification number;

The data set comparison algorithm is used to compare the clock source data set parameters reported by each node in turn, and the clock of the optimal node is used as the optimal clock, and the clocks of the two sub-optimal nodes are used to generate a redundant clock sequence table.

Further, each time-sensitive node in the clock synchronization domain receives the redundant clock list and the best master clock information to confirm the clock tree structure, that is, when a new node joins, the pros and cons of the node are calculated according to the clock source parameter information reported by the node. Sorting, and adding the node to the clock quality ranking table of the node according to the sorting, encapsulating the table into the redundant clock sequence table and sending the message and covering the previously sent message.

Further, the process of compensating the timestamp by using the timestamp precision compensation mechanism includes the following steps:

When the data passes through the input processing module, according to the different message types, the receiver timestamp t2 when the request message is received, the receiver timestamp t4 when the response message is received, and the receiver timestamp ts when the synchronization message is received are respectively recorded. The local time is extracted from the module to obtain the entry delay value;

After the data is sent from the synchronization module, when the data processing module is output, the sender’s timestamp t1 when sending the request message, the sender’s timestamp t3 when sending the response message, and the sender’s timestamp when sending the synchronization message are extracted according to different message types. Timestamp tm, compared with the local time to obtain the exit delay value;

The message key information extraction module performs timestamp compensation according to the calculated ingress delay value and the extracted egress delay value;

Send the corrected timestamp to the delay measurement module or the synchronization correction module.

Further, modifying the sending timestamp and the receiving timestamp includes:

egressTimestamp=egressMeasuredTimestamp+egressLatency

igressTimestamp=igressMeasuredTimestamp-igressLatency

Among them, egressTimestamp is the sending timestamp, igressTimestamp is the receiving timestamp, egressMeasuredTimestamp is the sending timestamp recorded by the synchronization module, egressLatency is the egress delay value, igressMeasuredTimestamp is the receiving timestamp recorded by the synchronization module, and igressLatency is the entry delay value.

Further, each time-sensitive node in the clock synchronization domain considers the adjacent frequency ratio and asymmetry to model the delay measurement and solve the delay error including:

Among them, Delay_reply is the delay obtained by solving; f _ratio is the frequency ratio of adjacent nodes; t1 is the timestamp of the sender when sending the transmission delay request message; t2 is the time stamp of the receiver's clock when receiving the transmission delay request message ; t3 is the timestamp of the sender when sending the response message, t4 is the timestamp of the receiver's clock when the response message is received; SDR is the degree of symmetry.

Further, in order to obtain a more accurate time delay, multiple time delay measurement calculations are performed, and the average delay measurement value calculated for multiple times is taken as the time delay, then the average delay measurement value obtained by the k-th calculation is expressed as:

D _avg,k =αD _avg,k−1 +(1−α)D _k−1 ;

，M是测量次数。Among them, D _k-1 is the k-1 delay measurement value, D _avg,k is the average delay measurement value calculated at the kth time; α is the exponential weight factor, expressed as

, M is the number of measurements.

Further, the adjacent node frequency ratio f _ratio is expressed as:

Among them, t ₃ (k) represents the time stamp of the sender when sending the response message at time k, t ₃ (k-1) represents the time stamp of the sender when sending the response message at time k-1; t ₄ (k) represents The timestamp of the receiver's clock when the response message is received at time k, and t ₄ (k-1) represents the timestamp of the receiver's clock when the response message is received at time k-1.

Further, the symmetry degree SDR is expressed as:

Wherein, Trans_request represents the time required to transmit the delay request message, expressed as Trans_reply=t ₄ -t ₃ ; Trans_reply represents the time required to transmit the delay response message, expressed as Trans_request=t ₂ -t ₁ .

By adopting the redundant master clock sequence, the present invention enables each node of the global network to quickly reselect the best master clock according to the redundant master clock sequence when the master clock node fails, thereby reducing the synchronization error accumulated in the time spent on re-selection At the same time, the reliability of clock synchronization is improved; by considering the adjacent frequency ratio, asymmetry and other factors, the path delay measurement value is modeled and calculated to reduce the synchronization error caused by the above factors; based on hardware circuit clock counting and using timestamps The precision compensation mechanism reduces the deviation between the recorded timestamp and the actual time to improve the synchronization precision.

Description of drawings

Fig. 1 is the industrial TSN network model in the embodiment of the present invention;

Fig. 2 is the flow chart of the industrial time-sensitive network clock synchronization method based on redundant clock in the present invention;

Fig. 3 is the master clock sequence table format in the embodiment of the present invention;

Fig. 4 is the flow chart of updating master clock sequence table of synchronous centralized control node in the present invention;

Fig. 5 is the continuous delayrep message principle diagram adopted in the present invention;

6 is a flow chart of the node path delay measurement adopted in the present invention;

Fig. 7 is the time stamp error principle diagram adopted in the present invention;

FIG. 8 is a schematic diagram of the link delay measurement adopted in the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

Fig. 1 is the industrial TSN network model adopted by the example of the present invention; this case considers the industrial TSN network composed of multiple terminals and bridges and a synchronous centralized control node as shown in Fig. 1 . Each node reports the clock source parameter information to the synchronization centralized control node to select an optimal master clock node, and use this node as the root node to generate the clock spanning tree as shown in the figure.

2 is a flowchart of an industrial time-sensitive network clock synchronization method based on redundant clocks in an example of the present invention. The clock synchronization method of the present invention improves synchronization reliability through a redundant clock sequence table, that is, if the master clock has a problem, it can be The master clock is reselected in sequence; the synchronization error is reduced by the time stamp compensation mechanism and path delay measurement compensation to improve the synchronization accuracy. The clock synchronization correction value of the IEEE802.1AS protocol is calculated by the time stamp and the path delay measurement value. Considering The above factors can reduce the delay measurement error and thus reduce the synchronization error; the method of the present invention ensures the reliability of clock synchronization while improving the synchronization accuracy, and the method method comprises the following steps:

Step 1: The synchronization centralized control node receives the clock source parameter information reported by each time-sensitive node in the clock synchronization domain, and selects the redundant clock sequence and the current best master clock through the data set comparison algorithm. The synchronization centralized control node sends the redundant clock sequence and the current best master clock information to all the time-sensitive nodes in the clock synchronization domain through centralized configuration. Figure 3 shows the format of the master clock sequence table generated by the synchronization centralized control node. As shown in the figure, the table entry is composed of the node's clock identification number and its corresponding master clock sequence order.

Step 2: The node determines the master-slave state of the local clock according to the master clock sequence table information issued. Figure 4 is the flow chart of the synchronization centralized control node updating the master clock sequence table after the new node joins. As shown in the figure, the newly added node reports itself The clock source parameter information is sent to the synchronization centralized control node, and the synchronization centralized control node compares the node information with the master clock sequence table entry in turn. The order of entries in this order is collectively shifted back by one. If all options are compared and no one is inferior to the new node, a new entry generated by this node is added to the end of the original master clock sequence entry.

Step 3: The node models the link delay measurement considering the adjacent frequency ratio and asymmetry, thereby reducing the synchronization error caused by the above factors. The specific process includes:

Differences in propagation and transmission delays must be known when using asymmetric traffic, and since the synchronization process of time-sensitive networks involves different node models, dynamic data rates, and asymmetric properties, it is necessary to propose a model to handle these variables.

1) Symmetry SDR

Among them, Trans_request and Trans_reply are the time required to transmit delay request message and response message respectively, including transmission delay and data propagation delay

Trans_reply=t ₄ -t ₃

Trans_request=t ₂ -t ₁

Among them, t1 and t2 are the time stamps of the sender's and receiver's clocks when the transmission delay request message is sent and received, respectively. Similarly, t3 and t4 are the timestamps of the sender's and receiver's clocks when the reply message was sent and received.

Transtime _request is the transmission time of the request message, Transtime _reply is the transmission time of the response message, and the deterministic time difference Δ _{fixed_time} is equal to the absolute value of the subtraction of the two.

Δ _{fixed_time} = |Transtime _request -Transtime _reply |

In the wired scenario, the data propagation time is basically fixed, and the asymmetry of the data link is mainly reflected in the difference in the transmission time of the packets within the node.

t ₄ -t ₃ =(t ₂ -t ₁ )+ _{Δfixed_time}

Available SDR ratios:

2) Adjacent node frequency ratio f _ratio :

In the actual measurement, timestamps t1 and t4 use the clock source of the sender node as the counting reference, and t2 and t3 use the clock source of the responder as the counting reference. If the frequency of the crystal oscillator source of the two clock sources is different, a delay measurement will be given. bring some errors. Therefore, in order to obtain accurate synchronization time on the slave clock, the frequency ratio f _ratio of adjacent time-aware devices is calculated to compensate for the drift time of the local clock.

Figure 5 is a schematic diagram of continuous delayrep messages. As shown, the value of f _ratio can be calculated by the last two subsequent delayrep messages:

where t ₃ (k) and t ₃ (k-1) are the receiving node clock and the previous timestamp of the delayrep message in the sending adjacent time-aware node, respectively. Similarly, t ₄ (k) and t ₄ (k-1) are the current timestamp values of the same delayrep message.

3) Calculate the Delay_reply value

The result of one measurement may have a large deviation. In order to calculate a more accurate delay measurement value, it is necessary to perform multiple calculations:

D _avg , _k =αD _avg , _k-1 +(1-α)D _k-1

Wherein, D _k-1 is the k-1 th delay measurement, D _avg,k is the average delay measurement value calculated for the k th time, α is an exponential weighting factor, and M is the number of measurements.

Figure 6 is the flow chart of the node path delay measurement. As shown in the figure, the node first calculates the adjacent frequency ratio and asymmetry after receiving the four time stamps, and then substitutes it into the established delay measurement value model to obtain the exact link The link delay value is calculated according to the average calculation method to obtain the finally adopted link delay measurement value.

In this embodiment, t1 to t4 are calculated based on the time stamps generated by the message exchange process of delay measurement. As shown in Figure 8, the talker sends a path delay request message and records the time stamp t1, and the listener receives the request message and records the time stamp t2, then the listener returns a response message with timestamp t2 and records the sending time t3. After sending the response message, the listener encapsulates t3 to follow the message and sends it to the talker. When the talker receives the response message with t2 Record the received timestamp t4, and calculate the path delay value through the received or recorded timestamp t1\t2\t3\t4.

Step 4: The node uses the hardware timestamp as the clock count, and adopts the timestamp precision compensation mechanism to reduce the error between the recording time and the actual time. Fig. 7 is a schematic diagram of the time stamp error used in the present invention. As shown in the figure, there is an output delay or input delay error between the time stamp recording time of data transmission and reception and the actual time, which reduces the accuracy of the time stamp and further reduces the accuracy of the time stamp. Reduced synchronization accuracy. The present invention adopts the time stamp precision compensation mechanism as follows:

egressTimestamp=egressMeasuredTimestamp+egressLatency

igressTimestamp=igressMeasuredTimestamp-igressLatency

Among them, egressTimestamp is the sending timestamp, igressTimestamp is the receiving timestamp, egressMeasuredTimestamp is the sending timestamp recorded by the synchronization module, egressLatency is the egress delay value, igressMeasuredTimestamp is the receiving timestamp recorded by the synchronization module, and igressLatency is the entry delay value.

The specific implementation steps are as follows:

Step 1: When the data passes through the input processing module, record the received timestamp and encapsulate it into the header, and extract the header timestamp and local time in the synchronization module to calculate the entry delay value.

Step 2: After the data is sent from the synchronization message module, when outputting the data processing module, extract the sending time stamp and the local time stamp carried by the message to calculate the egress delay value and encapsulate it into the reserved value of the data message.

Step 3: The message key information extraction module corrects the obtained time stamp according to the calculated ingress delay value and the extracted egress delay value according to the above formula, and sends the modified time stamp to the delay measurement module or the synchronization correction module For calculation of delay measurements and clock skew.

Although the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications and substitutions can be made in these embodiments without departing from the principle and spirit of the invention and modifications, the scope of the present invention is defined by the appended claims and their equivalents.

Claims (9)

1. A clock synchronization method based on IEEE802.1AS redundant master clock is characterized by comprising the following steps:

the synchronous centralized control node receives clock source parameter information reported by each time sensitivity in a clock synchronization domain to obtain a redundant clock sequence table and a current optimal master clock;

the synchronous centralized control node issues the redundant clock sequence list and the current optimal master clock to other nodes, and the nodes determine the master-slave state of the local clock according to the issued master clock sequence list information;

the node adopts a hardware timestamp as clock counting, and simultaneously adopts a timestamp precision compensation mechanism to compensate the timestamp;

and each time-sensitive node in the clock synchronization domain considers the adjacent frequency ratio and the asymmetry degree to model and solve the delay error for the delay measurement, thereby completing the clock synchronization.

2. The clock synchronization method based on IEEE802.1AS redundant master clock as claimed in claim 1, wherein the process of generating the redundant clock sequence list and selecting the current best master clock comprises:

the synchronous centralized control node receives clock source parameter information reported by each time sensitive node in a clock synchronous domain, wherein the clock source parameter information at least comprises a clock source class, a clock error estimation value and a clock identification number;

and sequentially comparing the clock source data set parameters reported by each node by adopting a data set comparison algorithm, taking the clock of the optimal node as the optimal clock, and generating a redundant clock sequence list by using the clocks of the two suboptimal nodes.

3. The clock synchronization method according to claim 2, wherein each time-sensitive node in the clock synchronization domain receives the redundant clock list and the best master clock information to confirm the clock tree structure, that is, when a new node is added, the priority ranking of the node is calculated according to the clock source parameter information reported by the node, and the node is added to the clock priority ranking list of the node according to the ranking, and the list is encapsulated into the redundant clock sequence list message to be issued and covers the previously issued message.

4. The clock synchronization method based on IEEE802.1AS redundant master clock as claimed in claim 1, wherein the process of compensating the timestamp by using the timestamp accuracy compensation mechanism comprises the following steps:

when data passes through the input processing module, respectively recording a receiver timestamp t2 when a request message is received, a receiver timestamp t4 when a response message is received and a receiver timestamp ts when a synchronous message is received according to different message types, and extracting local time in the synchronous module for comparison to obtain an entry delay value; (ii) a

After the data is sent from the synchronization module, when the data processing module is output, according to different message types, a sender timestamp t1 when the request message is sent is extracted, a sender timestamp t3 when the response message is sent and a sender timestamp tm when the synchronization message is sent are compared with local time to obtain an outlet delay value;

the message key information extraction module carries out timestamp compensation according to the calculated entry delay value and the extracted exit delay value;

and sending the corrected time stamp to a time delay measurement module or a synchronous correction module.

5. The clock synchronization method based on IEEE802.1AS redundant master clock as claimed in claim 1, wherein the correcting the transmission time stamp and the reception time stamp comprises:

egressTimestamp＝egressMeasuredTimestamp+egressLatency

igressTimestamp＝igressMeasuredTimestamp-igressLatency

wherein, egressTimestamp is the transmission timestamp, igressTimestamp is the receipt timestamp, egressMeasuredTimestamp is the transmission timestamp of synchronization module record, egressLatency is the exit delay value, igresMeasuredTimestamp is the receipt timestamp of synchronization module record, igressLatency is the entry delay value.

6. The clock synchronization method based on the IEEE802.1AS redundant master clock as claimed in claim 1, wherein the step of solving the delay error for the delay measurement modeling by each time-sensitive node in the clock synchronization domain considering the adjacent frequency ratio and the asymmetry degree comprises:

wherein Delay _ reply is time Delay obtained by solving; f. of_ratioIs the frequency ratio of the adjacent nodes; t1 is the timestamp of the sender when sending the transmission delay request message; t2 is the timestamp of the receiver clock when receiving the transmission delay request message; t3 is the timestamp of the sender when sending the response message, and t4 is the timestamp of the receiver clock when receiving the response message; SDR is the degree of symmetry.

7. The clock synchronization method according to claim 1, wherein to obtain more accurate delay, a plurality of delay measurement calculations are performed, and the average delay measurement value calculated a plurality of times is taken as the delay, and then the average delay measurement value calculated at the kth time is expressed as:

D_avg,k＝αD_avg,k-1+(1-α)D_k-1；

wherein D is_k-1Is the k-1 th time delay measurement, D_avg,kIs the average delay measurement value obtained by the k-th calculation; alpha is an exponential weighting factor, expressed as

M is the number of measurements.

8. The clock synchronization method based on IEEE802.1AS redundant master clock as claimed in claim 1, wherein the frequency ratio f of neighboring nodes is_ratioExpressed as:

wherein, t₃(k) Time stamp, t, of the sender indicating when the response packet was sent at time k₃(k-1) indicating the timestamp of the sender when the response message is sent at the k-1 moment; t is t₄(k) Time stamp, t, of the receiver clock indicating when the response message was received at time k₄And (k-1) represents the timestamp of the receiver clock when the response message is received at the time of k-1.

9. The clock synchronization method based on IEEE802.1AS redundant master clock as claimed in claim 1, wherein the symmetry SDR is expressed as:

wherein, the Trans _ request represents the time required for transmitting the delay request message, and represents that the Trans _ reply is t₄-t₃(ii) a Trans _ reply represents the time required for transmitting the delayed response message, and is represented as Trans _ request ═ t₂-t₁。

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