CN104601269B - Master-salve clock synchronous method and system - Google Patents

Abstract

The invention discloses a kind of master-salve clock synchronous method and system, this master-salve clock synchronous method includes: receives sync message from clock and records the T time of reception₂；From clock from synchronizing to follow acquisition moment T message₁T1+t4, t1 are the moment that sync message arrives the first protocol conversion apparatus being connected with master clock, and t4 is the moment that sync message leaves the second protocol conversion equipment being connected with from clock；Send from clock and postpone request message and record delivery time T₃；From the delay response message received, moment T is obtained from clock₄+ t1 ' t4 ', t1 ' are to postpone request message to arrive the moment of second protocol conversion equipment, and t4 ' is to postpone request message to leave the moment of the first protocol conversion apparatus；From clock according to T₂、T₃、T₁T1+t4 and T₄+ t1 ' t4 ' calculates the time deviation of master-salve clock.Improve the computational accuracy of master-salve clock time deviation.

Description

Master-slave clock synchronization method and system

technical field

The present invention relates to the technical field of communication, in particular to a master-slave clock synchronization method and system.

Background technique

With the construction of the smart grid, new services such as protection, automatic services, and line status real-time sensing devices in the power system have put forward higher requirements for time synchronization, but the time synchronization systems configured in various substations and power plants have not yet been networked. It is difficult to achieve a high degree of uniformity between the various substations.

Based on the current technological development and network status, using the Precision Time Protocol (PTP) technology to transmit time synchronization signals via the Synchronous Digital Hierarchy (SDH) network is one of the best solutions. Among them, the PTP technology is that the slave clock can obtain the accurate value T1 of the sending time of the Sync message from the Follow_Up message. The clock can obtain the precise time T4 when the main clock receives the Delay_Req message from the Delay_Resp message. The premise of calculating the time offset between the master and slave clocks is that the bidirectional transmission routes are symmetrical.

In the actual environment, the two-way path of the SDH network transmission link is inconsistent, which inevitably introduces a delay difference, and the original PTP algorithm is not fully applicable. Moreover, the PTP technology transmits Ethernet packets, and the SDH network transmits E1-based third-order high-density bipolar codes (High Density Bipolar of Order 3, referred to as HDB3 codes), which require protocol conversion during transmission, but The transmission rates of the two protocols differ greatly, and a certain time delay will inevitably be introduced, and the conversion time delays of different protocol conversion devices are inconsistent. Therefore, in the process of transmitting PTP time synchronization signals in the SDH network, the time delay caused by the protocol conversion and the asymmetry of the two-way transmission link affects the calculation accuracy of the time deviation between the master and slave clocks, which in turn affects the accuracy of the transmission time synchronization signal.

Contents of the invention

The present invention provides a master-slave clock synchronization method and system to at least solve the problem of protocol conversion delay and inconsistent bidirectional transmission path delay in the current process of transmitting time synchronization signals via SDH network using PTP technology, which affects the calculation of time deviation A question of precision.

According to one aspect of the present invention, a master-slave clock synchronization method is provided, including: the slave clock receives the synchronization message sent by the master clock at the _first time T1, and records the second time T when the synchronization message is received ₂ ; the slave clock receives the synchronization following message sent by the master clock, and obtains the sending time T ₁ -t1+t4 from the synchronization following message, wherein the sending time T ₁ -t1+t4 is The second protocol conversion device adjusts the _first time T1 to obtain the time, and the second protocol conversion device is connected to the slave clock; t1 is the arrival of the synchronization message at the first time connected to the master clock The time of a protocol conversion device; t4 is the time when the synchronization message leaves the second protocol conversion device; the slave clock sends a delay request message to the master clock, and records the time of sending the delay request message At the _third moment T3, the master clock receives the delay request message at the _fourth moment T4; the slave clock receives the delay response message sent by the master clock, and receives the delay response message from the delay response message Obtaining the receiving time T ₄ +t1'-t4', wherein the receiving time T ₄ +t1'-t4' is the time obtained after the second protocol conversion device adjusts the _fourth time T4, t1' is the time when the delay request message arrives at the second protocol conversion device, and t4' is the time when the delay request message leaves the first protocol conversion device; the slave clock is based on the second time T ₂ , the third time T ₃ , the sending time T ₁ -t1+t4 and the receiving time T ₄ +t1'-t4' calculate the time offset between the master clock and the slave clock, And correct the time of the slave clock according to the time deviation.

In one embodiment, the slave clock calculates the time offset offset between the master clock and the slave clock according to the following formula: offset=(T ₂ -T ₁ +T ₃ -T ₄ +t4'-t1' +t1-t4)/2.

In one embodiment, before the slave clock receives the synchronization message sent by the master clock at the _first time T1, the method further includes: the first protocol conversion device receives the synchronization message, and records the synchronization message The time t1 when the text arrives at the first protocol conversion device, and outputs the synchronization message through the SDH network; the second protocol conversion device receives the synchronization message and sends the synchronization message to the slave clock , and record the time t4 when the synchronization message leaves the second protocol conversion device.

In an embodiment, before the slave clock receives the synchronization follow message sent by the master clock, the method further includes: the first protocol conversion device receives the synchronization follow message, and converts the synchronization follow message to The first moment T1 carried in the message is adjusted to T1 _{- t1} , and the synchronization following message is output through the SDH network; the second protocol conversion device receives the synchronization following message, and converts the synchronization following message to The time T ₁ -t1 carried in the following message is adjusted to T ₁ -t1+t4, and the synchronization following message is sent to the slave clock.

In one embodiment, before the slave clock receives the delay response message sent by the master clock, the method further includes: the second protocol conversion device receives the delay request message, and records the delay request The time t1' when the message arrives at the second protocol conversion device, and output the delay request message through the SDH network; the first protocol conversion device receives the delay request message and sends the delay request message to the master clock, and record the time t4' when the delay request message leaves the first protocol conversion device; after receiving the delay request message, the master clock outputs the delay response message; The first protocol conversion device receives the delayed response message, adjusts the _fourth time T4 carried in the delayed response message to T4 _- t4', and outputs the delayed response message through the SDH network ; The second protocol conversion device receives the delayed response message, adjusts the time T ₄ -t4' carried in the delayed response message to T ₄ +t1'-t4', and sends the delayed response message text sent to the slave clock.

According to another aspect of the present invention, a master-slave clock synchronization system is provided, including: a master clock, a first protocol conversion device, a second protocol conversion device, and a slave clock; the first protocol conversion device and the second protocol conversion device The message is transmitted between the protocol conversion devices through the SDH network; the master clock is used to send a synchronization message, a synchronization follow message and a delay response message to the slave clock, and receive a delay request message from the slave clock , wherein the synchronization following message carries the first time T ₁ when the master clock sends the synchronization message, and the delay response message carries the time when the master clock receives the delay request message The _fourth moment T4: the first protocol conversion device is connected to the master clock, and the first protocol conversion device includes: a first recording module and a first adjustment module; wherein, the first recording module uses record and store the time t1 when the synchronization message arrives at the first protocol conversion device and the time t4' when the delay request message leaves the first protocol conversion device; the first adjustment module is configured to The first time T ₁ carried in the synchronization following message is adjusted to T ₁ -t1, and the fourth time T ₄ carried in the delayed response message is adjusted to T ₄ -t4'; the second protocol The conversion device is connected to the slave clock, and the second protocol conversion device includes: a second recording module and a second adjustment module; wherein, the second recording module is used to record and store the synchronization message leaving the The time t4 of the second protocol conversion device and the time _t1 ' when the delay request message arrives at the second protocol conversion device; the second adjustment module is used to set the time T1 carried by the synchronization following message -t1 is adjusted to T ₁ -t1+t4, and the time T ₄ -t4' carried by the delayed response message is adjusted to T ₄ +t1'-t4'; the slave clock includes: a first transceiver module and a calculation module; wherein, the first transceiver module is configured to receive the synchronization message, and record the second moment T ₂ when the synchronization message is received; receive the synchronization following message, and follow the synchronization message from the Obtain the adjusted sending time T ₁ -t1+t4 of the synchronization message from the master clock in the message; send the delay request message, and record the third time T ₃ when sending the delay request message ; Receive the delay response message, and obtain the adjusted receiving time T ₄ +t1'-t4' when the master clock receives the delay request message from the delay response message; the calculation module , _used to _calculate the _{master clock} and the time deviation between the slave clocks, and correct the time of the slave clocks according to the time deviation.

In one embodiment, the calculation module calculates the time offset offset between the master clock and the slave clock according to the following formula: offset=(T ₂ -T ₁ +T ₃ -T ₄ +t4'-t1' +t1-t4)/2.

In one embodiment, the first protocol conversion device further includes: a second transceiver module, configured to receive and forward the synchronization message, the synchronization following message, the delay request message and the delay response message.

In one embodiment, the second protocol conversion device further includes: a third transceiver module, configured to receive and forward the synchronization message, the synchronization following message, the delay request message and the delay response message.

Through the master-slave clock synchronization method and system of the present invention, in the process of transmitting the PTP time synchronization signal through the E1 channel of the SDH network, the protocol conversion delay and the asymmetric delay of the bidirectional transmission path inconsistency are considered, and the protocol conversion device and the master-slave The clock association mechanism improves the calculation accuracy of the time deviation between the master and slave clocks, and the clock synchronization based on the time deviation is also more reliable and the implementation method is simple.

Description of drawings

The accompanying drawings described here are used to provide a further understanding of the present invention, and constitute a part of the application. The schematic embodiments of the present invention and their descriptions are used to explain the present invention, and do not constitute a limitation to the present invention. In the attached picture:

Fig. 1 is the flowchart of the master-slave clock synchronization method of the embodiment of the present invention;

Fig. 2 is a schematic diagram of the transmission of a protocol message according to an embodiment of the present invention;

FIG. 3 is a structural block diagram of a master-slave clock synchronization system according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The embodiment of the present invention provides a master-slave clock synchronization method, which can solve the problem of protocol conversion delay and bidirectional transmission link asymmetry introduced in the SDH network transmission of PTP time synchronization signals, and obtains the master-slave clock synchronization method. precise time offset.

The master clock sends Ethernet messages based on PTP technology, which are converted into E1 signals by the E1/Ethernet protocol conversion device (located on the side of the master clock, equivalent to the first protocol conversion device described below), and then transmitted in the SDH network , the E1 signal is converted into an Ethernet message through the E1/Ethernet protocol conversion device (located on the side of the slave clock, which is equivalent to the following second protocol conversion device), and the Ethernet message is received by the slave clock; the slave clock adopts the same The principle is to send PTP messages to the master clock to realize the transmission of synchronization messages between the master and slave clocks.

Fig. 1 is the flowchart of the master-slave clock synchronization method of the embodiment of the present invention, as shown in Fig. 1, the method comprises the following steps:

Step S101 , the slave clock receives a synchronization message (Sync) sent by the master clock at the first time T ₁ , and records the second time T ₂ when the synchronization message is received.

Step S102, the slave clock receives the synchronization follow-up message (Follow_Up) sent by the master clock, and obtains the sending time T ₁ -t1+t4 from the synchronization following message, wherein the sending time T ₁ -t1+t4 is the second protocol conversion The time obtained after the device adjusts the _first time T1, the second protocol conversion device is connected to the slave clock; t1 is the time when the synchronization message arrives at the first protocol conversion device connected to the master clock; t4 is the time when the synchronization message leaves the first protocol conversion device The moment of the two-protocol conversion device.

Step S103, the slave clock sends a delay request message (Delay_Req) to the master clock, and records the third time T ₃ when the delay request message is sent, wherein the master clock receives the delay request message at the fourth time T ₄ .

Step S104, the slave clock receives the delay response message (Delay_Resp) sent by the master clock, and obtains the reception time T ₄ +t1'-t4' from the delay response message, wherein the reception time T ₄ +t1'-t4' is The time obtained by the second protocol conversion device after adjusting the _fourth time T4, t1' is the time when the delay request message arrives at the second protocol conversion device, and t4' is the time when the delay request message leaves the first protocol conversion device.

Step S105, the slave clock calculates the time offset between the master clock and the slave clock according to the second time T ₂ , the third time T ₃ , the sending time T ₁ -t1+t4 and the receiving time T ₄ +t1'-t4', and Correct the time of the slave clock according to the time offset.

Through the above-mentioned master-slave clock synchronization method, in the process of transmitting the PTP time synchronization signal through the E1 channel of the SDH network, the protocol conversion delay and the asymmetric delay of the bidirectional transmission path inconsistency are considered, and the association mechanism between the protocol conversion device and the master-slave clock is considered. , the calculation accuracy of the time deviation between the master and slave clocks is improved, and the clock synchronization based on the time deviation is also relatively reliable, and the implementation method is simple.

In one embodiment, the slave clock calculates the time offset offset between the master clock and the slave clock according to the following formula: offset=(T ₂ -T ₁ +T ₃ -T ₄ +t4'-t1'+t1-t4)/ 2. The origin of this formula will be described below.

When the time synchronization signal of the master clock reaches the slave clock through the E1/Ethernet protocol conversion device and the SDH network, the transmission diagram of each protocol message is shown in Figure 2.

In Figure ₂ , it is assumed that the Sync message is sent from the main clock and passes through the E1/Ethernet protocol conversion device A. The conversion delay value of △T ₂ .

Assuming that the Delay_Req message is sent from the slave clock, the conversion delay value of the E1/Ethernet protocol conversion device B is △T ₄ , the path delay of the SDH network transmission is delay2, and the conversion delay value of the E1/Ethernet protocol conversion device A is is ΔT ₃ .

The calculation method of the time deviation of the master-slave clock in the existing PTP technology is based on the premise that the two-way transmission route is symmetrical, that is, the slave clock can obtain the time T 1 when the master clock sends the Sync message from the Follow_Up message, and the slave clock measures its reception time T ₁ . The time when the Sync message arrives is T ₂ , the time when the slave clock sends the Delay_Req message is T ₃ , and the slave clock can obtain the time T ₄ when the master clock receives the Delay_Req message from the Delay_Resp message. When the two-way transmission route is symmetrical, the relationship between the time offset offset between the master and slave clocks and the transmission path delay value delay can be obtained as follows:

$\left\{\begin{array}{c}{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; l</span>}\mathrm{<span\; class="notranslate">\; a</span>}\mathrm{<span\; class="notranslate">\; the\; y</span>}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; t</span>}\\ {\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; l</span>}\mathrm{<span\; class="notranslate">\; a</span>}\mathrm{<span\; class="notranslate">\; the\; y</span>}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; t</span>}\end{array}\right.<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

In the process of using the SDH network to transmit the time synchronization signal based on PTP technology, considering the E1/Ethernet protocol conversion delay and the inconsistency of the SDH network bidirectional transmission path, the formula (1) is modified as:

$\left\{\begin{array}{c}{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; \&Delta;T</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; \&Delta;T</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; l</span>}\mathrm{<span\; class="notranslate">\; a</span>}\mathrm{<span\; class="notranslate">\; the\; y</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; t</span>}\\ {\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; l</span>}\mathrm{<span\; class="notranslate">\; a</span>}\mathrm{<span\; class="notranslate">\; the\; y</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; \&Delta;T</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; \&Delta;T</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; t</span>}\end{array}\right.<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

Organized:

offset＝(T ₂ -T ₁ +T ₃ -T ₄ +delay2-delay1+ΔT ₃ +ΔT ₄ -ΔT ₁ -ΔT ₂ )/2 (3)

It can be seen from Figure 2 that the time when the Sync message is sent from the main clock and arrives at the E1/Ethernet protocol conversion device A is t1, and the time when the protocol conversion is completed and ready to be sent to the SDH network is t2, then the conversion delay value obtained from t2-t1 is △T ₁ . Similarly, the time when the Sync message arrives at the E1/Ethernet protocol conversion device B is t3, the time when the protocol conversion is completed and ready to be sent to the slave clock is t4, and the conversion delay value ΔT ₂ is obtained from t4-t3, namely:

$\left\{\begin{array}{c}{\mathrm{<span\; class="notranslate">\; \&Delta;T</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; t</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; t</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\\ {\mathrm{<span\; class="notranslate">\; \&Delta;T</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; t</span>}\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; t</span>}\mathrm{<span\; class="notranslate">\; 3</span>}\end{array}\right.<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

Similarly, the conversion delay value of the Delay_Req message from the slave clock to the master clock is as follows:

$\left\{\begin{array}{c}{\mathrm{<span\; class="notranslate">\; \&Delta;T</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; t</span>}{\mathrm{<span\; class="notranslate">\; 4</span>}}^{<span\; class="notranslate">\; ,</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; t</span>}{\mathrm{<span\; class="notranslate">\; 3</span>}}^{<span\; class="notranslate">\; ,</span>}\\ {\mathrm{<span\; class="notranslate">\; \&Delta;T</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; t</span>}{\mathrm{<span\; class="notranslate">\; 2</span>}}^{<span\; class="notranslate">\; ,</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; 11</span>}}^{<span\; class="notranslate">\; ,</span>}\end{array}\right.<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

In formula (5), t1' is the time when the Delay_Req message arrives at the E1/Ethernet protocol conversion device B, and t2' is the time when the protocol conversion is completed and ready to be sent to the SDH network, that is, the time when the Delay_Req message leaves the protocol conversion device B, and t3 ' is the time when the Delay_Req message arrives at the protocol conversion device A, and t4' is the time when the Delay_Req message leaves the protocol conversion device A.

Substituting formula (4) and formula (5) into formula (3), we get:

offset＝(T ₂ -T ₁ +T ₃ -T ₄ +delay2-delay1+t4'-t3'+t2'-t1'-t2+t1-t4+t3)/2 (6)

It can be seen from Figure 2 that the path delay value delay1 of the Sync message transmitted in the SDH network can be represented by t3-t2, and the path delay value delay2 of the Delay_Req message transmitted through the SDH network can be represented by t3'-t2', so the following formula Established:

$\left\{\begin{array}{c}\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; l</span>}\mathrm{<span\; class="notranslate">\; a</span>}\mathrm{<span\; class="notranslate">\; the\; y</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; t</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; t</span>}\mathrm{<span\; class="notranslate">\; 2</span>}\\ \mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; l</span>}\mathrm{<span\; class="notranslate">\; a</span>}\mathrm{<span\; class="notranslate">\; the\; y</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; t</span>}{\mathrm{<span\; class="notranslate">\; 3</span>}}^{<span\; class="notranslate">\; ,</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; t</span>}{\mathrm{<span\; class="notranslate">\; 2</span>}}^{<span\; class="notranslate">\; ,</span>}\end{array}\right.<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>$

Substituting formula (7) into formula (6), we can get:

offset＝(T ₂ -T ₁ +T ₃ -T ₄ +t4'-t1'+t1-t4)/2 (8)

From formula (8), it can be obtained that the time deviation between the master and slave clocks and the time when the Sync message arrives at the E1/Ethernet protocol conversion device A, the time when the Sync message leaves the E1/Ethernet protocol conversion device B, and the time when the Delay_Req message arrives at the E1 /Ethernet protocol conversion device B is related to the time when the Delay_Req message leaves the E1/Ethernet protocol conversion device A. That is, during the message transmission process, the time deviation between the master and slave clocks can be accurately calculated by clarifying the time values of the Sync message and the Delay_Req message at different positions. The specific time values that need to be clearly recorded are as follows: The slave clock receives The time when the Sync message arrives; the exact value of the time when the master clock sends the Sync message; the time when the slave clock sends the Delay_Req message; the exact value of the time when the master clock receives the Delay_Req message; the Sync message arrives at the The moment of the protocol conversion device; the moment when the Sync message leaves the protocol conversion device directly connected to the slave clock; the moment when the Delay_Req message leaves the protocol conversion device directly connected to the master clock; the Delay_Req message arrives at the protocol conversion directly connected to the slave clock moment of installation.

Specifically, a module can be added to the E1/Ethernet protocol conversion device for recording the arrival and departure time of the message, storing the recorded time, and adjusting the time information carried in the message according to the recorded time. For example, record and store the time t1 when the Sync message arrives at the protocol conversion device A and the time t4 when it leaves the protocol conversion device B, and adjust the time T1 carried in the Follow_up message to T1 _{- t1} +t4 according to the recorded time; record And store the time t1' when the Delay_Req message arrives at the protocol conversion device B and the time t4' when it leaves the protocol conversion device _A , and adjust the time T4 carried in the Delay_Resp message to T4 ₊ t1'-t4' according to the recorded time. In specific implementation, the protocol conversion device directly connected to the master clock can be configured to only record and store the time t1 when the Sync message arrives at the protocol conversion device and the time t4' when the Delay_Req message leaves the protocol conversion device through an association mechanism; The protocol conversion device directly connected to the clock only records and stores the time t4 when the Sync message leaves the protocol conversion device and the time t1' when the Delay_Req message arrives at the protocol conversion device; and then adjusts the time information carried by the corresponding messages respectively.

The specific methods of recording time and adjusting time are as follows:

₁ ) after the master clock sends the synchronization message at the first moment T1, the first protocol conversion device receives the synchronization message, records the time t1 when the synchronization message arrives at the first protocol conversion device, and outputs the synchronization message through the SDH network;

The second protocol conversion device receives the synchronization message, sends the synchronization message to the slave clock, and records the time t4 when the synchronization message leaves the second protocol conversion device;

After the master clock sends the synchronous following message, the first protocol conversion device receives the synchronous following message, adjusts the _first moment T1 carried in the synchronous following message to T1- _t1 , and outputs the synchronous following message through the SDH network;

The second protocol conversion device receives the synchronization following message, adjusts the time T ₁ -t1 carried in the synchronization following message to T ₁ -t1+t4, and sends the synchronization following message to the slave clock.

2) After the slave clock sends the delay request message at the _third moment T3, the second protocol conversion device receives the delay request message, records the time t1' when the delay request message arrives at the second protocol conversion device, and outputs the delay through the SDH network request message;

The first protocol conversion device receives the delay request message, sends the delay request message to the master clock, and records the moment t4' when the delay request message leaves the first protocol conversion device;

After the master clock receives the delay request message at the _fourth moment T4, it outputs a delay response message;

The first protocol conversion device receives the delayed response message, adjusts the _fourth moment T4 carried in the delayed response message to T4 _- t4', and outputs the delayed response message through the SDH network;

The second protocol conversion device receives the delay response message, adjusts the time T ₄ -t4' carried in the delay response message to T ₄ +t1'-t4', and sends the delay response message to the slave clock.

It can be seen that when the master-slave clock adopts PTP technology to transmit the time synchronization signal through the SDH network, the E1/Ethernet protocol conversion device introduces the protocol conversion time delay and the inconsistent asymmetric delay of the two-way transmission path of the SDH network. In the original PTP algorithm (required Two-way transmission path symmetry, that is, the two-way delay is consistent), and the conversion delay and asymmetric delay are included in the calculation process to obtain a more accurate master-slave clock time deviation, and then the clock synchronization based on the time deviation is also more reliable.

Based on the same inventive concept, an embodiment of the present invention also provides a master-slave clock synchronization system, which can be used to implement the methods described in the above embodiments, as described in the following embodiments. Since the problem-solving principle of the master-slave clock synchronization system is similar to the master-slave clock synchronization method, the implementation of the master-slave clock synchronization system can refer to the implementation of the master-slave clock synchronization method, and the repetition will not be repeated. The term "module" used hereinafter may be a combination of software and/or hardware that realizes a predetermined function. Although the systems described in the following embodiments are preferably implemented in software, implementations in hardware, or a combination of software and hardware are also possible and contemplated.

Fig. 3 is the structural block diagram of the master-slave clock synchronization system of the embodiment of the present invention, as shown in Fig. 3, this system comprises: master clock 31, first protocol conversion device 32, second protocol conversion device 33 and slave clock 34, the first Messages are transmitted between the first protocol conversion device 32 and the second protocol conversion device 33 through the SDH network. This structure will be specifically described below.

The master clock 31 is used to send a synchronization message, a synchronization following message and a delay response message to the slave clock 34, and receive a delay request message from the slave clock 34, wherein the synchronization following message carries a synchronization message sent by the master clock. The first time T ₁ of the message, the delay response message carries the fourth time T ₄ when the master clock receives the delay request message;

The first protocol conversion device 32 is connected to the master clock 31, and the first protocol conversion device 32 includes: a first recording module 321 and a first adjustment module 322;

Wherein, the first recording module 321 is used to record and store the time t1 when the synchronization message arrives at the first protocol conversion device and the time t4' when the delay request message leaves the first protocol conversion device;

The first adjustment module 322, connected to the first recording module 321, is used to adjust the first time T1 carried in the synchronization following message to T1 _{- t1} , and adjust the _fourth time T4 carried in the delay response message adjusted to T4 _- t4';

The second protocol conversion device 33 is connected to the slave clock 34, and the second protocol conversion device 33 includes: a second recording module 331 and a second adjustment module 332;

Wherein, the second recording module 331 is used to record and store the time t4 when the synchronization message leaves the second protocol conversion device and the time t1' when the delay request message arrives at the second protocol conversion device;

The second adjustment module 332, connected to the second recording module 331, is used to adjust the time T ₁ -t1 carried by the synchronization following message to T ₁ -t1+t4, and the time T ₄ -t4 carried by the delayed response message 'Adjust to T ₄ + t1'-t4';

The slave clock 34 includes: a first transceiver module 341 and a computing module 342;

Among them, the first transceiver module 341 is used to receive the synchronization message, and record the _second moment T2 when the synchronization message is received; receive the synchronization follow message, and obtain the adjusted master clock from the synchronization follow message to send the synchronization The sending time T ₁ -t1+t4 of the message; sending the delay request message, and recording the third moment T ₃ of sending the delay request message; receiving the delay response message, and obtaining the adjusted master from the delay response message The time T ₄ +t1'-t4' at which the clock receives the delay request message;

_The calculation module 342, connected to the _{first transceiver} module ₃₄₁ , is used to calculate the master clock and The time deviation between the slave clocks, and correct the time of the slave clocks according to the time deviation.

Through the above-mentioned master-slave clock synchronization system, in the process of transmitting the PTP time synchronization signal through the E1 channel of the SDH network, the protocol conversion delay and the asymmetric delay due to inconsistent bidirectional transmission paths are considered, and the association mechanism between the protocol conversion device and the master-slave clock is considered. , the calculation accuracy of the time deviation between the master and slave clocks is improved, and the clock synchronization based on the time deviation is also relatively reliable, and the implementation method is simple.

The calculation module 342 calculates the time offset offset between the master clock and the slave clock according to the following formula:

offset=(T ₂ -T ₁ +T ₃ -T ₄ +t4'-t1'+t1-t4)/2.

The first protocol conversion device 32 also includes: a second transceiver module, configured to receive and forward a synchronization message, a synchronization following message, a delay request message and a delay response message.

The second protocol conversion device 33 also includes: a third transceiver module, configured to receive and forward a synchronization message, a synchronization following message, a delay request message and a delay response message.

To sum up, when the master-slave clock uses PTP technology to transmit time synchronization signals through the SDH network, the E1/Ethernet protocol conversion device introduces the protocol conversion delay and the asymmetric delay of the bidirectional transmission path of the SDH network. Cooperate with the protocol conversion device and The association mechanism of the master-slave clock is based on the original PTP algorithm (requiring that the two-way transmission path is symmetrical, that is, the two-way delay is consistent), and the conversion delay and asymmetric delay are included in the calculation process to obtain a more accurate master-slave clock time The deviation improves the calculation accuracy of the time deviation between the master and slave clocks, and the clock synchronization based on the time deviation is also more reliable.

Those skilled in the art should understand that the embodiments of the present invention may be provided as methods, systems, or computer program products. Accordingly, the present invention can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, systems, and computer program products according to embodiments of the invention. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the scope of the present invention. Protection scope, within the spirit and principles of the present invention, any modification, equivalent replacement, improvement, etc., shall be included in the protection scope of the present invention.

Claims (7)

1. A master-slave clock synchronization method, characterized in that, comprising: The slave clock receives the synchronization message sent by the master clock at the _first time T1, and records the _second time T2 when the synchronization message is received; The slave clock receives the synchronization following message sent by the master clock, and obtains the sending time T ₁ -t1+t4 from the synchronization following message, wherein the sending time T ₁ -t1+t4 is the second The protocol conversion device adjusts the time T ₁ -t1, the time T ₁ -t1 is the time obtained after the first protocol conversion device adjusts the first time T ₁ , and the second protocol conversion device Connected to the slave clock; t1 is the moment when the synchronization message arrives at the first protocol conversion device connected to the master clock; t4 is the time when the synchronization message leaves the second protocol conversion device; The slave clock sends a delay request message to the master clock, and records the _third time T3 when the delay request message is sent, wherein the master clock receives the delay request message at a _fourth time T4 ; The slave clock receives the delay response message sent by the master clock, and obtains the reception time T ₄ +t1'-t4' from the delay response message, wherein the reception time T ₄ +t1'-t4 ' is obtained after the second protocol conversion device adjusts the time T ₄ -t4', and the time T ₄ -t4' is obtained after the first protocol conversion device adjusts the fourth time T ₄ , t1' is the moment when the delay request message arrives at the second protocol conversion device, and t4' is the time when the delay request message leaves the first protocol conversion device; _{The slave} clock _calculates the master _clock and time deviation between the slave clocks, and correcting the time of the slave clocks according to the time deviation; Wherein, the slave clock calculates the time offset offset between the master clock and the slave clock according to the following formula: offset=(T ₂ -T ₁ +T ₃ -T ₄ +t4'-t1'+t1-t4)/2. 2. The method according to claim 1, characterized in that, before the slave clock receives the synchronization message sent by the master clock at the _first moment T1, the method further comprises: The first protocol conversion device receives the synchronization message, records the time t1 when the synchronization message arrives at the first protocol conversion device, and outputs the synchronization message through the SDH network; The second protocol conversion device receives the synchronization message, sends the synchronization message to the slave clock, and records the time t4 when the synchronization message leaves the second protocol conversion device. 3. The method according to claim 2, wherein, before the slave clock receives the synchronization following message sent by the master clock, the method further comprises: The first protocol conversion device receives the synchronization following message, adjusts the first time T ₁ carried in the synchronization following message to T ₁ -t1, and outputs the synchronization following message through the SDH network ; The second protocol conversion device receives the synchronization following message, adjusts the time T ₁ -t1 carried in the synchronization following message to T ₁ -t1+t4, and sends the synchronization following message to the described slave clock. 4. The method according to claim 1, wherein, before the slave clock receives the delayed response message sent by the master clock, the method further comprises: The second protocol conversion device receives the delay request message, records the time t1' when the delay request message arrives at the second protocol conversion device, and outputs the delay request message through the SDH network; The first protocol conversion device receives the delay request message, sends the delay request message to the master clock, and records the time t4' when the delay request message leaves the first protocol conversion device; After receiving the delay request message, the master clock outputs the delay response message; The first protocol conversion device receives the delayed response message, adjusts the fourth time T ₄ carried in the delayed response message to T ₄ -t4', and outputs the delayed response message through the SDH network arts; The second protocol conversion device receives the delayed response message, adjusts the time T ₄ -t4' carried in the delayed response message to T ₄ +t1'-t4', and converts the delayed response message sent to the slave clock. 5. A master-slave clock synchronization system, characterized in that, comprising: a master clock, a first protocol conversion device, a second protocol conversion device and a slave clock; the first protocol conversion device and the second protocol conversion device Transmission of messages through the SDH network; The master clock is configured to send a synchronization message, a synchronization follow message and a delay response message to the slave clock, and receive a delay request message from the slave clock, wherein the synchronization follow message carries The first time T ₁ when the master clock sends the synchronization message, and the delay response message carries the fourth time T ₄ when the master clock receives the delay request message; The first protocol conversion device is connected to the master clock, and the first protocol conversion device includes: a first recording module and a first adjustment module; Wherein, the first recording module is used to record and store the time t1 when the synchronization message arrives at the first protocol conversion device and the time t4' when the delay request message leaves the first protocol conversion device; The first adjustment module is configured to adjust the first time T ₁ carried in the synchronization following message to T ₁ -t1, and adjust the fourth time T ₄ carried in the delayed response message to T ₄ -t4'; The second protocol conversion device is connected to the slave clock, and the second protocol conversion device includes: a second recording module and a second adjustment module; Wherein, the second recording module is used to record and store the time t4 when the synchronization message leaves the second protocol conversion device and the time t1' when the delay request message arrives at the second protocol conversion device; The second adjustment module is configured to adjust the time T ₁ -t1 carried in the synchronization following message to T ₁ -t1+t4, and adjust the time T ₄ -t4' carried in the delayed response message to be T ₄ +t1'-t4'; The slave clock includes: a first transceiver module and a computing module; Wherein, the first transceiver module is configured to receive the synchronization message, and record the _second time T2 when the synchronization message is received; receive the synchronization following message, and record the synchronization following message from the Obtain the sending time T ₁ -t1+t4 of the synchronization message sent by the master clock after the adjustment; send the delay request message, and record the third time T ₃ of sending the delay request message; receive The delay response message, and obtain the adjusted receiving time T ₄ +t1'-t4' of the master clock receiving the delay request message from the delay response message; _{The calculation module} is _configured to calculate the a time offset between the master clock and the slave clock, and correcting the time of the slave clock according to the time offset; Wherein, the calculation module calculates the time offset offset between the master clock and the slave clock according to the following formula: offset=(T ₂ -T ₁ +T ₃ -T ₄ +t4'-t1'+t1-t4)/2. 6. The system according to claim 5, wherein the first protocol conversion device further comprises: a second transceiver module, configured to receive and forward the synchronization message, the synchronization following message, the Delaying the request message and the delayed response message. 7. The system according to claim 5, wherein the second protocol conversion device further comprises: a third transceiver module, configured to receive and forward the synchronization message, the synchronization following message, the Delaying the request message and the delayed response message.