CN118800805B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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Abstract
The embodiment of the application relates to a semiconductor device and a preparation method thereof. The semiconductor device comprises a semiconductor material layer, a well region, a drift region, a source region, a drain region, at least one isolation trench, at least one field oxide layer, a plurality of field plate trenches, a plurality of field plates and a plurality of field plate trenches, wherein the well region and the drift region are arranged in the semiconductor material layer and are adjacent to each other, the source region and the drain region are respectively arranged in the well region and the drift region, the at least one isolation trench is arranged in the drift region and is arranged between the source region and the drain region, the at least one field oxide layer is arranged in the at least one isolation trench, the plurality of field plate trenches are arranged in the field oxide layer, the plurality of field plates are respectively arranged in the corresponding plurality of field plate trenches, and the field plates are isolated from the drift region by the field oxide layer. The embodiment of the application can realize the adjustment of the surface electric field of the drift region, improve the surface electric field distribution of the drift region in the three-dimensional direction, effectively reduce the surface peak electric field near the drift region at the near-drain end and improve the breakdown voltage of the drain region. Thus, a semiconductor device having an ultra-high withstand voltage can be obtained without increasing the on-resistance of the device.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
The BCD (Bipolar-CMOS-DMOS) process is a monolithically integrated process technology that enables Bipolar, CMOS (Complementary Metal Oxide Semiconductor ) and DMOS (Double-diffused Metal Oxide Semiconductor, double diffused metal oxide semiconductor) devices to be fabricated on the same chip. The BCD technology integrates the advantages of the three devices, becomes a main flow technology of an integrated circuit, meets the requirements of low power consumption, high integration level, high speed and high driving capability of the whole circuit, and has better reliability.
The BCD technology integrates the advantages of high transconductance and strong load driving capability of the bipolar device, high integration level and low power consumption of the CMOS device, and more importantly, the characteristics of high-voltage and high-current driving capability of the DMOS device. DMOS devices typically occupy about half the area of a chip, and BCD processes may integrate a variety of DMOS power devices, such as LDMOS (Lateral Double-diffused metal oxide semiconductor) devices, VDMOS (Vertical Double-diffused MOSFET) devices, and trench DMOS devices. The LDMOS high-voltage power device is one of core devices of product design, and therefore, how to optimize the structure and process of the LDMOS device so as to obtain higher withstand voltage is a problem to be solved.
Disclosure of Invention
In view of the above, embodiments of the present application provide a semiconductor device and a method for manufacturing the same to solve at least one of the problems in the background art.
In a first aspect, an embodiment of the present application provides a semiconductor device, including:
A layer of semiconductor material;
A well region and a drift region in the semiconductor material layer and adjacent to each other;
A source region and a drain region respectively located in the well region and the drift region;
at least one isolation trench located in the drift region and between the source region and the drain region;
At least one field oxide layer located in the at least one isolation trench;
a plurality of field plate trenches located in the field oxide layer;
and the field plates are respectively positioned in the field plate grooves, and the field plates are isolated from the drift region through the field oxide layer.
With reference to the first aspect of the present application, in an optional implementation manner, the number of the isolation trenches is multiple, the number of the field oxide layers is multiple, and the multiple field oxide layers are respectively located in the corresponding multiple isolation trenches;
The plurality of field oxide layers extend along a first direction and are arranged at intervals along a second direction, wherein the first direction is parallel to the direction from the source electrode region to the drain electrode region, and the second direction is perpendicular to the first direction in the plane direction of the semiconductor material layer;
each field oxide layer comprises at least one field plate.
With reference to the first aspect of the present application, in an optional implementation manner, each of the field oxide layers includes a plurality of field plates distributed at equal intervals along the first direction;
The distance between the field plates and the first side wall of the field oxide layer in the same field oxide layer is equal to the distance between the field plates and the second side wall of the field oxide layer, and the first side wall and the second side wall are two opposite side walls along the second direction.
In combination with the first aspect of the present application, in an alternative embodiment, the depth of the field plate is less than or equal to two-thirds of the depth of the field oxide layer.
With reference to the first aspect of the present application, in an optional implementation manner, the semiconductor device further includes:
and a gate structure on the semiconductor material layer, covering the top surface of the well region between the source region and the drain region, and extending to the top surface of the field oxide layer.
In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, including:
Providing a semiconductor material layer;
The method comprises the steps of forming a well region, a drift region, a source region, a drain region, at least one isolation trench, at least one field oxide layer, a plurality of field plate trenches and a plurality of field plates in the semiconductor material layer, wherein the well region and the drift region are located in the semiconductor material layer and are adjacent to each other, the source region and the drain region are located in the well region and the drift region respectively, at least one isolation trench is located in the drift region and between the source region and the drain region, at least one field oxide layer is filled in the at least one isolation trench, a plurality of field plate trenches are located in the field oxide layer, a plurality of field plates are filled in the corresponding plurality of field plate trenches, and the field plates are isolated from the drift region through the field oxide layer.
With reference to the first aspect of the present application, in an optional implementation manner, the number of the isolation trenches is multiple, the number of the field oxide layers is multiple, and the multiple field oxide layers are respectively located in the corresponding multiple isolation trenches;
The plurality of field oxide layers extend along a first direction and are arranged at intervals along a second direction, wherein the first direction is parallel to the direction from the source electrode region to the drain electrode region, and the second direction is perpendicular to the first direction in the plane direction of the semiconductor material layer;
each field oxide layer comprises at least one field plate.
With reference to the first aspect of the present application, in an optional implementation manner, each of the field oxide layers includes a plurality of field plates distributed at equal intervals along the first direction;
The distance between the field plates and the first side wall of the field oxide layer in the same field oxide layer is equal to the distance between the field plates and the second side wall of the field oxide layer, and the first side wall and the second side wall are two opposite side walls along the second direction.
In combination with the first aspect of the present application, in an alternative embodiment, the depth of the field plate is less than or equal to two-thirds of the depth of the field oxide layer.
With reference to the first aspect of the present application, in an optional embodiment, after the forming a well region, a drift region, a source region, a drain region, at least one isolation trench, at least one field oxide layer, a plurality of field plate trenches, and a plurality of field plates in the semiconductor material layer, the method for manufacturing the semiconductor device further includes:
A gate structure is formed on the layer of semiconductor material, the gate structure overlying a top surface of the well region between the source region and the drain region and extending onto a top surface of the field oxide layer.
According to the semiconductor device and the preparation method thereof provided by the embodiment of the application, the field oxide layer in the drift region is provided with the field plates, so that a plurality of electric field peaks can be introduced in the three-dimensional direction of the drift region, namely the length direction, the width direction and the thickness direction, and therefore, the surface electric field of the drift region is regulated, the surface electric field distribution of the drift region is improved in the three-dimensional direction, the surface peak electric field near the drift region near the drain end is effectively reduced, and the drain breakdown voltage is improved. Thus, a semiconductor device having an ultra-high withstand voltage can be obtained without increasing the on-resistance of the device.
Additional aspects and advantages of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
Fig. 1 is a schematic diagram of a layout of a semiconductor device provided in the related art;
fig. 2 is a schematic cross-sectional structure of a semiconductor device according to an embodiment of the present application;
fig. 3 is a schematic three-dimensional structure of a semiconductor device according to an embodiment of the present application;
Fig. 4 is a schematic layout diagram of a semiconductor device according to an embodiment of the present application;
fig. 5 is a schematic view showing a three-dimensional structure of a semiconductor device according to another embodiment of the present application;
fig. 6 is a schematic top view of a semiconductor device according to an embodiment of the present application;
FIG. 7 is a schematic diagram of an equipotential line distribution for the semiconductor device of FIG. 6;
fig. 8 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application.
Reference numerals illustrate:
100. semiconductor material layer 101, field plate medium 110, substrate 120, buried layer 130, epitaxial layer 210, well region 220, drift region 230, source region 240, drain region 250, well region contact region 310, field oxide layer 320, field plate 410, gate structure 420, gate medium layer 430, gate side wall 500, crystallization layer 510, well region contact plug 520, source region contact plug 530, drain region contact plug 540, gate contact plug 610, device isolation structure 620, deep well region T1, isolation trench T2, field plate trench.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the application are shown in the drawings, it should be understood that the application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the application may be practiced without one or more of these details. In other instances, well-known functions and constructions are not described in detail since they would obscure the application in some of the features that are well known in the art, i.e., not all features of an actual embodiment are described herein.
In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present.
Spatial relationship terms such as "under", "above", "over" and the like may be used herein for convenience of description to describe one element or feature as illustrated in the figures in relation to another element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to provide a thorough understanding of the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present application. Preferred embodiments of the present application are described in detail below, however, the present application may have other embodiments in addition to these detailed descriptions.
Fig. 1 is a schematic layout diagram of a semiconductor device provided in the related art.
Referring to fig. 1, the ldmos device includes a well region 210 and a drift region 220, a source region (not shown) and a drain region 240 respectively located in the well region 210 and the drift region 220, a field plate dielectric 101 located in the drift region 220, a gate structure 410 covering a portion of a top surface of the well region 210 and extending onto a portion of a top surface of the field plate dielectric 101, a crystallization layer 500 located on the source region and the drain region 240, and a source region contact plug 520, a drain region contact plug 530, and a gate contact plug 540 electrically connecting the source region, the drain region 240, and the gate structure 410, respectively.
In the related art, in order to increase the breakdown voltage of the LDMOS device, a field plate (electric field control plate) is typically fabricated on the field plate dielectric 101 above the drain-liner PN junction termination region, for example, the portion of the gate structure 410 extending onto the top surface of the field plate dielectric 101 may serve as a gate field plate. The field plate can effectively suppress the surface electric field and prevent surface breakdown to increase the drain breakdown voltage of the transistor in the device.
Here, the field plate can effectively suppress the surface electric field because a structure similar to a MOS (Metal Oxide Semiconductor ) capacitor is formed at the field plate, which divides the high voltage of the drain by a part, thereby lowering the avalanche breakdown voltage of the silicon surface of the device, improving the drain breakdown voltage, and effectively improving the withstand voltage capability of the device.
Specifically, STI (Shallow Trench Isolation ) structures can be formed by filling silicon dioxide in the shallow trenches as field plate medium, and gate field plates are formed on the STI to improve breakdown voltage. Compared with the method of using LOCOS (Local Oxidation of Silicon, local oxidation isolation of silicon) structure as field plate medium and forming metal field plate on LOCOS, the method has the advantages of simple process and no need of extra mask.
However, in order to further increase the breakdown voltage, an LDMOS device with an ultra-high withstand voltage is obtained, and a method of further increasing the length of the drift region or the depth of the shallow trench isolation structure is generally adopted to increase the on-resistance so as to increase the withstand voltage performance of the device, but this may sacrifice the area of the active region of the device and the on-path of the current, and increase the on-path of the current of the device, thereby greatly increasing the on-resistance (characteristic on-resistance) of the device.
Based on the above, the embodiment of the application provides a semiconductor device. Fig. 2 is a schematic cross-sectional structure of a semiconductor device according to an embodiment of the present application. Referring to fig. 2, the semiconductor device includes:
a layer of semiconductor material 100;
Well region 210 and drift region 220 are located in semiconductor material layer 100 and adjacent to each other;
A source region 230 and a drain region 240 located in the well region 210 and the drift region 220, respectively;
At least one isolation trench T1 located in the drift region 220 and between the source region 230 and the drain region 240;
At least one field oxide layer 310 located in the at least one isolation trench T1;
a plurality of field plate trenches T2 in the field oxide layer 310;
the field plates 320 are respectively located in the corresponding plurality of field plate trenches T2, wherein the field plates 320 are isolated from the drift region 220 by the field oxide layer 310.
It can be appreciated that, in the embodiment of the present application, by disposing a plurality of field plates 320 in the field oxide layer 310 located in the drift region 220, a plurality of electric field peaks may be introduced in the three-dimensional direction, i.e., the length direction, the width direction and the thickness direction of the drift region 220, so as to adjust the surface electric field of the drift region 220, improve the surface electric field distribution of the drift region 220 in the three-dimensional direction, effectively reduce the surface peak electric field near the near-drain drift region 220, and improve the drain breakdown voltage. Thus, a semiconductor device having an ultra-high withstand voltage can be obtained without increasing the on-resistance of the device.
In addition, the embodiment of the application can also reduce the length of the drift region 220 on the basis of maintaining the maximum breakdown voltage of the semiconductor device provided by the related technology, thereby reducing the on-resistance of the device and increasing the chip integration density.
In some embodiments, referring to fig. 2, the semiconductor material layer 100 may include a substrate 110, and a buried layer 120 and an epitaxial layer 130 formed on the substrate 110. The buried layer 120 and the epitaxial layer 130 are sequentially stacked on the substrate 110 from bottom to top. The layer of semiconductor material 100 may also be referred to as a "wafer".
Specifically, the well region 210, the drift region 220, the source region 230, the drain region 240, the isolation trench T1, the field oxide layer 310, the field plate trench T2, and the field plate 320 are all located in the epitaxial layer 130.
It should be noted that the top surface and the bottom surface of the semiconductor material layer 100 are located on the same plane, or strictly speaking, the center plane in the thickness direction Z of the semiconductor material layer is defined as the plane of the semiconductor material layer, and the direction parallel to the plane of the semiconductor material layer is the direction along the plane of the semiconductor material layer. Two first directions X and second directions Y perpendicular to each other are defined in the plane direction of the semiconductor material layer. Here, the first direction X is a direction parallel to a direction from the source region 230 to the drain region 240, and the second direction Y is a direction perpendicular to the first direction X in a plane direction of the semiconductor material layer.
The material of the substrate 110 may be an elemental semiconductor material (e.g., a silicon substrate, a germanium substrate, etc.), or a III-V compound semiconductor material (e.g., a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, an indium phosphide substrate, etc.), or a II-VI compound semiconductor material, or an organic semiconductor material, or other semiconductor materials known in the art. In an embodiment of the present application, the substrate 110 may be a silicon substrate.
In some embodiments, referring to fig. 2, the buried layer 120 may be a buried layer of a first conductivity type, and the epitaxial layer 130 may be an epitaxial layer of a second conductivity type. The first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is N-type and the second conductivity type is P-type. Specifically, the N-type impurity ions include phosphorus ions, arsenic ions, and antimony ions, and the P-type impurity ions include boron ions, gallium ions, and indium ions. The conductivity types of the buried layer 120 and the epitaxial layer 130 are opposite, and the conductivity types of the buried layer 120 and the epitaxial layer 130 may be adjusted according to the device actually formed.
In actual fabrication, the buried layer 120 may be formed by ion implantation of the first conductivity type of the top surface layer of the substrate 110. Epitaxial layer 130 may be formed by an epitaxial growth process or other suitable method.
In some embodiments, referring to fig. 2, the well region 210 and the drift region 220 are adjacent to each other along the first direction X, and a space exists between the drift region 220 and the well region 210. A source region 230 is formed in the well region 210, and a drain region 240 is formed in the drift region 220. Also, a well contact region 250 is formed in the well region 210, the well contact region 250 is adjacent to the source region 230, and the well contact region 250 is located at a side of the source region 230 away from the drift region 220.
Well region 210 may also be referred to as a "body region" or a "channel region," and well region contact region 250 may be referred to as a "channel-out implant region.
In practical preparation, the well region 210, the source region 230, the drain region 240, and the drift region 220 plasma implantation regions may be formed by ion implantation. Well region 210 may also be formed by self-aligned implantation.
In some embodiments, the conductivity type of the drift region 220, the source region 230, and the drain region 240 may be the same, and the same as the conductivity type of the epitaxial layer 130. Well region 210 and well region contact region 250 are of the same conductivity type. The conductivity types of the drift region 220 and the well region 210 are different.
Specifically, epitaxial layer 130 may be an N-type epitaxial layer, drift region 220 may be an N - drift region, source region 230 may be an N + source region, drain region 240 may be an N + drain region, well region 210 may be a P - well region, and well region contact region 250 may be a P + well region contact region. Here, the drift region 220 may be a lightly doped region to facilitate the improvement of the withstand voltage level of the device, and the source region 230 and the drain region 240 may be heavily doped regions to facilitate the reduction of the contact resistance.
It is understood that the conductivity type of the drift region 220 is the same as the conductivity type of the epitaxial layer 130, and that the drift region 220 has an opposite conductivity type to the buried layer 120. Here, by providing the buried layer 120 having the opposite conductivity type at the bottom of the drift region 220, the impurity concentration at the bottom of the drift region 220 is advantageously increased, and thus the electric field distribution at the bottom of the drift region 220 can be improved, and the breakdown voltage of the device can be increased.
In some embodiments, referring to fig. 2, the isolation trench T1 is located in the drift region 220, and the depth of the isolation trench T1 is smaller than the depth of the drift region 220 along the thickness direction Z of the semiconductor material layer. The isolation trench T1 may be formed in the drift region 220 by a photolithography etching or the like process.
In some embodiments, in a cross section perpendicular to the second direction Y, the isolation trench T1 may have an inverted trapezoid shape in cross section, and the isolation trench T1 may be filled with a dielectric material to form a shallow trench isolation Structure (STI) as the field oxide layer 310. Dielectric materials include, but are not limited to, silicon dioxide.
Specifically, the isolation trench T1 is completely filled by the field oxide layer 310, the top surface of the field oxide layer 310 is flush with the top surface of the drift region 220, or the field oxide layer 310 extends from the top surface of the drift region 220 into the drift region 220, and the depth of the field oxide layer 310 is smaller than the depth of the drift region 220 along the thickness direction Z of the semiconductor material layer.
In some other embodiments, the field oxide layer 310 may be a silicon local oxide isolation structure or a high temperature oxide layer.
The shallow trench isolation structure, the silicon local oxidation isolation structure and the high temperature oxidation layer have different forming modes and thicknesses, and can be selected according to the device requirements. If the field oxide layer 310 is a shallow trench isolation structure, the shallow trench isolation structure may be formed by etching and filling the isolation trench T1 in the drift region 220, if the field oxide layer 310 is a silicon local oxidation isolation structure, the silicon local oxidation isolation structure may be formed by local oxidation, and if the field oxide layer 310 is a high temperature oxide layer, the high temperature oxide layer may be formed by high temperature deposition. In this embodiment, the field oxide layer 310 is a shallow trench isolation structure, and the material of the field oxide layer 310 may be silicon oxide.
In some embodiments, referring to fig. 2, a plurality of field plate trenches T2 are located in the field oxide layer 310, and the depth of the field plate trenches T2 is smaller than the depth of the field oxide layer 310 along the thickness direction Z of the semiconductor material layer. The field plate trench T2 may be formed in the field oxide layer 310 by a photolithography etching or the like process.
In some embodiments, the field plate trench T2 may have a rectangular cross-sectional shape in a cross-section perpendicular to the second direction Y, and the field plate trench T2 may be filled with a conductive material to form the field plate 320. Conductive materials include, but are not limited to, metals, polysilicon. In some other embodiments, the field plate 320 may also be a contact hole structure. In a cross section perpendicular to the second direction Y, the cross-sectional shape of the field plate 320 may be an inverted trapezoid.
Specifically, the field plate 320 completely fills the field plate trench T2, and the top surface of the field plate 320 is flush with the top surface of the field oxide layer 310, or the field plate 320 extends from the top surface of the field oxide layer 310 into the field oxide layer 310 (embedded inside the field oxide layer 310). The field plate may also be referred to as a "trench field plate".
Along the thickness direction Z of the semiconductor material layer, the depth of the field plate 320 is less than the depth of the field oxide layer 310, and the depth of the field plate 320 is less than or equal to two-thirds of the depth of the field oxide layer 310. Thus, in the thickness direction Z of the semiconductor material layer, the distance between the bottom of the field plate 320 and the bottom of the field oxide layer 310 is at least one third of the depth of the field oxide layer 310, and an effective electric field control region may be formed between the field plate 320 and the field oxide layer 310, so that electric field peaks are dispersed to improve breakdown voltage.
For example, the plurality of field plates 320 may be equally spaced in the first direction X in the field oxide layer 310. The plurality of field plates 320 may also be referred to herein as a "comb-like field plate structure".
In some embodiments, the plurality of field plates 320 in the field oxide layer 310 may be arranged in a plurality of rows and columns respectively distributed along the first direction X and the second direction Y in an array manner, and the plurality of field plates 320 are arranged at equal intervals along the first direction X and the second direction Y.
In some other embodiments, the plurality of field plates 320 may be arranged in a plurality of rows and columns respectively distributed along the first direction X and the third direction array. Here, the third direction may be a direction intersecting only the first direction X in the plane direction of the semiconductor material layer, not perpendicular to each other.
It will be appreciated that, where the length of the drift region 220 is fixed, the greater the number of electric field peaks within the drift region 220, the smaller the electric field peaks of the drain region 240. It can be seen that the number of electric field peaks in the drift region 220 is related to the breakdown voltage of the semiconductor device. Then, the larger the number of field plates 320, the larger the number of electric field peaks. And the smaller the width and pitch of the field plates 320, the greater the number of field plates 320 that can be provided. Accordingly, in some embodiments, the breakdown voltage of the semiconductor device may be adjusted by adjusting the number of field plates 320, the spacing between the plurality of field plates 320, and the width of the field plates 320.
Fig. 3 is a schematic three-dimensional structure of a semiconductor device according to an embodiment of the present application, and fig. 4 is a schematic layout of the semiconductor device according to an embodiment of the present application.
In some embodiments, referring to fig. 2 to 4, the number of the isolation trenches T1 is plural, the number of the field oxide layers 310 is plural, the field oxide layers 310 are respectively located in the corresponding isolation trenches T1, the field oxide layers 310 extend along a first direction X and are arranged at intervals along a second direction Y, the first direction X is parallel to a direction from the source region 230 to the drain region 240, the second direction Y is a direction perpendicular to the first direction X in a planar direction of the semiconductor material layer 100, and each field oxide layer 310 includes at least one field plate 320.
In some embodiments, referring to fig. 4 and 5, two field plates 320 are provided in each field oxide layer 310, which is an alternative embodiment of the present application. In some other embodiments, when the number of field oxide layers 310 is plural, the plurality of field plates 320 may be located in only one part of the field oxide layers 310, and no field plates 320 may be located in another part of the field oxide layers 310. The layout of the field plates 320 in the field oxide layers 310 may be selected according to practical requirements, which is not specifically limited herein.
Specifically, the drift region 220 between two adjacent field oxide layers 310 is an active region (active region) through which current passes from the source region 230 to the drain region 240. Here, the additional active region is advantageous for reducing the on-resistance of the semiconductor device.
It should be noted that, for the LDMOS device, the trade-off between the breakdown voltage and the on-resistance is the most important, and sacrificing the on-resistance to obtain a higher withstand voltage can limit the development of the LDMOS device with high density, high power and high withstand voltage to some extent, and limit the application and performance of the LDMOS device. In the embodiment of the application, the plurality of field oxide layers 310 are arranged at intervals along the second direction Y, and at least one field plate 320 is arranged in each of the plurality of field oxide layers 310, so that the problem of breakdown voltage reduction of the device caused by the fact that the additional active area is not provided with the field plates to assist in improving the voltage resistance of the device while the on-resistance of the device is reduced can be avoided.
Specifically, referring to fig. 5, fig. 5 is a schematic three-dimensional structure of a semiconductor device according to another embodiment of the present application. When the plurality of field oxide layers 310 are spaced apart in the second direction Y, current may flow from the source region 230 to the drain region 240 through the plurality of active regions (drift regions 220) (current flow is shown by arrows in fig. 5). It can be seen that, by providing the field oxide layers 310 separated along the second direction Y, the drift region 220 between adjacent field oxide layers 310 can be used as an active region, so that the effective width of the LDMOS device is greatly increased, the area of the active region can be significantly increased, the conduction path of the current during forward conduction can be reduced, and the on-resistance can be greatly reduced.
Here, the "effective width" of the device is the width of the conductive region of the device. A larger effective width allows the device to carry a larger amount of current, while a smaller effective width limits the device to carry a smaller amount of current. Devices with larger effective widths will also have smaller on-resistances than devices with smaller effective widths.
Further, referring to fig. 6 and fig. 7, fig. 6 is a schematic top view of a semiconductor device according to an embodiment of the present application, and fig. 7 is an equipotential line distribution schematic diagram of the semiconductor device corresponding to fig. 6. The newly added active region is disposed between the adjacent field oxide layers 310, and when a voltage is applied to the device, the N region of the device is connected to a positive voltage (+v), the P region is connected to the ground, and the PN junction depletion boundary (region between two curves drawn in the form of a dotted line in the figure) of the active region (drift region 220) has dense equipotential lines, and at this time, the surface electric field of the active region is higher than that of the field oxide layer 310. The higher surface electric field of the active region results in smaller breakdown voltage at the active region, which in turn results in reduced voltage withstand performance of the device.
The field oxide layer 310 on the side walls of the field plate 320 and the active region forms a metal-oxide layer-semiconductor capacitor structure, and the effect of such a structure on the electric field between the surface and the interior in the direction perpendicular to the semiconductor material layer 100 is equivalent to the effect of the portion of the gate structure 410 extending onto the top surface of the field plate medium 101 in fig. 1, that is, the surface electric field can be effectively suppressed, the interior electric field can be regulated, and further, the width and depth of the active region can be properly regulated, so that the electric field can be distributed more uniformly, and the breakdown voltage of the device can be effectively improved.
In addition, when the device is in a reverse bias state, the field plate 320 and the field oxide layer 310 can form a MOS capacitor structure on the side wall, so as to effectively assist depletion and pinch-off, make the electric field distribution more uniform, and also improve the voltage-withstanding performance of the device to a certain extent.
In some embodiments, referring to fig. 3, each field oxide layer 310 includes a plurality of field plates 320 equally spaced along a first direction X, a distance between the plurality of field plates 320 in the same field oxide layer 310 and a first sidewall of the field oxide layer 310 is equal to a distance between the plurality of field plates 320 and a second sidewall of the field oxide layer 310, and the first sidewall and the second sidewall are two sidewalls opposite along a second direction Y.
Here, in the second direction Y, the line width of the plurality of field plates 320 in the same field oxide layer 310 is equal to or greater than one half of the line width of the field oxide layer 310.
It can be appreciated that the plurality of field plates 320 are arranged at equal intervals along the first direction X, which is beneficial to uniform distribution of the electric field and further improves the breakdown voltage of the device.
In some embodiments, the plurality of field plates 320 in each field oxide layer 310 are arranged in such a manner as to be equally spaced along the first direction X. Of course, in some other embodiments, the plurality of field plates 320 in the same field oxide layer 310 may be arranged in a plurality of rows and columns respectively distributed along the first direction X and the second direction Y, and the plurality of field plates 320 are equally spaced along the first direction X and the second direction Y. For example, the field plates 320 in the same field oxide layer 310 are 4 in number and are arranged in 2 rows and 2 columns.
Specifically, the number of field plates 320 in each field oxide layer 310 may be 2, 3,5 or 6, etc., and may be set according to actual requirements, which is not specifically limited herein.
In some embodiments, referring to fig. 2, the semiconductor device further includes:
a gate structure 410 is located on the semiconductor material layer 100, covers the top surface of the well region 210 between the source region 230 and the drain region 240, and extends onto the top surface of the field oxide layer 310.
It will be appreciated that the portion of the gate structure 410 extending to the top surface of the field oxide layer 310 along the first direction X may serve as a gate field plate, which is beneficial to further suppressing the surface electric field of the device, preventing surface breakdown, so as to increase the drain breakdown voltage of the transistor in the device and further improve the breakdown voltage of the semiconductor device.
In some embodiments, a gate dielectric layer 420 is disposed between the gate structure 410 and the well region 210. Gate sidewalls 430 are formed on two opposite sidewalls of the gate structure 410 along the first direction X.
Specifically, the material of the gate structure 410 includes, but is not limited to, polysilicon or a metal material, and the material of the gate dielectric layer 420 includes, but is not limited to, oxide, and the material of the gate sidewall 430 includes, but is not limited to, silicon oxide and silicon oxynitride.
In some embodiments, referring to FIG. 2, the semiconductor device further includes a crystallization layer 500, the crystallization layer 500 covering the source region 230, the drain region 240, the well region contact region 250, and the top surface of the gate structure 410. The material of the crystallized layer 500 includes, but is not limited to, metal silicide. The crystallized layer 500 may reduce contact resistance between the source region 230, the drain region 240, the well region contact region 250, and the gate structure 410 and other conductive structures.
In some embodiments, referring to FIG. 2, the semiconductor device further includes a well contact plug 510, a source contact plug 520, a drain contact plug 530, and a gate contact plug 540 (shown in FIG. 4). The contact plugs are all located on the crystallized layer 500.
Specifically, well contact plug 510, source contact plug 520, drain contact plug 530, and gate contact plug 540 are electrically connected to well contact region 250, source region 230, drain region 240, and gate structure 410, respectively. The materials of the well region contact plug 510, the source region contact plug 520, the drain region contact plug 530, and the gate contact plug 540 may be the same or different. Specifically, the material of the contact plug may be a metal, such as tungsten, titanium, aluminum, copper, or the like.
Note that the source region contact plug 520 may also be referred to as a "source contact hole", and the drain region contact plug 530 may also be referred to as a "drain contact hole".
In some embodiments, referring to FIG. 2, the semiconductor device further includes a device isolation structure 610 and a deep well region 620. The device isolation structure 610 and the deep well region 620 are located in the epitaxial layer 130 and on a side of the drift region 220 remote from the well region 210. The device isolation structure 610 extends from the top surface of the epitaxial layer 130 into the epitaxial layer 130, the deep well region 620 is located below the device isolation structure 610, and the top and bottom surfaces of the deep well region 620 are in direct contact with the bottom surface of the device isolation structure 610 and the bottom surface of the epitaxial layer 130, respectively.
Here, the device isolation structure 610 may be a shallow trench isolation structure, and the deep well region 620 may be a deep P-well region. Deep well region 620 and device isolation structure 610 are used to isolate a plurality of LDMOS devices.
Based on this, the embodiment of the application also provides a method for manufacturing a semiconductor device, and fig. 8 is a schematic flow chart of the method for manufacturing a semiconductor device according to the embodiment of the application. Referring to fig. 8, the method for manufacturing the semiconductor device includes:
step S101, providing a semiconductor material layer;
step S102, a well region, a drift region, a source region, a drain region, at least one isolation trench, at least one field oxide layer, a plurality of field plate trenches and a plurality of field plates are formed in the semiconductor material layer, wherein the well region and the drift region are located in the semiconductor material layer and are adjacent to each other, the source region and the drain region are respectively located in the well region and the drift region, the at least one isolation trench is located in the drift region and between the source region and the drain region, the at least one field oxide layer is filled in the at least one isolation trench, the plurality of field plate trenches are located in the field oxide layer, the plurality of field plates are filled in the corresponding plurality of field plate trenches, and the field plates are isolated from the drift region by the field oxide layer.
In some embodiments, the number of the isolation trenches is a plurality, the number of the field oxide layers is a plurality, the field oxide layers are respectively located in the corresponding isolation trenches, the field oxide layers extend along a first direction and are arranged at intervals along a second direction, the first direction is parallel to a direction from the source region to the drain region, the second direction is a direction perpendicular to the first direction in a plane direction of the semiconductor material layer, and each field oxide layer comprises at least one field plate.
In some embodiments, each field oxide layer comprises a plurality of field plates which are distributed at equal intervals along a first direction X, the distance between the field plates in the same field oxide layer and a first side wall of the field oxide layer is equal to the distance between the field plates and a second side wall of the field oxide layer, and the first side wall and the second side wall are two opposite side walls along a second direction Y.
In some embodiments, the depth of the field plate is less than or equal to two-thirds the depth of the field oxide layer.
In some embodiments, after forming the well region, the drift region, the source region, the drain region, the at least one isolation trench, the at least one field oxide layer, the plurality of field plate trenches, and the plurality of field plates in the semiconductor material layer, the method of fabricating the semiconductor device further includes forming a gate structure on the semiconductor material layer, the gate structure overlying a top surface of the well region between the source region and the drain region and extending onto a top surface of the field oxide layer.
In summary, the embodiment of the application can introduce a plurality of electric field peaks in the three-dimensional direction of the drift region, namely the length direction, the width direction and the thickness direction by arranging the field plates in the field oxide layer positioned in the drift region, so that the surface electric field distribution is improved in the three-dimensional direction of the drift region by using the field plates under the condition of not obviously increasing the process, the peak electric field of the drift region at the near-drain end (drain region) is reduced, the drain breakdown voltage of the LDMOS device is increased, the voltage withstand capability of the LDMOS device is effectively improved, and meanwhile, the on resistance of the drift region is greatly reduced, and the integration density of a chip is obviously improved. The semiconductor device provided by the embodiment of the application has the characteristics of high density, high power and high voltage resistance.
The embodiment of the semiconductor device and the embodiment of the preparation method of the semiconductor device provided by the application belong to the same conception, and all technical features in the technical scheme recorded in each embodiment can be arbitrarily combined under the condition of no conflict. However, it should be further noted that the technical characteristics of the semiconductor device provided by the embodiment of the present application may be combined to solve the technical problems to be solved by the present application, so that the semiconductor device provided by the embodiment of the present application may not be limited by the method for manufacturing a semiconductor device provided by the embodiment of the present application, and any semiconductor device manufactured by the method for manufacturing a semiconductor device structure capable of forming the embodiment of the present application is within the scope of protection of the present application.
It should be understood that the above examples are illustrative and are not intended to encompass all possible implementations. Various modifications and changes may be made in the above embodiments without departing from the scope of the disclosure. Likewise, the individual features of the above embodiments can also be combined arbitrarily to form further embodiments of the application which may not be explicitly described. Therefore, the above examples merely represent several embodiments of the present application and do not limit the scope of protection of the patent of the present application.
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| CN110610994A (en) * | 2019-07-17 | 2019-12-24 | 成都芯源系统有限公司 | A lateral double-diffused metal-oxide-semiconductor field-effect transistor |
| CN118156290A (en) * | 2024-03-07 | 2024-06-07 | 粤芯半导体技术股份有限公司 | Laterally diffused metal oxide semiconductor device and method for preparing the same |
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| US12057499B2 (en) * | 2018-09-25 | 2024-08-06 | Nxp Usa, Inc. | Transistor devices with termination regions |
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| CN110518056A (en) * | 2019-08-02 | 2019-11-29 | 无锡华润上华科技有限公司 | Transverse diffusion metal oxide semiconductor device and its manufacturing method |
| CN118156290A (en) * | 2024-03-07 | 2024-06-07 | 粤芯半导体技术股份有限公司 | Laterally diffused metal oxide semiconductor device and method for preparing the same |
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