CN119050131B - Semiconductor structure - Google Patents
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- CN119050131B CN119050131B CN202411536897.XA CN202411536897A CN119050131B CN 119050131 B CN119050131 B CN 119050131B CN 202411536897 A CN202411536897 A CN 202411536897A CN 119050131 B CN119050131 B CN 119050131B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
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- 239000012535 impurity Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
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- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
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- 229910021332 silicide Inorganic materials 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本申请公开了一种半导体结构，包括：衬底；U型通道，形成在所述衬底上，具有两个平行通道和位于平行通道一端、连接所述两个平行通道的连接通道；源极和漏极，分别位于所述U型通道的开口侧的两端部；以及栅极，位于所述U型通道上方并横跨所述U型通道的两个平行通道。通过在衬底上形成U型通道，栅极横跨U型通道的两个平行通道可以实现同时二次控制通道，这种二次控制增加了栅极控制能力，同时也能有效减小漏电流。
The present application discloses a semiconductor structure, including: a substrate; a U-shaped channel formed on the substrate, having two parallel channels and a connecting channel located at one end of the parallel channels and connecting the two parallel channels; a source electrode and a drain electrode, respectively located at the two ends of the opening side of the U-shaped channel; and a gate electrode, located above the U-shaped channel and spanning the two parallel channels of the U-shaped channel. By forming a U-shaped channel on the substrate, the gate electrode spanning the two parallel channels of the U-shaped channel can realize a simultaneous secondary control channel, which increases the gate control capability and can also effectively reduce the leakage current.
Description
Technical Field
The present application relates generally to the field of semiconductors. More particularly, the present application relates to a semiconductor structure, particularly a field effect transistor structure.
Background
Fig. 1 shows a currently prevailing planar MOSFET (metal-oxide-semiconductor field effect transistor) structure. As shown, the gate 110, drain 120 and source 130 of the N-channel laterally conductive double-diffused field effect transistor are all on the top surface of the silicon wafer, with the bottom being the substrate 140. The gate 110 is an electrode for controlling the switching of the transistor, and is typically made of polysilicon 101 and is covered with a thin layer of silicon oxide as an insulating layer. The gate oxide 102 prevents gate current from flowing directly into the channel while allowing gate voltage to pass through the electric field control channel 150. Channel 150 is a conductive region connecting source 130 and drain 120, which is formed to be dependent on the gate voltage. The source 130 and drain 120 are the two main current terminals of the transistor, typically forming low resistance regions by heavy doping. When the transistor is on, current flows from source to drain via channel 150.
In semiconductor device design, heavily doping and shrinking the gate oxide thickness are two common techniques used to improve device performance. However, the application of these techniques may also bring about side effects such as leakage current effects and reduced gate control capability, thereby limiting the device scaling. For example, heavy doping is typically used for the source and drain regions to reduce their resistance. At high doping levels, the distance between the source and drain is reduced, increasing the probability of direct tunneling and thus increasing leakage current. The high electric field of the heavily doped region may cause hot carriers to be injected into the gate oxide, increasing the gate current, which is also a leakage current. As another example, as the gate oxide becomes thinner, the electric field strength increases, increasing the probability of tunneling electrons through the gate oxide, resulting in an increase in gate leakage current. Thinning the gate oxide also reduces the gate's ability to control the channel because the effect of the gate voltage on the channel charge is reduced, which can lead to reduced threshold voltage and reduced device performance. Corresponding changes may also trigger Narrow channel effects (Narrow CHANNEL EFFECT, NCE) and Short channel effects (Short CHANNEL EFFECT, SCE), etc.
In view of the foregoing, it is desirable to provide a semiconductor structure, and in particular a field effect transistor scheme, that can reduce leakage current while improving gate control capability, thereby achieving a certain degree of integration.
Disclosure of Invention
To solve at least one or more of the technical problems mentioned above, the present application proposes a semiconductor structure.
In a first aspect, the application provides a semiconductor structure comprising a substrate, a U-shaped channel formed on the substrate and provided with two parallel channels and a connecting channel which is positioned at one end of the parallel channels and is used for connecting the two parallel channels, a source electrode and a drain electrode which are respectively positioned at two ends of the opening side of the U-shaped channel, and a grid electrode which is positioned above the U-shaped channel and spans the two parallel channels of the U-shaped channel.
In some embodiments, the closed end of the U-shaped channel is doped with ions to adjust the equivalent resistance of the U-shaped channel, thereby meeting different requirements.
In some embodiments, the closed end of the U-shaped channel is covered with a salicide block layer to increase the equivalent resistance of the U-shaped channel for use in High Voltage (HV) devices.
In some embodiments, the gate is positioned no further than two ends of the internal groove of the U-shaped channel in a lateral direction along the channel direction of the U-shaped channel.
In some embodiments, the semiconductor structure further includes a gate insulating layer located between the gate and the U-shaped channel in an area covered by the gate.
In some embodiments, the gate insulating layer is a high-k dielectric film and the gate is a metal gate.
In some embodiments, the gate insulating layer is a silicon oxide dielectric film and the gate is polysilicon.
In some embodiments, the semiconductor structure further comprises an insulating layer between the gate and the U-shaped channel, filling between and outside two parallel channels of the U-shaped channel. In some embodiments, the semiconductor structure further includes a plurality of the U-shaped channels formed on the substrate in parallel distribution, and the gate is located over and spans the parallel channels of the plurality of the U-shaped channels. In some embodiments, the U-channel bumps form a fin structure on the substrate, and the gate spans and wraps around the sidewalls and top of two parallel channels of the U-channel.
The unexpected beneficial technical effect of the application is that by forming the U-shaped channel on the substrate according to the semiconductor structure provided above, the gate electrode spans two parallel channels of the U-shaped channel to realize simultaneous secondary control channels. This secondary control increases the gate control capability while also effectively reducing leakage current. Further, the occupied length of the U-shaped channel design along the channel direction can be reduced to half of the previous length compared with the conventional design while maintaining the original channel length. That is, such a nearly square MOS design is more compact than an elongated design and can be more flexibly embedded in other structures. In some embodiments, the equivalent resistance portion of the channel may be doped with ions to adjust the equivalent resistance of the channel to match different requirements, or a salicide block (SAB) may be overlaid to increase the equivalent resistance of the channel, thereby being applicable to high voltage devices. In some embodiments, such a design may be well utilized in designs requiring a repeating structure, such as may be readily generalized where multiple field effect transistors are required in parallel. Furthermore, this design may also be advantageously applied in fin field effect transistors (finfets).
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present application will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. In the drawings, embodiments of the application are illustrated by way of example and not by way of limitation, and like reference numerals refer to similar or corresponding parts and in which:
fig. 1 shows a currently mainstream planar MOSFET structure;
Figure 2 illustrates a top view of a semiconductor structure according to some embodiments of the present application;
fig. 3 illustrates a cross-sectional view of a semiconductor structure along a dashed line AA in accordance with some embodiments of the present application;
Fig. 4 illustrates a cross-sectional view of a semiconductor structure along dashed line BB according to some embodiments of the present application;
fig. 5 illustrates a top view of a semiconductor structure in accordance with further embodiments of the present application;
Fig. 6 shows a schematic diagram of a semiconductor structure according to further embodiments of the application;
fig. 7 illustrates a process flow diagram for fabricating a semiconductor structure in accordance with some embodiments of the application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity.
It should be understood that the terms "comprises" and "comprising," when used in this specification and in the claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification and claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the present specification and claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
It will also be appreciated that spatially relative terms, such as "under," "below," "under," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. When an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present.
Specific embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 2-4 illustrate schematic diagrams of semiconductor structures 200 according to some embodiments of the application, wherein fig. 2 is a top view, fig. 3 is a cross-sectional view along a dashed line AA, and fig. 4 is a cross-sectional view along a dashed line BB.
As shown, semiconductor structure 200 includes a substrate 210. The substrate 210 may be a silicon substrate, a silicon germanium substrate, a group III-V element compound substrate, or other semiconductor material substrate known to those skilled in the art. In some embodiments, substrate 210 may be a lightly doped silicon substrate, the doping type of the substrate determining the type of transistor, such as N-type or P-type, as embodiments of the application are not limited in this respect.
The substrate 210 has a U-shaped channel 220 formed therein. As can be seen from the top view of fig. 2, the U-shaped channel 220 has two parallel channels and a connecting channel at one end of the parallel channels connecting the two parallel channels.
The source electrode 230 and the drain electrode 240 are respectively located at both end portions of the opening side of the U-shaped channel 220. The source electrode 230 and the drain electrode 240 may be formed by doping both end regions of the U-shaped channel with ions. For example, on a p-type substrate, two n+ regions, a source region and a drain region, respectively, are formed by an ion implantation or diffusion process.
Grid 250 is positioned over and spans two parallel channels of U-shaped channel 220. As shown in fig. 2, gate 250 may be a rectangular layer overlying U-shaped channel 220. The gate 250 is positioned in a lateral direction (X direction in the drawing) of the U-shaped channel not to exceed both ends of the internal recess of the U-shaped channel, and the specific position may be selected according to the device requirements, for example, closer to the open side of the U-shaped channel, closer to the closed side of the U-shaped channel, or in between. The width of gate 250 in the X-direction and/or the length in the Y-direction may also be designed according to the requirements of the actual device. In general, the width of gate 250 in the X-direction does not exceed the internal groove length of the U-shaped channel. In some embodiments, the length of gate 250 in the Y direction can cover at least two parallel channels of the U-shaped channel.
A gate insulating layer is also included between gate 250 and U-channel 220. As shown in the cross-sectional view of fig. 4, the gate insulating layer 260 is located between the gate 250 and the U-shaped channel 220 in the region covered by the gate 250, i.e., the region where the gate contacts two parallel channels of the U-shaped channel 220.
An insulating layer is also included in semiconductor structure 200. As shown in fig. 2-4, an insulating layer 270 is positioned between the gate 250 and the U-shaped channel 220, filling between and outside the two parallel channels of the U-shaped channel 220. The insulating layer 270 may be an oxide, such as SiO2.
According to the semiconductor structure having the U-shaped channel provided as above, since the gate spans two parallel channels of the U-shaped channel, simultaneous secondary control channels can be realized. This secondary control increases the gate control capability while also effectively reducing leakage current. Further, the occupied length of such a U-shaped channel design along the channel direction can be reduced to the previous half, e.g. from L to L/2, compared to conventional designs, while maintaining the original channel length. That is, such a nearly square MOS design is more compact than an elongated design and can be more flexibly embedded in other structures.
In some embodiments, gate insulating layer 260 may be a silicon oxide dielectric film, such as SiO2, and gate 250 may be polysilicon.
In other embodiments, the Gate insulating layer 260 may be a High-K (HK) dielectric film and the Gate may be a Metal Gate (MG). By adopting the HKMG, the physical thickness of the gate insulating layer is increased through the increase of the dielectric constant of the gate insulating medium under the condition of keeping the same unit area gate capacitance and further ensuring the same control of the channel, thereby greatly reducing the direct tunneling current between the gate and the channel.
In some embodiments, the closed end of the U-shaped channel 220 (e.g., the region shown in block 280 of the figure) may be doped with ions. The closed end is the equivalent resistance part of the channel, which can be adjusted to match different requirements by selecting doping ions. For example, doping n-type impurities, such As phosphorus (P) or arsenic (As), in P-type semiconductors can increase the concentration of free electrons. Such doping can reduce the equivalent resistance of the channel, since electrons typically have a higher mobility. For another example, doping n-type semiconductors (e.g., silicon or germanium) with p-type impurities, such as boron (B) or aluminum (Al), may form holes, but the mobility of these holes is typically lower than the mobility of electrons. Thus, p-type doping reduces the electron concentration of the n-type semiconductor, thereby increasing the equivalent resistance of the channel.
Alternatively or additionally, in other embodiments, the closed ends of the U-shaped channels 220 may be covered with Salicide Block (SAB). The SAB layer is used for preventing silicide from generating so as to obtain a diffusion region with higher resistance, and can be used for improving resistance and withstand voltage. The semiconductor structure can be applied to a high-voltage device by covering the SAB layer to increase the channel equivalent resistance.
The U-shaped channel design of the application can be well utilized in the design requiring a repeated structure, for example, the application can be easily popularized to the occasion requiring a plurality of field effect transistors in parallel connection.
Fig. 5 illustrates a top view of a semiconductor structure 500 in accordance with further embodiments of the present application. As shown, in these embodiments, a plurality of U-shaped channels 220 are formed in parallel on the substrate, 3U-shaped channels being shown by way of example. Grid 250 is positioned over and across parallel channels of the U-shaped channels 220. In these embodiments, the structure and properties of the U-shaped channel 220 are the same as previously described in connection with FIGS. 2-4 and are not repeated here.
By extending the length of gate 250 in the Y direction so that it spans parallel channels of multiple U-channels, the gates of these U-channels can be interconnected, sharing a single gate control signal. The U-shaped channel design provided by the application can be easily applied to occasions needing grid parallel connection, and has a simple structure, thereby being convenient for realizing device densification.
Further, the U-channel design of the present application may also be advantageously applied in fin field effect transistors (FinFETs).
Fig. 6 illustrates a schematic perspective view of a semiconductor structure 600 in accordance with further embodiments of the present application. As shown, in these embodiments, the U-shaped channel 220 has a height, the protrusions form a fin structure on the substrate 210, and the fin structure is U-shaped in horizontal cross section. Gate 250 spans and wraps around the sidewalls and top of the two parallel channels of U-shaped channel 220. In these embodiments, other structures and properties of the U-shaped channel 220 are the same as previously described in connection with FIGS. 2-4 and are not repeated here.
The source electrode 230 and the drain electrode 240 are respectively located at both end portions of the opening side of the U-shaped channel 220. An insulating layer 270 is located between the gate 250 and the U-shaped channel 220, filling between and outside the two parallel channels of the U-shaped channel 220. In this embodiment, however, the height of the insulating layer 270 is lower than the height of the U-shaped channel. A gate insulating layer (not shown) is located between the gate 250 and the U-shaped channel 220 in the region covered by the gate 250, i.e., the region where the gate contacts two parallel channels of the U-shaped channel 220. In this embodiment, the gate insulating layer may be an "n" type thin layer covering the sidewalls and top of the parallel channels.
By applying the U-shaped channel disclosed by the application to the FinFET, the performance of the FinFET can be further improved, the gate control capability is increased, and meanwhile, the leakage current is effectively reduced.
The semiconductor structure of embodiments of the present application may be prepared in a variety of ways, and those skilled in the art may form it using suitable processes without developing new processes based on the structures disclosed above. For example, when implemented as a planar MOS transistor, existing planar MOS transistor fabrication processes may be employed, including, but not limited to, furnace tube, thin Film (TF), photolithography (PH), etching (etc), chemical mechanical polishing (CMP, chemical-MECHANICAL POLISHING), wet Etching (WET, wet Etching), and the like. More specifically, the formation of the U-shaped channel may employ a conventional shallow trench isolation (STI, shallow Trench Isolation) process, except for the trench shape. For another example, when implemented as a FinFET, existing FinFET processes may be employed, except that the fin structures formed are shaped differently. For another example, when a high-K material is used for the gate insulating layer, the HKMG process may be equally applicable.
Fig. 7 illustrates a process flow diagram for fabricating a semiconductor structure in accordance with some embodiments of the application. In this example, a planar silicon gate nMOS transistor is used as an example to describe its fabrication. Those skilled in the art can also fabricate the semiconductor structures described in other embodiments of the present application based on existing processes.
As shown in fig. 7, first, in step 701, a pad oxide layer and a hard mask layer are sequentially deposited on a substrate. For example, p-type silicon is selected as the substrate material, and then an isolation oxide layer is grown on the substrate surface to protect the active region from chemical contamination during subsequent processing. A hard mask layer, such as silicon nitride, is deposited over the pad oxide layer as a robust mask material that helps to protect the active area and acts as a barrier material during CMP.
Then, in step 702, a trench is formed by sequentially etching the hard mask layer, the pad oxide layer, and the semiconductor substrate to a certain depth through photolithography and etching processes. In this step, note that the etched trench shape corresponds to the region between the two parallel channels of the U-shaped channel described above in connection with fig. 2-4.
Next, in step 703, an insulating material such as silicon oxide is deposited in the trench until the trench is filled with the insulating material. For example, a Chemical Vapor Deposition (CVD) technique is used to fill the trench CVD oxide.
Next, in step 704, the excess oxide, hard mask layer, and pad oxide layer are removed. Excess oxide is removed, for example, using Chemical Mechanical Polishing (CMP), to ensure that the surface is planar. Thereafter, the hard mask layer and the pad oxide layer are further removed. Thereby, a U-shaped channel is formed on the substrate.
Next, in step 705, a gate is formed over the U-shaped channel by an oxidation, photolithography, etching, deposition, or the like process.
Finally, in step 706, source and drain electrodes are formed at both ends of the open side of the U-shaped channel by an ion implantation or diffusion process. The subsequent processing may be continued according to a conventional MOS tube process, and a description thereof will be omitted herein.
Thus, an exemplary method of fabricating a semiconductor structure in accordance with embodiments of the present application is described above in connection with a particular fabrication process flow. It will be appreciated by those skilled in the art that the semiconductor structure of the embodiments of the present application may also be prepared by not limited to the process flow described above, and that some of the processes may be replaced by other processes, and the present application is not limited in this respect.
As can be seen from the above description, the unexpected technical effect of the embodiment of the present invention is that by forming the U-shaped channel on the substrate, the gate electrode spans two parallel channels of the U-shaped channel to realize simultaneous secondary control channels. This secondary control increases the gate control capability while also effectively reducing leakage current. In this case, the performance can be improved without reducing the size, for example, reducing the thickness of the gate oxide layer to cause leakage. Further, the occupied length of the U-shaped channel design along the channel direction can be reduced to half of the previous length compared with the conventional design while maintaining the original channel length. That is, such a nearly square MOS design is more compact than an elongated design and can be more flexibly embedded in other structures. In some embodiments, the equivalent resistance portion of the channel may be doped with ions to adjust the equivalent resistance of the channel to match different requirements, or a salicide block (SAB) may be overlaid to increase the equivalent resistance of the channel, thereby being applicable to high voltage devices. In some embodiments, such a design may be well utilized in designs requiring a repeating structure, such as may be readily generalized where multiple field effect transistors are required in parallel. Furthermore, this design may also be advantageously applied in fin field effect transistors (finfets).
While various embodiments of the present application have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous modifications, changes, and substitutions will occur to those skilled in the art without departing from the spirit and scope of the application. It should be understood that various alternatives to the embodiments of the application described herein may be employed in practicing the application. The appended claims are intended to define the scope of the application and are therefore to cover all equivalents or alternatives falling within the scope of these claims.
Claims (7)
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5563077A (en) * | 1992-04-24 | 1996-10-08 | Hyundai Electronics Industries Co., Ltd. | Method of fabricating a thin film transistor having vertical channel |
| CN101673762A (en) * | 2008-09-09 | 2010-03-17 | 上海华虹Nec电子有限公司 | LDMOS transistor structure and preparation method |
| CN105374876A (en) * | 2014-08-20 | 2016-03-02 | 台湾积体电路制造股份有限公司 | Finfet transistor with u-shaped channel |
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| US11818886B2 (en) * | 2021-09-29 | 2023-11-14 | International Business Machines Corporation | Low program voltage flash memory cells with embedded heater in the control gate |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5563077A (en) * | 1992-04-24 | 1996-10-08 | Hyundai Electronics Industries Co., Ltd. | Method of fabricating a thin film transistor having vertical channel |
| CN101673762A (en) * | 2008-09-09 | 2010-03-17 | 上海华虹Nec电子有限公司 | LDMOS transistor structure and preparation method |
| CN105374876A (en) * | 2014-08-20 | 2016-03-02 | 台湾积体电路制造股份有限公司 | Finfet transistor with u-shaped channel |
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