CN118800734A - Electronic packaging and method of manufacturing the same - Google Patents

Abstract

An electronic package and a dummy chip are arranged on a bearing piece, and the electronic element and the dummy chip are coated by a coating layer, so that the dummy chip is exposed out of the side surface of the coating layer, and the warping of the coating layer can be restrained by the dummy chip after the bearing piece is removed by increasing the whole volume of the dummy chip.

Description

Electronic packaging and method of manufacturing the same

Technical Field

The present invention relates to a semiconductor device, in particular to an electronic package and a manufacturing method thereof.

Background Art

With the evolution of technology, the demand trend of electronic products is moving towards heterogeneous integration. For this reason, multi-chip module (MCM or MCP) is gradually emerging.

The semiconductor package 1 shown in FIG1A is manufactured by combining a plurality of semiconductor chips 11 onto a carrier 8 (as shown in FIG1B ), and then encapsulating the semiconductor chips 11 with a packaging colloid 15. Next, the carrier 8 is removed, and a circuit structure 16 is formed on the packaging colloid 15, so that the circuit structure 16 is electrically connected to the semiconductor chips 11. Afterwards, the circuit structure 16 is disposed on a packaging substrate 10 through a plurality of conductive elements 17, and the packaging substrate 10 can be connected to a circuit board (not shown) through a plurality of solder balls 19. By encapsulating a plurality of semiconductor chips 11 into a single structure, it has a larger number of I/Os, can greatly increase the computing power of the processor, and reduce the delay time of signal transmission, so as to be applied to high-end products with high-density circuits/high transmission speeds/high stacking numbers/large-size designs.

During the packaging process, the carrier 8 is in the form of a wafer. The packaging colloid 15 is prone to warpage due to its large coefficient of thermal expansion (CTE), which causes the carrier 8 to warp together and causes the edge of the carrier 8 to break. Therefore, the industry configures a dummy chip 18 on the empty area of the carrier 8 to occupy the surface area of the carrier 8 and reduce the amount of the packaging colloid 15, thereby reducing the degree of warpage.

Furthermore, the packaging colloid 15 needs to provide an amount within the packaging area A as shown in Figure 1B through the molding operation, so the packaging colloid 15 will completely cover the side 18c of the dummy chip 18, wherein the packaging colloid 15 fills the space between each of the semiconductor chips 11 (such as the cutting line L), the space between the semiconductor chip 11 and the dummy chip 18 (such as the cutting line L) and covers the edge of the packaging area A.

However, after the carrier 8 is removed, the overall structure becomes thinner and cannot suppress the warping of the packaging resin 15 , causing the packaging resin 15 to break at the edge of the packaging area A, and even making it impossible to perform subsequent processes of the circuit structure 16 .

Furthermore, since the dummy chip 18 cannot fully fill the edge contour of the carrier 8, the amount of the packaging glue 15 in the packaging area A is limited. Therefore, even if the dummy chip 18 is configured, the warping degree of the packaging glue 15 cannot be suppressed after the carrier 8 is removed.

Therefore, how to overcome the various problems of the above-mentioned prior art has become a topic that needs to be solved urgently.

Summary of the invention

In view of the above-mentioned defects of the prior art, the present invention provides an electronic package and a method for manufacturing the same, which can at least partially solve the problems of the prior art.

The electronic package of the present invention comprises: a coating layer; an electronic component embedded in the coating layer, wherein the electronic component has an active surface and an inactive surface opposite to each other; and a dummy chip embedded in the coating layer in a manner of spacing the electronic component so that the dummy chip is exposed on the side of the coating layer.

The present invention also provides a method for manufacturing an electronic package, comprising: placing an electronic component and a dummy chip on a carrier, the electronic component having an active surface and an inactive surface opposite to each other, so that the electronic component is bonded to the carrier with its inactive surface, and the dummy chip is placed on the edge of the carrier in a manner of spacing the electronic component; forming a coating layer on the carrier so that the coating layer covers the electronic component and the dummy chip, and the dummy chip is exposed on the side of the coating layer; and removing the carrier.

In the aforementioned electronic package and its manufacturing method, the electronic component is provided with a plurality of conductors on its active surface.

In the aforementioned electronic package and its manufacturing method, the electronic package includes a plurality of the dummy chips and a plurality of the electronic components, and the plurality of the dummy chips surround the plurality of the electronic components.

The aforementioned electronic package and its manufacturing method further include forming a circuit structure on the coating layer so that the circuit structure is electrically connected to the electronic element. For example, the circuit structure is not electrically connected to the dummy chip.

In the aforementioned electronic packaging component and its manufacturing method, a portion of the edge contour of the dummy chip is the same as the edge contour of the carrier.

The aforementioned electronic package and its manufacturing method further include providing a plurality of the electronic components as a chipset, and then placing the chipset and the dummy chip on the carrier. For example, the chipset further includes a packaging layer covering the plurality of electronic components.

As can be seen from the above, in the electronic package and the manufacturing method thereof of the present invention, the overall volume of the dummy chip is increased mainly by exposing the side of the covering layer of the dummy chip to reduce the amount of the covering layer. Therefore, compared with the prior art, the present invention can effectively prevent the covering layer from warping.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic cross-sectional view of a conventional semiconductor package.

FIG. 1B is a top view schematically showing a conventional semiconductor package in a manufacturing process state.

2A to 2D are cross-sectional views of a method for manufacturing an electronic package according to a first embodiment of the present invention.

2A-1 to 2A-2 are top schematic views of the manufacturing process of FIG. 2A .

FIG. 2B-1 is a schematic top view of FIG. 2B .

FIG. 3 is a cross-sectional schematic diagram of another embodiment of FIG. 2D .

FIG. 4 is a schematic cross-sectional view of a subsequent process of FIG. 2D .

FIG. 5 is a cross-sectional view of a manufacturing method of a second embodiment of an electronic package of the present invention.

FIG. 6 is a cross-sectional schematic diagram of another embodiment of FIG. 5 .

Main component symbols

1 Semiconductor Package

10 Package substrate

11. Semiconductor Chip

15 Encapsulation colloid

16,26 Line structure

17,27 Conductive elements

18,28,38 Fake chips

18c,25c,28c side

19,42 solder balls

2,2a,2b,3,5,6 Electronic packaging

20,8 Bearing

200 Release layer

201 Dielectric protective layer

21,51 Electronic components

21a Action surface

21b Non-active surface

210 Electrode pads

211 Conductor

25 Coating

25a First surface

25b Second surface

260 Dielectric layer

261 Line Layer

262 Electrical contact pads

28a Surface

30 Wafer structure

40 Electronic devices

5a,6a chipset

60 Encapsulation Layer

91 First bonding layer

92 Second bonding layer

A Packaging area

L Cutting Road

S0,S1 edge profile

h1,h2 height.

DETAILED DESCRIPTION

The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment in size should still fall within the scope of the technical contents disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "on", "first", "second", and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

2A to 2D are cross-sectional views of a method for manufacturing an electronic package according to a first embodiment of the present invention.

As shown in FIG2A , a plurality of electronic components 21 are disposed on a carrier 20 through a first bonding layer 91, and at least one dummy die 28 is disposed on the carrier 20 through a second bonding layer 92 (as shown in FIG2A-2 , a plurality of electronic components 21 and a plurality of dummy chips 28 are disposed on the carrier 20), wherein a height h1 of the electronic component 21 relative to the carrier 20 is equal to or less than a height h2 of the dummy die 28 relative to the carrier 20.

The carrier 20 may be made of a metal plate or a semiconductor plate (such as a wafer or a glass plate). In this embodiment, the edge profile S0 of the carrier 20 is circular, and a release layer 200 and a dielectric protection layer 201 may be sequentially formed on the surface thereof.

The electronic component 21 is an active component, a passive component or a combination of the two. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor.

In this embodiment, the electronic component 21 is a single semiconductor chip, and its substrate body has a relative active surface 21a and an inactive surface 21b, the active surface 21a has a plurality of electrode pads 210, and the electronic component 21 is adhered to the dielectric protective layer 201 of the carrier 20 with its inactive surface 21b through the first bonding layer 91, and a plurality of bump-shaped conductors 211 are combined on the plurality of electrode pads 210.

Furthermore, an insulating layer (not shown) covering the plurality of conductors 211 may be formed on the active surface 21a, so that the top surface of the insulating layer and the end surface of the conductors 211 are flush with each other, so that the conductors 211 are exposed from the insulating layer. For example, the material forming the insulating layer is polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

The dummy chip 28 is a semiconductor material block without a signal transmission function, and a portion of its edge profile S1 is the same as the edge profile S0 of the carrier 20 .

In this embodiment, the substrate body of the electronic component 21 and the dummy chip 28 are made from a wafer of the same size. For example, the dummy chip 28 cuts a wafer structure 30, as shown in FIG. 2A-1, and removes the dummy chip 38 corresponding to the electronic component 21, and selects the remaining dummy chip 28, and places it on the carrier 20, so that the edge contour S1 of the dummy chip 28 on the carrier 20 corresponds to the edge contour S0 of the carrier 20, so that the overall outer contour of the dummy chips 28 is like a circle. It should be understood that the substrate body of the electronic component 21 forms the conductors 211 in the subsequent process, and the dummy chip 28 does not need to make the conductors 211.

Therefore, since the wafer structure 30 and the carrier 20 have the same shape and area, when the dummy chips 28 are arranged at the edge of the carrier 20 according to their positions on the wafer structure 30, as shown in Figure 2A-2, the dummy chips 28 can be configured corresponding to the edge contour S0 of the carrier 20.

In addition, the first bonding layer 91 and the second bonding layer 92 are both, for example, die attach films (DAF) embodiments, but there is no particular limitation.

As shown in FIG. 2B , a coating layer 25 is formed on the carrier 20 to cover the electronic component 21 and the dummy chip 28 to obtain the electronic package 2 , and the dummy chip 28 is exposed on the side surface 25 c of the coating layer 25 (as shown in FIG. 2B-1 ).

In this embodiment, the coating layer 25 has a first surface 25a and a second surface 25b opposite to each other, and the second surface 25b of the coating layer 25 is bonded to the dielectric protection layer 201 of the carrier 20. For example, the coating layer 25 is an insulating material, such as an encapsulating colloid of epoxy resin, which can be formed on the carrier 20 by lamination or molding.

Furthermore, a flattening process such as grinding is performed to remove part of the material of the first surface 25a of the cladding layer 25 so that the first surface 25a of the cladding layer 25 is flush with the end surface of the conductor 211 and the surface 28a of the dummy chip 28, so that the conductor 211 and the dummy chip 28 are exposed on the first surface 25a of the cladding layer 25.

In addition, the dummy chips 28 are configured to correspond to the edge profile S0 of the carrier 20 so that when the encapsulation layer 25 is formed in the packaging area A as shown in FIG. 2A-2, the side 28c of the dummy chip 28 is exposed to the side 25c of the encapsulation layer 25, wherein the packaging colloid 15 fills the space between each of the electronic components 21 (as shown in the cutting line L shown in FIG. 2A-2), the space between each of the dummy chips 28 (as shown in the cutting line L shown in FIG. 2A-2), and the space between the electronic component 21 and the dummy chip 28 (as shown in the cutting line L shown in FIG. 2A-2).

It should be understood that since the dummy chips 28 can be configured corresponding to the edge profile S0 of the carrier 20, so that the dummy chips 28 are distributed all over the edge of the packaging area A, the area of the empty area on the surface of the carrier 20 can be greatly reduced, so that the encapsulation layer 25 only occupies the cutting path L and its usage can be greatly reduced.

As shown in FIG. 2C , the carrier 20 and the release layer 200 and the dielectric protection layer 201 thereon are removed to form another embodiment of an electronic package 2 a .

As shown in FIG. 2D , a circuit structure 26 is formed on the first surface 25 a of the cladding layer 25 , and the circuit structure 26 is electrically connected to the conductor 211 to form another embodiment of an electronic package 2 b .

In this embodiment, the circuit structure 26 includes a plurality of dielectric layers 260 and a plurality of circuit layers 261 disposed on the plurality of dielectric layers 260 and electrically connected to the conductors 211, such as a circuit redistribution layer (RDL) specification. For example, the material forming the circuit layer 261 is copper, and the material forming the dielectric layer 260 is polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

Furthermore, a leveling process can be performed as required. As shown in FIG. 3 , the first bonding layer 91 and the second bonding layer 92 are removed by grinding so that the inactive surface 21b of the electronic component 21 and the surface of the dummy chip 28 are flush with the second surface 25b of the coating layer 25, and the inactive surface 21b of the electronic component 21 and the surface of the dummy chip 28 are exposed on the second surface 25b of the coating layer 25 to obtain an electronic package 3 with a thinner thickness.

In addition, the circuit structure 26 may have a plurality of electrical contact pads 262 exposed from the dielectric layer 260 on the outermost circuit layer 261 to combine with conductive elements 27 such as copper pillars or solder balls for subsequent placement of electronic devices 40 such as packaging structures, circuit boards or chips, as shown in FIG4. For example, the packaging substrate serves as the electronic device 40, and a plurality of solder balls 42 may be disposed on the lower side of the packaging substrate to combine with the circuit board.

In addition, the circuit structure 26 does not need to be electrically connected to the dummy chip 28 because no signal is transmitted to the dummy chip 28 .

Therefore, the manufacturing method of the present invention mainly designs a partial edge profile S1 of the dummy chip 28 to be the same as the edge profile S0 of the carrier 20, so that the dummy chip 28 almost covers the edge of the packaging area A, that is, the encapsulation layer 25 only occupies the area at the cutting path L of the packaging area A, so that after the encapsulation layer 25 is formed, the dummy chip 28 exposes the side 25c of the encapsulation layer 25. Therefore, compared with the prior art, the present invention reduces the volume ratio of the encapsulation layer 25 in the packaging area A, so as to effectively reduce the degree of warping caused by the CTE mismatch between the encapsulation layer 25 and the electronic component 21.

Furthermore, since the dummy chip 28 is distributed all over the edge of the packaging area A, the overall volume of the dummy chip 28 is increased, so that after the carrier 20 is removed, the warping of the encapsulation layer 25 caused by the larger coefficient of thermal expansion (CTE) can be effectively suppressed. Therefore, compared with the prior art, the internal stress of the encapsulation layer 25 can be greatly dispersed into the dummy chip 28 to prevent the encapsulation layer 25 from warping.

In addition, when the size of the carrier 20 is larger, the warping degree of the coating layer 25 will not increase accordingly due to the configuration of multiple dummy chips 28 corresponding to the edge profile S0 of the carrier 20. Therefore, when manufacturing the circuit structure 26, the electrical connection between the circuit layer 261 and the conductor 211 of the electronic component 21 can be effectively connected, thereby avoiding problems such as low yield and poor product reliability, thereby reducing costs and improving production capacity.

In addition, the manufacturing method of the present invention can use existing materials and old processes and machines without adding new processes and materials or purchasing new equipment. Therefore, the manufacturing method of the present invention can effectively control the process cost, making the electronic package 2, 2a, 2b, 3 of the present invention economical.

5 is a cross-sectional view of a second embodiment of the electronic package 5 of the present invention. The difference between this embodiment and the first embodiment lies in the size of the electronic components, and the other processes are substantially the same, so the same points will not be described in detail below.

As shown in FIG5 , in the process shown in FIG2A , a smaller electronic component 51 is used to arrange multiple electronic components 51 in the original layout area of the electronic component 21, as shown in FIG2A-2 , to serve as a chip set 5a. Afterwards, a coating layer 25 is formed on the carrier 20 to cover the chip set 5a and the dummy chip 28 to obtain an electronic package 5.

In this embodiment, the structure of the electronic component 51 with a smaller width is the same as the structure of the electronic component 21 with a larger width.

Furthermore, in another embodiment, as shown in FIG6 , the chipset 6a of the electronic package 6 may also be firstly encapsulated with the encapsulation layer 60 to encapsulate the electronic components 51, and then the chipset 6a may be bonded to the dielectric protection layer 201 of the carrier 20 through the first bonding layer 91. For example, the encapsulation layer 60 is an insulating material, such as an encapsulation colloid of epoxy resin, which may be the same as or different from the composition of the encapsulation layer 25.

The present invention further provides an electronic package 2 , 2 a , 2 b , 3 , 5 , 6 , comprising: a coating layer 25 , at least one electronic component 21 , 51 , and at least one dummy chip 28 .

The electronic components 21 , 51 are embedded in the coating layer 25 , wherein the electronic components 21 , 51 have an active surface 21 a and an inactive surface 21 b opposite to each other.

The dummy chip 28 is embedded in the covering layer 25 in a manner of spacing the electronic components 21 , 51 , and the dummy chip 28 is exposed on the side surface 25 c of the covering layer 25 .

In one embodiment, the electronic component 21 , 51 has a plurality of conductors 211 disposed on its active surface 21 a .

In one embodiment, the electronic package 2 , 2 a , 2 b , 3 , 5 , 6 includes a plurality of the dummy chips 28 and a plurality of the electronic components 21 , 51 , and the plurality of the dummy chips 28 surrounds the plurality of the electronic components 21 .

In one embodiment, the electronic package 2b further includes a circuit structure 26 disposed on the coating layer 25 to electrically connect the electronic component 21. For example, the circuit structure 26 is not electrically connected to the dummy chip 28.

In one embodiment, the electronic package 2 further includes a carrier 20 disposed on the covering layer 25 , which carries the electronic components 21 , 51 and the dummy chip 28 , and a portion of the edge profile S1 of the dummy chip 28 is the same as the edge profile S0 of the carrier 20 .

In one embodiment, a plurality of the electronic components 21 are embedded in the encapsulation layer 25 , so that the plurality of the electronic components 21 serve as the chipset 5 a , 6 a . For example, the chipset 6 a further includes a packaging layer 60 encapsulating the plurality of electronic components 51 .

In summary, the electronic package and the manufacturing method of the present invention increase the overall volume of the dummy chip by exposing the side of the coating layer of the dummy chip to reduce the amount of the coating layer, so the present invention can effectively prevent the coating layer from warping.

The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims (16)

1. An electronic package, comprising: Cladding layer; an electronic component embedded in the coating layer, wherein the electronic component has an active surface and an inactive surface opposite to each other; and The dummy chip is embedded in the covering layer in a manner of spacing the electronic component, and the dummy chip is exposed on the side surface of the covering layer. 2 . The electronic package as claimed in claim 1 , wherein a plurality of conductors are arranged on the active surface of the electronic component. 3 . The electronic package as claimed in claim 1 , wherein the electronic package comprises a plurality of the dummy chips and a plurality of the electronic components, and the plurality of the dummy chips surround the plurality of the electronic components. 4 . The electronic package as claimed in claim 1 , further comprising a circuit structure disposed on the covering layer to electrically connect the electronic component. The electronic package as claimed in claim 4 , wherein the circuit structure is not electrically connected to the dummy chip. 6 . The electronic package as claimed in claim 1 , further comprising a carrier disposed on the covering layer, the carrier carrying the electronic component and the dummy chip, and a portion of an edge profile of the dummy chip is the same as an edge profile of the carrier. 7 . The electronic package as claimed in claim 1 , wherein a plurality of the electronic components are embedded in the encapsulation layer so that the plurality of the electronic components serve as a chipset. 8 . The electronic package as claimed in claim 7 , wherein the chipset further comprises a packaging layer encapsulating the plurality of electronic components. 9. A method for manufacturing an electronic package, comprising: The electronic component and the dummy chip are arranged on a carrier, wherein the electronic component has an active surface and an inactive surface opposite to each other, so that the electronic component is bonded to the carrier with its inactive surface, and the dummy chip is arranged on the edge of the carrier in a manner of spacing the electronic component; forming a coating layer on the carrier so that the coating layer covers the electronic component and the dummy chip, and the dummy chip is exposed on a side surface of the coating layer; and Remove the carrier. 10 . The method for manufacturing an electronic package as claimed in claim 9 , wherein a plurality of conductors are disposed on the active surface of the electronic component. 11 . The method for manufacturing an electronic package as claimed in claim 9 , wherein a plurality of the dummy chips and a plurality of the electronic components are disposed on the carrier, and the plurality of the dummy chips surround a plurality of the electronic components. 12 . The method for manufacturing an electronic package as claimed in claim 9 , further comprising forming a circuit structure on the coating layer so that the circuit structure is electrically connected to the electronic component. 13 . The method for manufacturing an electronic package as claimed in claim 12 , wherein the circuit structure is not electrically connected to the dummy chip. 14 . The method for manufacturing an electronic package as claimed in claim 9 , wherein a portion of an edge contour of the dummy chip is the same as an edge contour of the carrier. 15 . The method for manufacturing an electronic package as claimed in claim 9 , further comprising providing a plurality of the electronic components to serve as a chipset, and then placing the chipset and the dummy chip on the carrier. 16 . The method for manufacturing an electronic package as claimed in claim 15 , wherein the chipset further comprises a packaging layer covering the plurality of electronic components.