CN118748206A - An enhanced gallium nitride high electron mobility transistor and a method for preparing the same - Google Patents

Abstract

The present invention discloses an enhanced gallium nitride high electron mobility transistor and a preparation method thereof. The transistor comprises: a GaN buffer layer and a barrier layer with a groove region sequentially grown on a substrate; a passivation protection layer covering the barrier layer; a high hole concentration structure layer covering the groove region; a source electrode and a drain electrode penetrating the barrier layer and the passivation protection layer and located on both sides of the high hole concentration structure layer; a gate electrode located on the high hole concentration structure layer; and a first ground electrode and a second ground electrode located outside the source electrode and the drain electrode and in contact with the GaN buffer layer. Since the first ground electrode and the second ground electrode are added to the edges of the drain electrode and the source electrode, they form an ohmic contact with the GaN buffer layer, and can extract electron-hole pairs generated by heavy ion incidence, thereby effectively improving the single particle burnout of the device caused by particles incident on the GaN high electron mobility transistor.

Description

An enhanced gallium nitride high electron mobility transistor and a method for preparing the same

Technical Field

The present invention belongs to the technical field of semiconductor power electronic devices, and in particular relates to an enhanced gallium nitride high electron mobility transistor and a preparation method thereof.

Background Art

GaN materials have unique advantages in the preparation of high-voltage, high-temperature, high-power and high-density integrated electronic devices due to their large bandgap, high critical breakdown electric field and high thermal conductivity. GaN materials can form heterojunction structures with materials such as AlGaN and InAlN. Due to the spontaneous polarization and piezoelectric polarization effects of materials such as AlGaN or InAlN, a high-concentration and high-mobility two-dimensional electron gas (2DEG) will be formed at the heterojunction interface. This characteristic can not only improve the carrier mobility and operating frequency of GaN-based devices, but also reduce the on-resistance and switching delay of the device.

Due to the superior electrical properties of GaN-based devices, they have broad application prospects in aerospace fields such as deep space exploration. In recent years, domestic and foreign research has been conducted on the single particle effects of GaN power devices in space applications. Studies have shown that particles incident on GaN high electron mobility transistors produce high-density electron-hole pairs of non-equilibrium carriers, which may cause device performance degradation or even burnout and failure.

Summary of the invention

The purpose of the present invention is to overcome the defects of the prior art and propose an enhanced gallium nitride high electron mobility transistor. The present invention also discloses a method for preparing an enhanced gallium nitride high electron mobility transistor, which can increase the single particle burnout threshold voltage of the device and counteract the single particle burnout effect.

An enhanced gallium nitride high electron mobility transistor comprises: a substrate, a GaN buffer layer, a barrier layer, a high hole concentration structure layer, a passivation protection layer, a source electrode, a drain electrode, a gate electrode, a first ground electrode, and a second ground electrode, wherein:

The GaN buffer layer and the barrier layer are sequentially grown on the substrate;

One side of the barrier layer has a groove region;

The passivation protection layer covers the barrier layer;

The high hole concentration structure layer covers the groove area;

The source electrode and the drain electrode are respectively located on both sides of the high hole concentration structure layer and penetrate the barrier layer and the passivation protection layer;

The gate electrode is located on the high hole concentration structure layer;

The first ground electrode is located outside the drain electrode, and the second ground electrode is located outside the source electrode and contacts the GaN buffer layer;

The source electrode and the drain electrode form an ohmic contact with the barrier layer, the gate electrode forms a Schottky contact with the high hole concentration structure layer, and the first ground electrode and the second ground electrode form an ohmic contact with the GaN buffer layer.

In an improved transistor, the distance between the first ground electrode and the drain electrode is greater than or equal to 1 um and less than or equal to 50 μm.

In an improved transistor, the distance between the second ground electrode and the source electrode is greater than or equal to 1 um and less than or equal to 50 μm.

In an improved transistor, the depth of the groove region is greater than or equal to 0 nm and less than or equal to the thickness of the barrier layer.

In an improved transistor, the high hole concentration structural layer is made of a p-type nitride multi-element alloy, and the doping concentration of the p-type nitride is greater than 10 ⁵ /cm ^-3 and less than or equal to 10 ²² /cm ^-3 .

On the other hand, the present invention provides a method for preparing an enhanced-mode gallium nitride high electron mobility transistor, comprising:

growing a GaN buffer layer on the substrate;

growing a barrier layer on the GaN buffer layer;

forming a mesa pattern on the barrier layer and the GaN buffer layer;

forming a passivation protective layer on the mesa pattern;

Patterning the passivation protection layer to obtain a first pattern;

forming a groove region on the barrier layer in the first pattern;

selectively regrowing a high hole concentration structure layer in the groove region;

Patterning the passivation protection layer to obtain a second pattern, a third pattern, a fourth pattern and a fifth pattern;

A source electrode and a drain electrode are prepared in the second and third graphics respectively, a first ground electrode and a second ground electrode are prepared in the fourth and fifth graphics, and high-temperature alloy annealing is performed to form an ohmic contact between the source electrode, the drain electrode and the barrier layer, and an ohmic contact is formed between the first and second ground electrodes and the GaN buffer layer;

A gate electrode is prepared on the high hole concentration structural layer, so that a Schottky contact is formed between the gate electrode and the high hole concentration structural layer.

In an improved preparation method, the distance between the first ground electrode and the drain electrode is greater than or equal to 1 um and less than or equal to 50 μm.

In an improved preparation method, the distance between the second ground electrode and the source electrode is greater than or equal to 1 um and less than or equal to 50 μm.

In an improved preparation method, the depth of the groove region is greater than or equal to 0 nm and less than or equal to the thickness of the barrier layer.

In an improved preparation method, the high hole concentration structural layer is made of a p-type nitride multi-element alloy, and the doping concentration of the p-type nitride is greater than or equal to 10 ⁵ /cm ^-3 and less than or equal to 10 ²² /cm ^-3 .

Compared with the prior art, the advantages of the present invention are:

A first ground electrode and a second ground electrode are added to the edges of the drain electrode and the source electrode of the transistor. The first ground electrode and the second ground electrode form an ohmic contact with the GaN buffer layer. By setting the bias voltage of the ground electrode, an electric field is established between the source, the drain and the ground electrode, which can extract electron-hole pairs generated by heavy ion incidence, prevent the device from having a single particle burnout effect at a low drain bias voltage, and increase the single particle burnout threshold voltage of the device. Therefore, the single particle burnout of the device caused by particles incident on the GaN high electron mobility transistor can be effectively improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic structural diagram of a gallium nitride high electron mobility transistor provided in Example 1 of the present invention;

FIG2 is a flow chart of a manufacturing process of a gallium nitride high electron mobility transistor according to Embodiment 2 of the present invention;

FIG3 is a second flow chart of the preparation process of a gallium nitride high electron mobility transistor provided in Example 2 of the present invention;

FIG4 is a third flow chart of the preparation process of a gallium nitride high electron mobility transistor provided in Example 2 of the present invention;

FIG5 is a fourth flow chart of the manufacturing process of the gallium nitride high electron mobility transistor provided in Example 2 of the present invention;

FIG6 is a fifth process flow chart of the preparation process of the gallium nitride high electron mobility transistor provided in Example 2 of the present invention;

FIG. 7 is a sixth flow chart of the manufacturing process of a gallium nitride high electron mobility transistor provided in Example 2 of the present invention;

FIG8 is a seventh process flow chart of the preparation process of a gallium nitride high electron mobility transistor provided in Example 2 of the present invention;

FIG. 9 is an eighth flowchart of the manufacturing process of the gallium nitride high electron mobility transistor provided in Example 2 of the present invention.

Reference numerals

100, substrate 200, GaN buffer layer

300, Barrier layer 301, Table top pattern

400, passivation protection layer 401, first pattern

402, groove area 500, high hole concentration structure layer

601, second figure 602, third figure

603, fourth figure 604, fifth figure

611, source electrode 612, drain electrode

613. Gate electrode 614. First ground electrode

615. Second ground electrode.

DETAILED DESCRIPTION

The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

Example 1

FIG1 is a schematic diagram of the structure of a gallium nitride high electron mobility transistor provided in Example 1 of the present invention. The gallium nitride high electron mobility transistor comprises:

Substrate 100, GaN buffer layer 200, barrier layer 300, passivation protection layer 400, high hole concentration structure layer 500, source electrode 611, drain electrode 612, gate electrode 613, first ground electrode 614 and second ground electrode 615, wherein:

The GaN buffer layer 200 and the barrier layer 300 are sequentially grown on the substrate 100;

One side of the barrier layer has a groove region;

The high hole concentration structure layer 500 covers the groove area;

The source electrode 611 and the drain electrode 612 are respectively located on two sides of the upper surface of the barrier layer 300 that is not covered by the high hole concentration structure layer 500, and penetrate the barrier layer and the passivation protection layer;

The gate electrode 613 is located on the high hole concentration structure layer 500;

The first ground electrode 614 and the second ground electrode 615 are located on the upper surface of the GaN buffer layer 200 on both sides of the source electrode 611 and the drain electrode 612;

The passivation protection layer 400 covers the barrier layer 300, specifically covers the area on the upper surface of the barrier layer 300 that is not covered by the high hole concentration structure layer 500, the source electrode 611, the drain electrode 612, the gate electrode 613, the first ground electrode 614 and the second ground electrode 615, the end surface of the barrier layer 300, part of the end surface of the GaN buffer layer 200, and part of the upper surface of the GaN buffer layer 200;

The source electrode 611 and the drain electrode 612 form an ohmic contact with the barrier layer 300 , the gate electrode 613 forms a Schottky contact with the high hole concentration structure layer 500 , and the first ground electrode 614 and the second ground electrode 615 form an ohmic contact with the GaN buffer layer 200 .

Specifically, the substrate 100 can be made of GaN, sapphire, Si, diamond or SiC.

The thickness of the GaN buffer layer 200 is in the range of 50 nm to 10 μm, and the thickness may be an end value of 50 nm and 10 μm.

The barrier layer 300 may be made of AlN, InN, AlGaN, InGaN or InAlN, and has a thickness ranging from 5 nm to 1 μm, with the thickness having end values of 5 nm and 1 μm.

The high hole concentration structure layer 500 may be made of a p-type nitride multi-element alloy, such as AlGaN, InGaN, GaN, etc.

The doping concentration of the p-type nitride of the high hole concentration structural layer 500 is greater than 10 ⁵ /cm ⁻³ and less than or equal to 10 ²² /cm ⁻³ .

The passivation protection layer 400 has a thickness of 5 nm-1 μm, and the thickness may be an end value of 5 nm and 1 μm.

The passivation protection layer 400 may be made of materials such as SiO ₂ , Si ₃ N ₄ , AlN, Al ₂ O ₃ , MgO, Sc ₂ O ₃ , TiO ₂ , HfO ₂ , BCB, ZrO ₂ , Ta ₂ O ₅ or La ₂ O ₃ .

The source electrode 611 , the drain electrode 612 , and the gate electrode 613 may be made of materials such as Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN, or any combination thereof.

The first ground electrode 614 and the second ground electrode 615 may be made of materials such as Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN, or any combination thereof.

FIG. 2 to FIG. 9 are flow charts of a manufacturing process of a gallium nitride high electron mobility transistor provided in Example 2 of the present invention. As shown in FIG. 2 to FIG. 9 , the corresponding method for manufacturing a gallium nitride high electron mobility transistor includes the following steps:

Step 1: growing a GaN buffer layer 200 on a substrate 100, as shown in FIG. 2 .

The substrate 100 may be made of GaN, sapphire, Si, diamond or SiC etc. The thickness of the GaN buffer layer 200 may be in the range of 50 nm to 10 μm.

Step 2: growing a barrier layer 300 on the GaN buffer layer 200 , as shown in FIG. 2 .

The barrier layer 300 may be made of AlN, InN, AlGaN, InGaN or InAlN, and may have a thickness ranging from 5 nm to 1 μm.

Step 3, forming a mesa pattern 301 on the barrier layer 300 and the GaN buffer layer 200 to isolate the GaN high electron mobility transistor from other GaN high electron mobility transistors, as shown in FIG. 3 .

The mesa pattern 301 may be formed by ion implantation, photolithography, and plasma dry etching techniques.

The mesa height of the mesa pattern 301 is greater than or equal to the thickness of the barrier layer 300 .

Step 4: forming a passivation protection layer 400 on the mesa pattern 301, as shown in FIG. 4 .

The passivation protection layer 400 may be formed by a common process such as deposition, wherein the passivation protection layer 400 may be deposited by sputtering or chemical vapor deposition.

The thickness of the passivation protection layer 400 is 20 nm-1 μm, and the material of the passivation protection layer 400 may be SiO ₂ , Si ₃ N ₄ , AlN, Al ₂ O ₃ , MgO, Sc ₂ O ₃ , TiO ₂ , HfO ₂ , BCB, ZrO ₂ , Ta ₂ O ₅ or La ₂ O ₃ or the like.

Step 5: patterning the passivation protection layer 400 to obtain a first pattern 401, as shown in FIG. 5 .

The passivation protection layer 400 may be patterned by using photolithography, plasma dry etching technology or wet etching technology.

Step 6: Form a groove region 402 in the barrier layer in the first pattern 401 region, wherein the groove depth is ≤ the thickness of the barrier layer 300 and the depth of the groove region can be 0 nm, as shown in FIG. 6 .

The barrier layer may be formed into grooves by using photolithography, plasma dry etching technology or wet etching technology.

Step 7: selectively re-grow a high hole concentration structure layer 500 in the groove region 402 , as shown in FIG. 7 .

The high hole concentration structural layer 500 is made of a p-type nitride multi-element alloy, such as AlGaN, InGaN, GaN, etc.

The doping concentration of the p-type nitride of the high hole concentration structural layer 500 is greater than or equal to 10 ⁵ / ^{cm -3} and less than or equal to 10 ²² /cm ^-3 .

The high hole concentration structure layer 500 may be formed in the recessed region 402 by growth and deposition, such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) and/or atomic layer deposition (ALD).

Step 8, patterning the passivation protection layer 400 to obtain a second pattern 601, a third pattern 602, a fourth pattern 603 and a fifth pattern 604, as shown in FIG. 8 .

The passivation protection layer 400 may be patterned by using photolithography, plasma dry etching technology or wet etching technology.

Step 9, prepare a source electrode 611 in the second figure 601, prepare a drain electrode 612 in the third figure 602, prepare a first ground electrode 614 in the fourth figure 603, and prepare a second ground electrode 615 in the fifth figure 604, as shown in Figure 9, and use high-temperature alloy annealing to form an ohmic contact between the source electrode 611 and the drain electrode 612 and the barrier layer 300, and an ohmic contact between the first ground electrode 614 and the second ground electrode 615 and the GaN buffer layer.

Metal electrodes can be prepared using photolithography, electron beam evaporation or sputtering techniques.

The source electrode 611, the drain electrode 612, the first ground electrode 614 and the second ground electrode 615 may be made of materials such as Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN and any combination thereof.

Step 10: prepare a gate electrode 613 on the high hole concentration structure layer 500 , as shown in FIG. 1 , so that a Schottky contact is formed between the gate electrode 613 and the high hole concentration structure layer 500 .

Metal electrodes can be prepared using photolithography, electron beam evaporation or sputtering techniques.

The gate electrode 613 may be made of a material selected from Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN, and any combination thereof.

Based on the traditional gallium nitride high electron mobility transistor, the present invention adds a first ground electrode 614 and a second ground electrode 615 at the edges of the drain electrode and the source electrode of the transistor, which can extract the electron-hole pairs generated by the heavy ion incidence, thereby preventing the device from having a single particle effect under a low drain bias voltage, and improving the single particle burnout threshold voltage of the device. The present invention has high reliability and good repeatability.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention is described in detail with reference to the embodiments, it should be understood by those skilled in the art that any modification or equivalent replacement of the technical solutions of the present invention does not depart from the spirit and scope of the technical solutions of the present invention and should be included in the scope of the claims of the present invention.

Claims (10)

1. An enhancement-mode gallium nitride high electron mobility transistor, comprising: a substrate, a GaN buffer layer, a barrier layer, a high hole concentration structure layer, a passivation protection layer, a source electrode, a drain electrode, a gate electrode, a first ground electrode and a second ground electrode, wherein: The GaN buffer layer and the barrier layer are sequentially grown on the substrate; One side of the barrier layer has a groove region; The passivation protection layer covers the barrier layer; The high hole concentration structure layer covers the groove area; The source electrode and the drain electrode are respectively located on both sides of the high hole concentration structure layer and penetrate the barrier layer and the passivation protection layer; The gate electrode is located on the high hole concentration structure layer; The first ground electrode is located outside the drain electrode, and the second ground electrode is located outside the source electrode and contacts the GaN buffer layer; The source electrode and the drain electrode form an ohmic contact with the barrier layer, the gate electrode forms a Schottky contact with the high hole concentration structure layer, and the first ground electrode and the second ground electrode form an ohmic contact with the GaN buffer layer. 2 . The enhancement-mode gallium nitride high electron mobility transistor according to claim 1 , wherein a distance between the first ground electrode and the drain electrode is greater than or equal to 1 um and less than or equal to 50 μm. 3 . The enhancement-mode gallium nitride high electron mobility transistor according to claim 1 , wherein a distance between the second ground electrode and the source electrode is greater than or equal to 1 um and less than or equal to 50 μm. 4 . The enhancement-mode gallium nitride high electron mobility transistor according to claim 1 , wherein a depth of the groove region is greater than or equal to 0 nm and less than or equal to a thickness of the barrier layer. 5. The enhancement mode gallium nitride high electron mobility transistor according to any one of claims 1 to 4, characterized in that the high hole concentration structural layer is made of a p-type nitride multinary alloy, and the doping concentration of the p-type nitride is greater than ¹⁰⁵ /cm ^-3 and less than or equal to ¹⁰²² /cm ^-3 . 6. A method for preparing an enhanced-mode gallium nitride high electron mobility transistor, comprising: growing a GaN buffer layer on the substrate; growing a barrier layer on the GaN buffer layer; forming a mesa pattern on the barrier layer and the GaN buffer layer; forming a passivation protection layer on the mesa pattern; Patterning the passivation protection layer to obtain a first pattern; forming a groove region on the barrier layer in the first pattern; selectively regrowing a high hole concentration structure layer in the groove region; Patterning the passivation protection layer to obtain a second pattern, a third pattern, a fourth pattern and a fifth pattern; A source electrode and a drain electrode are prepared in the second figure and the third figure respectively, a first ground electrode and a second ground electrode are prepared in the fourth figure and the fifth figure, and high temperature alloy annealing is performed to form an ohmic contact between the source electrode, the drain electrode and the barrier layer, and an ohmic contact is formed between the first ground electrode and the second ground electrode and the GaN buffer layer; A gate electrode is prepared on the high hole concentration structural layer, so that a Schottky contact is formed between the gate electrode and the high hole concentration structural layer. 7 . The method for preparing an enhancement-mode gallium nitride high electron mobility transistor according to claim 6 , wherein a distance between the first ground electrode and the drain electrode is greater than or equal to 1 um and less than or equal to 50 μm. 8 . The method for preparing an enhancement-mode gallium nitride high electron mobility transistor according to claim 6 , wherein a distance between the second ground electrode and the source electrode is greater than or equal to 1 um and less than or equal to 50 μm. 9 . The method for preparing an enhancement-mode gallium nitride high electron mobility transistor according to claim 6 , wherein a depth of the groove region is greater than or equal to 0 nm and less than or equal to a thickness of the barrier layer. 10. The method for preparing an enhancement mode gallium nitride high electron mobility transistor according to any one of claims 6-9, characterized in that the high hole concentration structural layer is made of a p-type nitride multinary alloy, and the doping concentration of the p-type nitride is greater than or equal to ¹⁰⁵ /cm ^-3 and less than or equal to ¹⁰²² /cm ^-3 .