CN118630021A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises: an SOI substrate, comprising a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, the SOI substrate comprising a first device region and a second device region, the top surface of the lower substrate in the first device region is higher than the top surface of the lower substrate in the second device region, the top surface of the insulating buried layer in the first device region is flush with the top surface of the insulating buried layer in the second device region, and the top surface of the semiconductor layer in the first device region is lower than the top surface of the semiconductor layer in the second device region. The technical solution of the present invention enables fully depleted devices and partially depleted devices to be integrated on the same substrate.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof.

Background Art

SOI (Semiconductor-On-Insulator) technology introduces an insulating buried layer between the top semiconductor layer and the lower substrate, thus achieving dielectric isolation of devices in integrated circuits and eliminating the latch-up effect in the CMOS circuit of the bulk substrate. In addition, integrated circuits made with SOI technology also have the advantages of small parasitic capacitance, high integration density, high speed, simple process, small short channel effect, and are particularly suitable for low-voltage and low-power circuits. SOI substrates include PDSOI (Partially Depleted SOI) substrates and FDSOI (Fully Depleted SOI) substrates.

SOI technology can be used to make PDSOI devices (partially depleted devices) and FDSOI devices (fully depleted devices). PDSOI devices are made on PDSOI substrates and have a higher breakdown voltage. They are mostly used as RF devices. In order to prevent harmonic interference of RF signals, the top semiconductor layer and the lower substrate need to be more insulated, that is, a thicker insulating buried layer and a thicker top semiconductor layer are required; while FDSOI devices are made on FDSOI substrates and have a lower breakdown voltage. They are mainly used as logic devices. In order to suppress the DIBL (Drain Induced Barrier Lowering) effect caused by device miniaturization, a thinner insulating buried layer and a thinner top semiconductor layer are required. In the prior art, different types of SOI devices can be integrated to enable the integrated devices to obtain better performance and functions. Due to the different thicknesses of the insulating buried layer and the top semiconductor layer of the PDSOI substrate and the FDSOI substrate, PDSOI devices are incompatible with FDSOI devices.

Therefore, how to integrate fully depleted devices and partially depleted devices on the same substrate is a problem that needs to be solved urgently.

Summary of the invention

The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so that a fully depleted device and a partially depleted device can be integrated on the same substrate.

To achieve the above-mentioned purpose, the present invention provides a semiconductor device, comprising: an SOI substrate, comprising a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, the SOI substrate comprising a first device region and a second device region, the top surface of the lower substrate in the first device region is higher than the top surface of the lower substrate in the second device region, the top surface of the insulating buried layer in the first device region is flush with the top surface of the insulating buried layer in the second device region, and the top surface of the semiconductor layer in the first device region is lower than the top surface of the semiconductor layer in the second device region.

Optionally, the buried insulating layer in the second device region includes a first insulating layer and a second insulating layer from bottom to top, and the buried insulating layer in the first device region includes the second insulating layer; and the bottom surfaces of the second insulating layers in the first device region and the second device region are flush.

Optionally, the buried insulating layer of the first device region further includes a third insulating layer, the third insulating layer is located between the second insulating layer and the underlying substrate, and the thickness of the third insulating layer is less than the thickness of the first insulating layer; or, the buried insulating layers of the first device region and the second device region both further include a third insulating layer, the third insulating layer of the first device region is located between the second insulating layer and the underlying substrate, and the third insulating layer of the second device region is located between the first insulating layer and the second insulating layer.

Optionally, the semiconductor device further includes:

A trench isolation structure is formed at the junction of the first device region and the second device region, and the trench isolation structure extends from the semiconductor layer to the lower substrate.

The present invention also provides a method for manufacturing a semiconductor device, comprising:

forming a first substrate, wherein a first insulating layer is formed in the first substrate;

forming a second substrate, the second substrate comprising a first base and a second insulating layer formed on the first base;

Bonding a surface of the second substrate having the second insulating layer formed thereon to a surface of the first substrate having the first insulating layer formed thereon;

Forming a first trench in the first substrate, wherein a projection of the first trench in a direction perpendicular to the surface of the first substrate is offset from a position of the first insulating layer, so as to form an SOI substrate, wherein the SOI substrate comprises, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer, and the SOI substrate comprises a first device region and a second device region;

Among them, the lower substrate of the first device area includes the first substrate below the first trench, the lower substrate of the second device area includes the first substrate below the first insulating layer, the insulating buried layer of the first device area includes the second insulating layer, the insulating buried layer of the second device area includes the second insulating layer and the first insulating layer, the semiconductor layer of the first device area includes the first base at the bottom of the first trench, and the semiconductor layer of the second device area includes the first base above the first insulating layer, so that the top surface of the lower substrate of the first device area is higher than the top surface of the lower substrate of the second device area, the top surface of the insulating buried layer of the first device area is flush with the top surface of the insulating buried layer of the second device area, and the top surface of the semiconductor layer of the first device area is lower than the top surface of the semiconductor layer of the second device area.

Optionally, the step of forming the first substrate includes:

Providing a second substrate, wherein a first insulating layer is formed on the second substrate;

forming a second trench penetrating the first insulating layer;

forming a first semiconductor layer in the second trench, wherein the second base, the first semiconductor layer and the first insulating layer together constitute the first substrate;

Alternatively, the step of forming the first substrate includes:

providing a second substrate;

forming a third groove in the second substrate;

A first insulating layer is formed in the third trench, and the second base and the first insulating layer together constitute the first substrate.

Optionally, after forming the first substrate, the method for manufacturing the semiconductor device further includes:

forming a third insulating layer in the first substrate outside the first insulating layer, wherein the thickness of the third insulating layer is less than the thickness of the first insulating layer;

Alternatively, a third insulating layer is formed on the first substrate, and the third insulating layer also covers the first insulating layer.

Optionally, the step of forming the second substrate includes:

providing a first substrate;

A second insulating layer is formed on the first substrate.

Optionally, before forming the first trench in the first substrate, the method for manufacturing the semiconductor device further includes:

A side of the first substrate away from the second insulating layer is thinned.

Optionally, the method for manufacturing the semiconductor device further includes:

A trench isolation structure is formed at the junction of the first device region and the second device region, and the trench isolation structure extends from the first base into the first substrate.

Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

1. The semiconductor device of the present invention comprises: an SOI substrate, including a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, the SOI substrate comprises a first device region and a second device region, the top surface of the lower substrate in the first device region is higher than the top surface of the lower substrate in the second device region, the top surface of the insulating buried layer in the first device region is flush with the top surface of the insulating buried layer in the second device region, and the top surface of the semiconductor layer in the first device region is lower than the top surface of the semiconductor layer in the second device region. This enables fully depleted devices and partially depleted devices to be integrated on the same substrate.

2. The method for manufacturing a semiconductor device of the present invention comprises: forming a first substrate, in which a first insulating layer is formed; forming a second substrate, in which the second substrate comprises a first base and a second insulating layer formed on the first base; bonding a side of the second substrate formed with the second insulating layer to a side of the first substrate formed with the first insulating layer; forming a first groove in the first base, wherein the projection of the first groove in a direction perpendicular to the surface of the first substrate is offset from the position of the first insulating layer to form a first device region and a second device region. This enables fully depleted devices and partially depleted devices to be integrated on the same substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

FIG2 is a schematic diagram of a semiconductor device according to another embodiment of the present invention;

3 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

4 to 15 are schematic diagrams of devices of a method for manufacturing the semiconductor device shown in FIG. 3 .

The reference numerals of Figures 1 to 15 are described as follows:

11-second substrate; 12-first insulating layer; 13-first semiconductor layer; 131-second trench; 14-first conductive layer; 15-second conductive layer; 21-first substrate; 211-first trench; 22-second insulating layer; 23-trench isolation structure; 231-silicon oxide layer; 232-silicon nitride layer; 233-fourth trench.

DETAILED DESCRIPTION

In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

An embodiment of the present invention provides a semiconductor device, comprising: an SOI substrate, comprising a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, the SOI substrate comprising a first device region and a second device region, the top surface of the lower substrate in the first device region is higher than the top surface of the lower substrate in the second device region, the top surface of the insulating buried layer in the first device region is flush with the top surface of the insulating buried layer in the second device region, and the top surface of the semiconductor layer in the first device region is lower than the top surface of the semiconductor layer in the second device region.

The semiconductor device provided in this embodiment is described in more detail below with reference to FIGS. 1 to 2 . FIGS. 1 to 2 are schematic longitudinal cross-sectional views of the semiconductor device.

The SOI substrate (Semiconductor-On-Insulator) includes a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, and the SOI substrate includes a first device region and a second device region, wherein the top surface of the lower substrate in the first device region is higher than the top surface of the lower substrate in the second device region, the top surface of the insulating buried layer in the first device region is flush with the top surface of the insulating buried layer in the second device region, and the top surface of the semiconductor layer in the first device region is lower than the top surface of the semiconductor layer in the second device region, so that the thickness of the insulating buried layer in the first device region is less than the thickness of the insulating buried layer in the second device region, and the thickness of the semiconductor layer in the first device region is less than the thickness of the semiconductor layer in the second device region, thereby enabling the first device region to be used to form a fully depleted device (FDSOI device) and the second device region to be used to form a partially depleted device (PDSOI device), thereby realizing the integration of fully depleted devices and partially depleted devices on the same SOI substrate, so that fully depleted devices and partially depleted devices are compatible.

The lower substrate and the semiconductor layer may be made of any suitable semiconductor material, including but not limited to: Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, other III/V or II/VI compound semiconductors and other semiconductor materials, and the insulating buried layer may be, for example, a silicon oxide layer.

In one embodiment, the lower substrate of the first device region consists of a first part and a second part from bottom to top, and the top surface of the first part is flush with the top surface of the lower substrate of the second device region; in another embodiment, the lower substrate of the first device region is a whole.

As shown in Figure 1, the lower substrate of the first device area A1 includes a second base 11 and a first semiconductor layer 13 from bottom to top, and the lower substrate of the second device area A2 only includes the second base 11. The top surface of the second base 11 of the first device area A1 is flush with the top surface of the second base 11 of the second device area A2. Therefore, the top surface of the first semiconductor layer 13 of the first device area A1 is higher than the top surface of the second base 11 of the second device area A2.

In one embodiment, the buried insulating layer in the second device region includes a first insulating layer and a second insulating layer from bottom to top, and the buried insulating layer in the first device region includes only the second insulating layer; the bottom surfaces of the second insulating layers in the first device region and the second device region are flush.

As shown in Figure 1, the buried insulating layer of the second device area A2 includes a first insulating layer 12 and a second insulating layer 22 from bottom to top, and the buried insulating layer of the first device area A1 only includes the second insulating layer 22, and the top and bottom surfaces of the second insulating layer 22 of the first device area A1 are flush with the top and bottom surfaces of the second insulating layer 22 of the second device area A2.

In one embodiment, as shown in FIG. 1 , the semiconductor layer of the first device area A1 includes a first substrate 21 , the semiconductor layer of the second device area A2 includes a first substrate 21 , and a top surface of the first substrate 21 of the first device area A1 is lower than a top surface of the first substrate 21 of the second device area A2 .

Preferably, the buried insulating layer in the first device region further includes a third insulating layer, the third insulating layer is located between the second insulating layer and the underlying substrate, the thickness of the third insulating layer is less than the thickness of the first insulating layer, and the top surface of the third insulating layer is slightly higher than the top surface of the first insulating layer; or, the buried insulating layers in the first device region and the second device region both further include a third insulating layer, the third insulating layer in the first device region is located between the second insulating layer and the underlying substrate, the third insulating layer in the second device region is located between the first insulating layer and the second insulating layer, and the top surface and bottom surface of the third insulating layer in the first device region are flush with the top surface and bottom surface of the third insulating layer in the second device region.

The semiconductor device further comprises:

A trench isolation structure is formed at the junction of the first device region and the second device region, and the trench isolation structure extends from the semiconductor layer to the lower substrate.

The top surface of the trench isolation structure is higher than the top surface of the semiconductor layer in the second device region, or the top surface of the trench isolation structure is flush with the top surface of the semiconductor layer in the second device region.

As shown in FIG. 1 , the trench isolation structure 23 extends from the first substrate 21 to the second substrate 11 , and the top surface of the trench isolation structure 23 is higher than the top surface of the first substrate 21 in the second device area A2 .

The semiconductor device further comprises:

A gate structure is formed on the semiconductor layer in the first device region and the second device region; the gate structure may include a gate dielectric layer, a gate layer and a sidewall, the gate dielectric layer and the gate layer are formed on the semiconductor layer from bottom to top, and the sidewall is formed on the sidewalls of the gate dielectric layer and the gate layer;

The source region and the drain region are formed on both sides of the gate structure; wherein, in the first device region, the source region and the drain region are formed on the semiconductor layer on both sides of the gate structure; and in the second device region, the source region and the drain region are formed in the semiconductor layer on both sides of the gate structure.

The buried insulating layers in the first device region and the second device region may also be provided with structures capable of optimizing the performance of the SOI substrate, thereby improving the performance of semiconductor devices.

In one embodiment, as shown in FIG2 , a first conductive layer 14 electrically connected to the semiconductor layer and the underlying substrate may be formed in the insulating buried layer of the first device area A1, and a second conductive layer 15 electrically connected to the semiconductor layer and the underlying substrate may be formed in the insulating buried layer of the second device area A2. Wherein, in the second device area A2, the second conductive layer 15 is located on the side of the source area or the drain area away from the gate structure, so that the source area or the drain area can be connected to the lower substrate through the second conductive layer 15, so that the heat generated in the semiconductor layer during the operation of the partially depleted device can be quickly transferred to the lower substrate through the second conductive layer 15, so that it can be dissipated in time through the lower substrate; in the first device area A1, the first conductive layer 14 is located on the side of the source area or the drain area away from the gate structure, so that the source area or the drain area can be connected to the lower substrate through the first conductive layer 14, so that the heat generated in the semiconductor layer during the operation of the fully depleted device can be quickly transferred to the lower substrate through the first conductive layer 14, so that it can be dissipated in time through the lower substrate. Thereby, the temperature rise of the entire semiconductor device is avoided, and the mobility of the semiconductor device is avoided to be reduced, so as to avoid the reduction of the channel current. Wherein, the materials of the first conductive layer 14 and the second conductive layer 15 include but are not limited to metal materials or semiconductor materials.

In summary, the semiconductor device provided by the present invention comprises: an SOI substrate, comprising a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, the SOI substrate comprising a first device region and a second device region, the top surface of the lower substrate in the first device region is higher than the top surface of the lower substrate in the second device region, the top surface of the insulating buried layer in the first device region is flush with the top surface of the insulating buried layer in the second device region, and the top surface of the semiconductor layer in the first device region is lower than the top surface of the semiconductor layer in the second device region. The semiconductor device of the present invention enables fully depleted devices and partially depleted devices to be integrated on the same substrate.

An embodiment of the present invention provides a method for manufacturing a semiconductor device. Referring to FIG. 3 , FIG. 3 is a flow chart of the method for manufacturing a semiconductor device according to an embodiment of the present invention. The method for manufacturing a semiconductor device includes:

Step S1, forming a first substrate, wherein a first insulating layer is formed in the first substrate;

Step S2, forming a second substrate, wherein the second substrate includes a first base and a second insulating layer formed on the first base;

Step S3, bonding the side of the second substrate having the second insulating layer formed thereon to the side of the first substrate having the first insulating layer formed thereon;

Step S4, forming a first trench in the first substrate, wherein a projection of the first trench in a direction perpendicular to the surface of the first substrate is offset from a position of the first insulating layer to form a first device region and a second device region.

The manufacturing method of the semiconductor device provided in this embodiment is described in more detail below with reference to FIGS. 1 to 2 and 4 to 15 . FIGS. 1 to 2 and 4 to 15 are schematic longitudinal cross-sectional views of the semiconductor device.

According to step S1, a first substrate is formed, in which a first insulating layer is formed. That is, the first insulating layer extends from the surface of the first substrate to the inside of the first substrate. The structure of the first substrate is shown in FIG6 or FIG7.

In one embodiment, referring to Figures 4 to 6, the steps of forming the first substrate may include: first, as shown in Figure 4, providing a second base 11, on which a first insulating layer 12 is formed; then, as shown in Figure 5, forming a second groove 131 penetrating the first insulating layer 12; then, as shown in Figure 6, forming a first semiconductor layer 13 in the second groove 131, the top surface of the first semiconductor layer 13 in the second groove 131 is flush with the top surface of the first insulating layer 12, and the second base 11, the first semiconductor layer 13 and the first insulating layer 12 together constitute the first substrate.

Alternatively, in another embodiment, as shown in Figure 7, the step of forming the first substrate may include: providing a second base 11 (not shown); forming a third groove (not shown) in the second base 11; forming a first insulating layer 12 in the third groove, and the second base 11 and the first insulating layer 12 together constitute the first substrate.

Preferably, after forming the first substrate, the method for manufacturing the semiconductor device further comprises:

A third insulating layer is formed in the first substrate outside the first insulating layer, and the thickness of the third insulating layer is less than the thickness of the first insulating layer; wherein the third insulating layer can be formed on the top of the first substrate outside the first insulating layer by a process such as thermal oxidation, and the top surface of the third insulating layer is slightly higher than the top surface of the first insulating layer.

Alternatively, a third insulating layer is formed on the first substrate, and the third insulating layer also covers the first insulating layer, that is, the third insulating layer extends from the surface of the first substrate to the surface of the first insulating layer; wherein the third insulating layer can be formed by a deposition process.

The second substrate and the first semiconductor layer can be composed of any suitable semiconductor material, including but not limited to: Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, other III/V or II/VI compound semiconductors and other semiconductor materials, and the first insulating layer and the third insulating layer are, for example, silicon oxide layers.

According to step S2, a second substrate is formed, wherein the second substrate includes a first base and a second insulating layer formed on the first base. The structure of the second substrate is shown in FIG8 .

In one embodiment, the step of forming the second substrate includes: first, providing an SOI substrate (not shown), the SOI substrate including, from bottom to top, a lower substrate, an insulating buried layer, and a second semiconductor layer; then, removing the second semiconductor layer to form a second substrate, the lower substrate being the first base, and the insulating buried layer being the second insulating layer; or removing the lower substrate to form a second substrate, the second semiconductor layer being the first base, and the insulating buried layer being the second insulating layer.

Alternatively, in another embodiment, as shown in FIG. 8 , the step of forming the second substrate includes: first, providing a first base 21 ; and then, forming a second insulating layer 22 on the first base 21 by using a process such as thermal oxidation or deposition.

It should be noted that the order of step S1 and step S2 is not limited.

According to step S3, the side of the second substrate on which the second insulating layer is formed is bonded to the side of the first substrate on which the first insulating layer is formed.

When the third insulating layer is formed only in the first substrate outside the first insulating layer, the third insulating layer and the first insulating layer are bonded to the side of the second insulating layer away from the first substrate; when the first substrate and the first insulating layer are both covered with the third insulating layer, the side of the third insulating layer away from the first substrate is bonded to the side of the second insulating layer away from the first substrate. In the above two embodiments, since the bonding interface is made of insulating material, the bonding effect is better.

As shown in FIG. 9 , a surface of the first insulating layer 12 away from the second substrate 11 is bonded to a surface of the second insulating layer 22 away from the first substrate 21 .

The first substrate can be made of any suitable semiconductor material, including but not limited to: Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, other III/V or II/VI compound semiconductors and other semiconductor materials, and the second insulating layer is, for example, a silicon oxide layer.

In one embodiment, as shown in FIG. 10 , before subsequently forming a first trench 211 in the first substrate 21 , the method for manufacturing a semiconductor device further includes: thinning a surface of the first substrate 21 away from the second insulating layer 22 .

According to step S4, a first trench is formed in the first substrate, and a projection of the first trench in a direction perpendicular to the surface of the first substrate is offset from a position of the first insulating layer to form a first device region and a second device region.

As shown in Figure 11, the first groove 211 is formed in the first substrate 21, and the projection of the first groove 211 in a direction perpendicular to the surface of the second substrate 11 is staggered with the projection of the first insulating layer 12 in a direction perpendicular to the surface of the second substrate 11, thereby forming a first device area A1 and a second device area A2, wherein the area where the first groove 211 is located is the first device area A1, and the area where the first insulating layer 12 is located is the second device area A2.

A projection of the first trench 211 in a direction perpendicular to the surface of the second substrate 11 overlaps with a projection of the first semiconductor layer 13 in a direction perpendicular to the surface of the second substrate 11 .

The method for manufacturing the semiconductor device further includes:

A trench isolation structure is formed at the junction of the first device region and the second device region, and the trench isolation structure extends from the first base into the first substrate.

The top surface of the trench isolation structure is higher than a side of the second substrate away from the first substrate, or the top surface of the trench isolation structure is flush with a side of the second substrate away from the first substrate.

In one embodiment, referring to Figures 12 to 15, the steps of forming the trench isolation structure may include: first, as shown in Figure 12, a mask layer is formed on the first substrate 21, and the mask layer fills the first trench 211; then, as shown in Figure 13, a fourth trench 233 is formed by etching, and the fourth trench 233 extends from the surface of the mask layer to the second substrate 11; then, as shown in Figure 14, a trench isolation structure 23 is formed in the fourth trench 233, and the trench isolation structure 23 isolates the first device area A1 and the second device area A2; then, as shown in Figure 15, the mask layer is removed.

The material of the mask layer may be silicon oxide, silicon nitride, silicon oxynitride, etc., and the material of the mask layer may also be photoresist. In the embodiment shown in FIG. 12 , the mask layer includes a silicon oxide layer 231 and a silicon nitride layer 232 from bottom to top, and the silicon oxide layer 231 fills the first trench 211 .

It can be known from the above content that by bonding the side of the second substrate on which the second insulating layer is formed with the side of the first substrate on which the first insulating layer is formed, and forming the first groove in the first base of the second substrate, the projection of the first groove in the direction perpendicular to the surface of the first substrate is offset from the position of the first insulating layer in the first substrate, so that a new SOI substrate (including a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top) can be formed, and the formed SOI substrate includes two device regions, namely a first device region and a second device region, the lower substrate of the first device region includes the first substrate below the first groove, the lower substrate of the second device region includes the first substrate below the first insulating layer, the insulating buried layer of the first device region includes the second insulating layer, the insulating buried layer of the second device region includes the second insulating layer and the first insulating layer, and the semiconductor layer of the first device region includes the bottom of the first groove The first substrate in the part, the semiconductor layer in the second device area includes the first substrate above the first insulating layer, so that the top surface of the lower substrate in the first device area is higher than the top surface of the lower substrate in the second device area, the top surface of the insulating buried layer in the first device area is flush with the top surface of the insulating buried layer in the second device area, and the top surface of the semiconductor layer in the first device area is lower than the top surface of the semiconductor layer in the second device area. Therefore, the thickness of the insulating buried layer in the first device area is less than the thickness of the insulating buried layer in the second device area, and the thickness of the semiconductor layer in the first device area is less than the thickness of the semiconductor layer in the second device area, so that the first device area can be used to form a fully depleted device (FDSOI device), and the second device area can be used to form a partially depleted device (PDSOI device), so that the fully depleted device and the partially depleted device are integrated on the same SOI substrate, so that the fully depleted device and the partially depleted device are compatible.

For example, in the embodiments shown in Figures 1 and 15, the formed SOI substrate includes a first device area A1 and a second device area A2, the second substrate 11 and the first semiconductor layer 13 of the first device area A1 together constitute the lower substrate of this area, the second substrate 11 of the second device area A2 serves as the lower substrate of this area, the second insulating layer 22 of the first device area A1 constitutes an insulating buried layer of this area, the first insulating layer 12 and the second insulating layer 22 of the second device area A2 together constitute an insulating buried layer of this area, and the first substrate 21 of the first device area A1 and the second device area A2 serve as semiconductor layers of these two areas respectively. Therefore, the thickness of the insulating buried layer of the first device area A1 is less than the thickness of the insulating buried layer of the second device area A2, and the thickness of the semiconductor layer of the first device area A1 is less than the thickness of the semiconductor layer of the second device area A2.

The method for manufacturing the semiconductor device may further include:

A gate structure is formed on the semiconductor layer of the first device region and the second device region; the gate structure may include a gate dielectric layer, a gate layer and a sidewall, the gate dielectric layer and the gate layer are formed on the semiconductor layer from bottom to top, and the sidewall is formed on the sidewalls of the gate dielectric layer and the gate layer.

A source region and a drain region are formed on both sides of the gate structure; wherein, in the first device region, the source region and the drain region are formed on the first substrate on both sides of the gate structure; and in the second device region, the source region and the drain region are formed in the first substrate on both sides of the gate structure.

In addition, since the SOI substrate is formed by bonding the second substrate to the first substrate, the first substrate and/or the second substrate can be processed before bonding to form a structure in the first substrate and/or the second substrate that can optimize the performance of the SOI substrate, thereby improving the performance of the semiconductor device.

In one embodiment, as shown in FIG2 , a first conductive layer 14 electrically connected to the semiconductor layer and the underlying substrate may be formed in the insulating buried layer of the first device area A1, and a second conductive layer 15 electrically connected to the semiconductor layer and the underlying substrate may be formed in the insulating buried layer of the second device area A2. Among them, in the second device area A2, the second conductive layer 15 is located on the side of the source area or the drain area away from the gate structure, so that the source area or the drain area can be connected to the lower substrate through the second conductive layer 15, so that the heat generated in the semiconductor layer during the operation of the partially depleted device can be quickly transferred to the lower substrate through the second conductive layer 15, so as to be dissipated in time through the lower substrate; in the first device area A1, the first conductive layer 14 is located on the side of the source area or the drain area away from the gate structure, so that the source area or the drain area can be connected to the lower substrate through the first conductive layer 14, so that the heat generated in the semiconductor layer during the operation of the fully depleted device can be quickly transferred to the lower substrate through the first conductive layer 14, so as to be dissipated in time through the lower substrate. Thereby, the temperature rise of the entire semiconductor device is avoided, and the mobility of the semiconductor device is avoided to be reduced, thereby avoiding the reduction of the channel current. The first conductive layer 14 and the second conductive layer 15 can be formed by a multi-step process, and the materials of the first conductive layer 14 and the second conductive layer 15 include but are not limited to metal materials or semiconductor materials.

In summary, the manufacturing method of the semiconductor device provided by the present invention includes: forming a first substrate, in which a first insulating layer is formed; forming a second substrate, in which the second substrate includes a first base and a second insulating layer formed on the first base; bonding the side of the second substrate formed with the second insulating layer to the side of the first substrate formed with the first insulating layer; forming a first groove in the first base, wherein the projection of the first groove in a direction perpendicular to the surface of the first substrate is offset from the position of the first insulating layer, so as to form a first device area and a second device area. The manufacturing method of the semiconductor device of the present invention enables fully depleted devices and partially depleted devices to be integrated on the same substrate.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims (10)

1. A semiconductor device, comprising: the SOI substrate comprises a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, wherein the SOI substrate comprises a first device region and a second device region, the top surface of the lower substrate of the first device region is higher than the top surface of the lower substrate of the second device region, the top surface of the insulating buried layer of the first device region is flush with the top surface of the insulating buried layer of the second device region, and the top surface of the semiconductor layer of the first device region is lower than the top surface of the semiconductor layer of the second device region.

2. The semiconductor device according to claim 1, wherein the buried insulating layer of the second device region includes a first insulating layer and a second insulating layer from bottom to top, the buried insulating layer of the first device region including the second insulating layer; the first device region is flush with a bottom surface of the second insulating layer of the second device region.

3. The semiconductor device of claim 2, wherein the buried insulating layer of the first device region further comprises a third insulating layer, the third insulating layer being located between the second insulating layer and the underlying substrate, the third insulating layer having a thickness that is less than a thickness of the first insulating layer; or the buried insulating layers of the first device region and the second device region each further comprise a third insulating layer, the third insulating layer of the first device region is located between the second insulating layer and the lower substrate, and the third insulating layer of the second device region is located between the first insulating layer and the second insulating layer.

4. The semiconductor device according to claim 1, wherein the semiconductor device further comprises:

And the groove isolation structure is formed at the junction of the first device region and the second device region, and extends from the semiconductor layer to the lower substrate.

5. A method of manufacturing a semiconductor device, comprising:

Forming a first substrate, wherein a first insulating layer is formed in the first substrate;

forming a second substrate comprising a first base and a second insulating layer formed on the first base;

Bonding one surface of the second substrate, on which the second insulating layer is formed, with one surface of the first substrate, on which the first insulating layer is formed;

Forming a first groove in the first base, wherein the projection of the first groove in the direction vertical to the surface of the first substrate is staggered with the position of the first insulating layer, so as to form an SOI substrate, the SOI substrate comprises a lower substrate, a buried insulating layer and a semiconductor layer from bottom to top, and the SOI substrate comprises a first device region and a second device region;

wherein the lower substrate of the first device region includes the first substrate under the first trench, the lower substrate of the second device region includes the first substrate under the first insulating layer, the buried insulating layer of the first device region includes the second insulating layer, the buried insulating layer of the second device region includes the second insulating layer and the first insulating layer, the semiconductor layer of the first device region includes the first base at the bottom of the first trench, and the semiconductor layer of the second device region includes the first base above the first insulating layer such that the top surface of the lower substrate of the first device region is higher than the top surface of the lower substrate of the second device region, the top surface of the buried insulating layer of the first device region is flush with the top surface of the buried insulating layer of the second device region, and the top surface of the semiconductor layer of the first device region is lower than the top surface of the semiconductor layer of the second device region.

6. The method for manufacturing a semiconductor device according to claim 5, wherein the step of forming the first substrate comprises:

Providing a second substrate, wherein a first insulating layer is formed on the second substrate;

Forming a second trench penetrating the first insulating layer;

Forming a first semiconductor layer in the second trench, wherein the second substrate, the first semiconductor layer and the first insulating layer together form the first substrate;

Or the step of forming the first substrate comprises:

providing a second substrate;

forming a third groove in the second substrate;

And forming a first insulating layer in the third groove, wherein the second substrate and the first insulating layer jointly form the first substrate.

7. The method for manufacturing a semiconductor device according to claim 5, wherein after the first substrate is formed, the method for manufacturing a semiconductor device further comprises:

forming a third insulating layer in the first substrate at the periphery of the first insulating layer, wherein the thickness of the third insulating layer is smaller than that of the first insulating layer;

Or forming a third insulating layer on the first substrate, wherein the third insulating layer also covers the first insulating layer.

8. The method for manufacturing a semiconductor device according to claim 5, wherein the step of forming the second substrate comprises:

providing a first substrate;

Forming a second insulating layer on the first substrate.

9. The method of manufacturing a semiconductor device according to claim 5, wherein before forming the first trench in the first substrate, the method further comprises:

and thinning one surface of the first substrate far away from the second insulating layer.

10. The method for manufacturing a semiconductor device according to claim 5, wherein the method for manufacturing a semiconductor device further comprises:

And forming a groove isolation structure at the junction of the first device region and the second device region, wherein the groove isolation structure extends from the first base to the first substrate.