JP2006310726A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve characteristics of a semiconductor device in a high frequency region. <P>SOLUTION: A semiconductor device 20A is formed with an emitter pad electrode 23E, a collector pad electrode 23C, and a base pad electrode 23B connected with an active region 21, on the surface of a semiconductor substrate 25. Further, a back electrode 26 is formed on the backside of the semiconductor substrate 25. Further, the emitter pad electrode 23E connected with a ground potential is connected with the back electrode 26 through a through-electrode 24A that passes through the semiconductor substrate 25 in a thickness direction. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a through electrode penetrating a semiconductor substrate and a manufacturing method thereof.

  A circuit device 100 incorporating a conventional semiconductor device 105 will be described with reference to the perspective view of FIG. 13 (see, for example, Patent Document 1 below).

  The circuit device 100 has a structure in which a semiconductor device 105 is mounted on the surface of a land 112 arranged at the center. Leads 101B and 101D are led out from both ends of the land 112 to the outside. Furthermore, the leads 101A and 101C are located on both sides of the land 112. The entire circuit device 100 is covered with a sealing resin 104.

Here, the semiconductor device 105 is a bipolar transistor, and an emitter electrode, a collector electrode, and a base electrode are formed on the surface thereof. The collector electrode and the base electrode formed on the surface of the semiconductor device 105 are connected to the lead 101C and the lead 101A via the metal thin wire 103. Further, the emitter electrode of the semiconductor device 105 is connected to the land 112 through the fine metal wire 103. Here, the two emitter electrodes formed on the surface of the semiconductor device 105 are connected to the land 112 through the fine metal wire 103. In addition, the emitter electrode is connected to the ground potential in order to obtain voltage gain and current gain.
JP 2004-102345 A

  However, in the circuit device 100 in which the semiconductor device 105 described above is built, the land 112 becomes larger than that of the semiconductor device 105, which has a problem of hindering the miniaturization of the circuit device 100. Specifically, in order to connect the emitter electrode of the semiconductor device 105 and the land 112, an area for wire bonding the metal thin wire 103 must be secured in the periphery of the land 112. Therefore, when the planar size of the semiconductor device 105 is 0.3 mm × 0.3 mm, the planar size of the land 112 is required to be about 1.5 mm × 1.5 mm or more. That is, the land 112 having an area about 25 times the size of the semiconductor device 105 to be mounted is required, and this hinders the miniaturization of the circuit device 100 as a whole.

  Furthermore, a parasitic inductance component is generated in the thin metal wire 103, and there is a problem that the high frequency characteristics of the semiconductor device 105 are deteriorated. The magnitude of the parasitic inductance generated by the fine metal wire 103 is proportional to the length of the fine metal wire 103 and further inversely proportional to the thickness of the fine metal wire 103. Therefore, for example, when the thin metal wire 103 having a diameter of 25 μm and a length of 1 mm is employed, a large parasitic inductance is generated, and the high frequency characteristics of the semiconductor device 105 are deteriorated. In particular, in the case of the semiconductor device 105 operating at a high frequency of 1 GHz or more, the high frequency characteristics are greatly deteriorated due to the parasitic inductance.

  The present invention has been made in view of the above problems, and a main object of the present invention is to provide a semiconductor device that contributes to downsizing of the entire device and has reduced parasitic inductance, and a method for manufacturing the same.

  A semiconductor device of the present invention includes a plurality of pad electrodes formed on the surface of a conductive substrate and electrically connected to an active region, a back electrode provided on the back surface of the semiconductor substrate, and the semiconductor substrate in the thickness direction. A through electrode that penetrates and connects the pad electrode and the back electrode is connected, and at least one of the pad electrodes connected to a ground potential is connected to the back electrode through the through electrode. It is characterized by.

  Furthermore, the semiconductor device of the present invention is characterized in that a plurality of the pad electrodes are connected to the back electrode through the through electrodes.

  Further, in the semiconductor device of the present invention, a bipolar transistor is formed in the active region, and the pad electrode connected to the emitter region of the bipolar transistor is connected to the back electrode through the through electrode. And

  Furthermore, in the semiconductor device of the present invention, a MOSFET is formed in the active region, and the pad electrode connected to the source region of the MOSFET is connected to the back electrode through the through electrode. .

  Furthermore, in the semiconductor device of the present invention, the back electrode of the semiconductor substrate is fixed to a land-like conductive member, and the pad electrode connected to a ground potential is connected to the conductive member via the through electrode and the back electrode. It is connected to.

  Furthermore, the semiconductor device of the present invention is characterized in that the other pad electrode that is not connected to the ground potential is electrically connected to another conductive member through a thin metal wire.

  Furthermore, the semiconductor device of the present invention is characterized in that the back electrode is in direct contact with the back surface of the semiconductor substrate, and the through electrode and the semiconductor substrate have the same potential.

  Furthermore, the semiconductor device of the present invention is characterized in that a plurality of back surface electrodes are formed on the back surface of the semiconductor substrate, and each of the back surface electrodes is electrically connected to the pad through the through electrode.

  Furthermore, the semiconductor device of the present invention is characterized in that the back electrode is insulated from the semiconductor substrate via an insulating film covering the back surface of the semiconductor substrate.

  Furthermore, the semiconductor device of the present invention is characterized in that all of the pad electrodes connected to the active region are connected to the back electrode through the through electrode.

  Furthermore, in the semiconductor device of the present invention, the active region is formed inside a region surrounded by the isolation region, and the through electrode is formed inside a through hole penetrating the semiconductor substrate outside the isolation region, The through electrode is in contact with an inner wall of the through hole.

  Furthermore, the semiconductor device of the present invention includes a semiconductor substrate having a semiconductor layer on which an active element is formed, a first electrode electrically connected to one diffusion region of the active element, and the first electrode. A pad electrode extending around the semiconductor substrate, a through electrode provided in a lower layer of the pad electrode and extending from the semiconductor layer surface to the back surface of the semiconductor substrate, and electrically connected to the through electrode And a back surface electrode provided on the back surface of the semiconductor substrate.

  Furthermore, in the semiconductor device of the present invention, the active element is a BIP-type or MOS-type transistor, and the first electrode electrically connected to the grounded diffusion region is electrically connected to at least two through electrodes. It is connected to.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming an active region on a surface of a semiconductor substrate, a step of forming a pad electrically connected to the active region on the surface of the semiconductor substrate, and a lower portion of the pad Forming a through-hole penetrating the semiconductor substrate located at a position, and forming a back electrode electrically connected to the pad on the back surface of the semiconductor substrate through a through-electrode formed inside the through-hole Forming the through hole outside the isolation region formed so as to surround the active region, and forming the through electrode in direct contact with the inner wall of the through hole. It is characterized by.

  Furthermore, the method for manufacturing a semiconductor device according to the present invention is characterized in that the isolation region has a trench structure, a LOCOS oxide film, or a PN junction isolation structure.

  According to the semiconductor device of the present invention, the pad electrode formed on the surface of the semiconductor substrate and the back electrode formed on the back surface of the semiconductor substrate can be connected via the through electrode penetrating the semiconductor substrate. Accordingly, it is possible to connect the pad electrode to the outside through the through electrode and the back electrode without using a fine metal wire. Thus, the land on which the semiconductor device is mounted can be reduced in size to the same extent as the semiconductor device, and the entire device in which the semiconductor device is incorporated is also reduced in size.

  Furthermore, according to the semiconductor device of the present invention, it is possible to connect the pad electrode and the outside by using a through electrode having a path shorter and thicker than the fine metal wire. For this reason, for example, even in the case of a semiconductor device that operates at a high frequency of 1 GHz or more, the parasitic inductance can be reduced, so that the high-frequency characteristics can be improved.

  Furthermore, according to the method of manufacturing a semiconductor device of the present invention, the through electrode can be formed directly inside the through hole penetrating the semiconductor substrate by separating the active region from the isolation region. That is, it is not necessary to insulate the inside of the through hole using a technique such as a thermal oxidation method. Accordingly, a heating step such as a thermal oxidation method for heating the semiconductor substrate to a high temperature can be omitted, so that the yield can be improved.

<First Embodiment>
In this embodiment, a structure of a semiconductor device including a through electrode penetrating a semiconductor substrate will be described with reference to FIGS.

  With reference to FIG. 1, a configuration of a circuit device 10A in which a semiconductor device 20A of the present invention is incorporated will be described. 1A is a perspective view of the circuit device 10A, and FIG. 1B is a cross-sectional view of the semiconductor device 20A.

  Referring to FIG. 1A, here, a semiconductor device 20A is built in a lead frame type circuit device 10A. Specifically, the semiconductor device 20 </ b> A is fixed to the upper surface of the land 12 disposed at the center. Further, from the end of the land 12, two leads 11D and 11B extend outward. Further, a lead 11 </ b> A and a lead 11 </ b> C are provided close to the land 12. The land 12 and the lead 11A are examples of conductive members. As the conductive member, a conductive pattern as shown in FIG. 2 (A) or FIG. 2 (B) may be used.

  The semiconductor device 20A is fixed to the top of the land 12 via a conductive adhesive such as solder. Four pad electrodes 23 are formed on the upper portion of the semiconductor device 20A. Here, the two pad electrodes 23 are electrically connected to the land 12 through the through electrodes 24A. The other two pad electrodes 23 are connected to the leads 11A and 11C through the fine metal wires 13, respectively.

  The through electrode 24 </ b> A provided in the semiconductor device 20 </ b> A may be made of a film-like metal formed in a through hole that penetrates the semiconductor substrate 25. Furthermore, the through electrode 24A can be formed by filling the through hole with a metal such as solder, W, Cu, or Al.

  The lead 11A and the lead 11C are connected to the pad electrode 23 of the semiconductor device 20A through the fine metal wire 13. Here, the pad electrode 23 connected to the collector electrode and the base electrode is connected to the lead 11A and the lead 11C via the thin metal wire 13.

  The sealing resin 14 seals the whole with the leads 11A, 11B, 11C, and 11D partially exposed to the outside.

  Next, the semiconductor device 20A fixed to the land 12 will be described with reference to FIG. In this semiconductor device 20 </ b> A, an active region 21 is formed on the surface of a semiconductor substrate 25. Here, the active region 21 is a region where an active element such as a transistor or a diode is generally formed. When a bipolar transistor is formed in the active region 21, a collector region, a base region, and an emitter region are formed. Further, when a MOSFET is formed in the active region 21, a gate region, a source region, and a drain region are formed. Further, an IC or LSI may be formed in the active region 21. A pad electrode 23 electrically connected to the diffusion region formed in the active region 21 is formed on the surface of the semiconductor substrate 25 via the rewiring 22 extending to the periphery of the active region 21. ing. Further, a back electrode 26 is formed on at least a part of the back surface of the semiconductor substrate 25. Here, since the back surface is used as the emitter electrode, the back surface electrode 26 is formed on the entire surface. Further, a penetrating electrode 24 </ b> A that penetrates the semiconductor substrate 25 in the thickness direction is formed so as to reach the back surface of the pad electrode 23.

  Here, the back surface of the semiconductor substrate 25 may be insulated. Further, the through electrode 24A and the semiconductor substrate 25 may be insulated by, for example, a Si oxide film by thermal oxidation or CVD.

  Further, the back electrode 26 of the semiconductor device 20 </ b> A is fixed to the surface of the land 12 through the fixing material 15. As the fixing material 15, solder, conductive paste, or the like can be used. Here, since the land 12 is at a fixed potential (GND or Vcc), the pad electrode 23 is connected to the fixed potential. Thus, a desired electrode can be fixed at a stable potential, and the operation of the transistor formed in the active region 21 can be stabilized.

  For example, conventionally, an emitter, a collector, and a base electrode are connected to a lead through a fine metal wire. However, the impedance of the thin metal wire is not negligible. In the present invention, the through electrode 24A is employed instead of the fine metal wire, and the short path portion, that is, the semiconductor substrate 25 is formed so that the path is short and the impedance can be lowered. Moreover, even when a large current is passed, it is sufficient to increase the diameter of the through electrode 24A, and the impedance of the path connected to the emitter electrode can be reduced. Therefore, the characteristics can be significantly improved as compared with a package in which the emitter electrode is connected by a thin metal wire.

  Next, configurations of circuit devices 10B and 10C of other forms will be described with reference to FIG. 2A is a cross-sectional view of the circuit device 10B including the circuit board 19, and FIG. 2B is a cross-sectional view of the circuit device 10C including the conductive patterns 18A and 18B embedded in the sealing resin 14. is there.

  Referring to FIG. 2A, in circuit device 10B, conductive patterns 18A and 18B formed on the surface of circuit board 19 are electrically connected to semiconductor device 20A. As the circuit board 19, a board made of a resin such as a flexible sheet or a printed board or a ceramic board can be generally adopted. The conductive pattern 18 </ b> A formed on the surface of the circuit board 19 is connected to the semiconductor device 20 </ b> A through the thin metal wire 13. The conductive pattern 18B is connected to the back electrode 26 of the semiconductor device 20A through a fixing material 15 such as solder. The conductive patterns 18 </ b> A and 18 </ b> B are connected to a conductive pattern formed on the back surface of the circuit board 19 through a through hole formed in the circuit board 19. Further, a sealing resin 14 is formed on the surface of the circuit board 19 so as to cover the semiconductor device 20A and the fine metal wires 13.

  By employing the through electrode 24A, it is not necessary to connect the conductive pattern 18B and the semiconductor device 20A using a fine metal wire, and therefore the size of the conductive pattern 18B can be reduced to the same level as the semiconductor device 20A. Therefore, the overall size of the circuit board 19 can be reduced.

  Referring to FIG. 2B, in circuit device 10C, conductive patterns 18A and 18B embedded in sealing resin 14 are electrically connected to semiconductor device 20A. The conductive patterns 18A and 18B are embedded in the sealing resin 14 with the back surface exposed. Further, the back surfaces of the conductive patterns 18A and 18B exposed from the sealing resin 14 are covered with a coating resin 45 except for a portion where a brazing material is formed. Further, the conductive pattern 18A and the conductive pattern 18B are separated by a separation groove 44. This structure can be realized by, for example, pasting a pattern such as a lead frame on a flexible sheet, peeling off the flexible sheet after mounting and molding. Also, prepare Cu foil, half-etch to leave the conductive pattern in a protruding shape, and after mounting and molding, etch the back surface of the Cu foil so that the sealing resin filled in the half-etched groove is exposed It can be realized by backing up.

  Next, the semiconductor device 20A will be described with reference to FIGS. 3A is a perspective view of the semiconductor device 20A, and FIG. 3B is a plan view of the semiconductor device 20A viewed from above. 4A is a cross-sectional view of the semiconductor device 20A, and FIG. 4B is a plan view showing a schematic pattern of the active region 21. FIG. FIG. 4C illustrates a configuration of another form of the semiconductor device 20B.

  Referring to FIGS. 3A and 3B, an active region 21 is formed at the center of the surface of the semiconductor substrate 25. A collector pad electrode 23C, a base pad electrode 23B, and an emitter pad electrode 23E are formed on the periphery of the surface of the semiconductor substrate 25. Each pad electrode and the active region 21 are connected by a rewiring 22.

  Here, since the semiconductor device 20A is used in the grounded emitter circuit, the emitter pad electrode 23E is connected to the back electrode 26 through the through electrode 24A. Therefore, when the semiconductor device 20A is used in the base ground circuit, the base pad electrode 23B is connected to the back electrode 26 through the through electrode 24A. When the semiconductor device 20A is used in a collector ground circuit, the collector pad electrode 23C is connected to the back electrode 26 through the through electrode 24A. In this embodiment, the through electrode 24A is employed to reduce the impedance. Furthermore, since the two through electrodes 24A are employed, the impedance of the through electrodes is connected in parallel and halved. That is, if one electrode is connected in parallel via n (three or more) through electrodes 24A, the impedance becomes 1 / n.

  Further, in the active region 21, for example, a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) other than the bipolar transistor can be formed. In this case, a pad electrode (either a drain electrode, a source electrode or a gate electrode) connected to the ground potential is connected to the back electrode 26 via the through electrode 24A. In particular, when the circuit device 20 is used in a source grounded circuit having a large gain, the pad connected to the source electrode is connected to the back electrode 26 through the through electrode 24A. Again, by using a plurality of through electrodes 24A, the impedance can be connected in parallel and can be reduced.

Details of the active region 21 will be described with reference to FIG. An N ⁺ type buried layer 43 is provided above the P type semiconductor substrate 42, and an N ⁻ type epitaxial layer 31 is formed thereon. Further, a P ⁺ type external base region 34 A, a P type active base region 34 B, and an N ⁺ type collector contact region 37 are formed on the surface of the N ⁻ type epitaxial layer 31. Further, an N-type emitter region 35 is formed above the active base region 34B. The N ⁺ -type collector contact region 37 is formed from the surface of the N ⁻ -type epitaxial layer 31 until it reaches the N ⁺ -type buried layer 43.

The trench 33 extends from the surface of the N ⁻ -type epitaxial layer 31 until it reaches the P-type semiconductor substrate 42, and an oxide film 32 is embedded therein. An isolation region including a trench 33 is formed so as to surround the active region 21, and the active region 21 is isolated. Here, the active region 21 is isolated by the trench structure, but the active region 21 may be isolated by a LOCOS (Local Oxidation of Silicon) oxide film or PN junction isolation. Further, an oxide film may be formed on the surface of the trench 33, and the element may be isolated with polysilicon buried therein.

  The emitter pad electrode 23E is formed at a position outside the trench 33, and is connected to the back electrode 26 through the through electrode 24A.

The through electrode 24A is made of a conductive material embedded in a through hole formed so as to penetrate the P type semiconductor substrate 42, the N ⁻ type epitaxial layer 31 and the oxide film 32. The emitter pad electrode 23E and the back electrode 26 are connected by the through electrode 24A. The through electrode 24 </ b> A can be formed of a plating film that is integrated with the back electrode 26. This plating film is formed on the side wall of the through hole and the back surface of the P-type semiconductor substrate 42. A sidewall insulating film 41 made of a silicon oxide film or the like is formed on the side surface of the through electrode 24A.

Since the P-type semiconductor substrate 42 is separated from the active region 21 by the trench 33 and the buried layer 43, the sidewall insulating film 41 does not have to be formed between the P-type semiconductor substrate 42 and the through electrode 24A. For example, when a P ⁺ type isolation region or the like penetrating the epitaxial layer 31 is formed, the P type semiconductor substrate 42 is fixed to GND, and the emitter electrode is fixed to a potential other than GND, an insulating film is required. . That is, when the potentials of the P-type semiconductor substrate 42 and the emitter electrode are different, the sidewall insulating film 41 is necessary.

  Furthermore, the through electrode 24A may be formed by filling the through hole with solder, an alloy such as W, Cu or Al, or a metal. In particular, when the through electrode 24A made of W or Cu is formed, the surface of the through hole is preferably protected by a barrier film made of a Ti / TiN laminated film or a Ta / TaN laminated film.

The back electrode 26 is formed on the back surface of the P-type semiconductor substrate 42 and connected to the through electrode 24A. The back electrode 26 and the P-type semiconductor substrate 42 are insulated via an insulating film when the semiconductor substrate 42 is not electrically separated from the active region 21. When the semiconductor substrate 42 and the active region 21 are electrically separated by the trench 33 and the P-type semiconductor substrate 42 and the N ⁺ -type buried layer 43, the back electrode is directly on the back surface of the P-type semiconductor substrate 42. 26 may be contacted.

  By bringing the back electrode 26 and the P-type semiconductor substrate 42 into direct contact, the parasitic capacitance generated between the P-type semiconductor substrate 42 and the through electrode 24A can be reduced. Specifically, when the sidewall insulating film 41, which is an insulator, is located between the P-type semiconductor substrate 42 and the through electrode 24A, a parasitic capacitance is generated due to a potential difference. When the back electrode 26 electrically connected to the through electrode 24A is in direct contact with the P-type semiconductor substrate 42, the through electrode 24A and the P-type semiconductor substrate 42 can have the same potential, and the parasitic capacitance described above can be obtained. Can be reduced.

  With reference to FIG. 4B, the structure of the active region 21 will be further described. 4A is a cross-sectional view taken along line A-A ′ of FIG. An active region 21 is formed in a region surrounded by the trench 33. Within the active region 21, two emitter regions 35 are formed vertically long, and an active base region 34 </ b> B is formed so as to surround the emitter region 35. Therefore, the emitter electrode 27E is formed by two comb teeth, and is integrally connected to the upper left and lower right emitter pad electrodes 23E of the chip via the rewiring 22 from the emitter electrode 27E. On the other hand, the base electrode 27B is formed by two comb teeth so as to be in contact with the external base region 34A and alternately arranged with the emitter electrode 27E, and is connected to the base pad electrode 23B on the lower left of the chip via the rewiring 22. The Furthermore, the collector electrode 27 </ b> C is in contact with the collector contact region 37 reaching the buried layer 43 and is formed on the left side of the active region 21. The collector electrode 27C is connected to the collector pad electrode 23C formed on the upper right side of the chip via the rewiring 22.

  In the present embodiment, pad electrodes such as the emitter pad electrode 23E are provided outside the trench 33 that is the isolation region. The reason is as follows.

  First, even if the through electrode 24A is formed in the emitter, base, and collector regions, the width of these regions is 1 μm or less. Therefore, problems such as alignment when the through electrode 24A is formed occur. Second, when a pad electrode is disposed on or in the vicinity of the active region 21, parasitic capacitance or the like is generated in the element. Therefore, by forming a sufficiently large pad electrode on the outer side of the separation region and forming the through electrode 24A on the back surface thereof, a good manufacturing method and characteristics can be obtained.

  With reference to FIG. 4C, the structure of another form of semiconductor device 20B will be described. The basic configuration of the semiconductor device 20B is the same as that of the semiconductor device 20A described above, and the difference is that the sidewall insulating film 41 (see FIG. 4A) is omitted.

  Specifically, the inner wall of the through hole 24B is not covered with the side wall insulating film 41 as described above. Accordingly, the through electrode 24A made of a conductive material such as copper is in direct contact with the side wall of the through hole 24B made of a semiconductor. Thus, the configuration of the semiconductor device 20B can be simplified. In addition, since the step of manufacturing the sidewall insulating film 41 can be omitted, the manufacturing cost of the semiconductor device 20B can be reduced.

  The active region 21 in which the bipolar transistor is formed is surrounded by the trench 33 and is electrically isolated from other regions. Further, the through electrode 24 </ b> A is located outside the region surrounded by the trench 33. Therefore, the active region 21 and the through electrode 24A are electrically separated by the trench 33. For this reason, even if the through electrode 24A directly contacts the semiconductor substrate 42, the active region 21 and the through electrode 24A do not short-circuit.

  Next, referring to FIG. 5, a simulation result performed to confirm the effect of the present embodiment will be described. FIG. 5A is an equivalent circuit of a circuit device including a semiconductor device 20A that is a bipolar transistor. FIG. 5B is a graph showing frequency characteristics of the semiconductor device.

  Referring to FIG. 5A, parasitic inductance is generated in a path connected to each electrode of the bipolar transistor used in the grounded emitter circuit. Here, the parasitic inductance of the path connected to the base electrode is expressed as Lb, the parasitic inductance of the path connected to the collector electrode is expressed as Lc, and the parasitic inductance of the path connected to the emitter electrode is expressed as Le. . In addition, a predetermined parasitic capacitance is generated between the electrodes of the transistor.

  In this embodiment, the Le is reduced by using the through electrode 24A penetrating the semiconductor substrate instead of the fine metal wire connected to the emitter pad electrode. Here, Le in the conventional example using a thin metal wire is assumed to be 1.0 nH, and Le in the present embodiment using the through electrode 24A is assumed to be 0.5 nH, which is half of the conventional value. Further, the values of other parasitic inductances and parasitic capacitances are the same as those in the conventional example and the present embodiment, and the change in forward transfer gain with respect to the change in frequency is measured.

  With reference to FIG. 5 (B), the simulation result performed on said conditions is demonstrated. The horizontal axis of this graph represents frequency, and the vertical axis represents forward transfer gain. The results obtained under the conventional conditions are indicated by dotted lines, and the results obtained under the conditions of the present application are indicated by solid lines.

  From this graph, it can be understood that the forward transfer gain of the semiconductor device of this embodiment using the through electrode is larger than that of the conventional example using the fine metal wire, particularly in the high frequency region. Specifically, in a relatively low frequency region with a frequency of 100 MHz, the transfer gain of the semiconductor device of this embodiment is almost the same as that of the conventional device (about 30 dB). When the frequency increases, the transmission gain decreases in both this embodiment and the conventional technique. This is because the parasitic capacitance and parasitic inductance described above increase as the frequency increases. However, in the semiconductor device of this embodiment using the through electrode, the decrease in transmission gain accompanying an increase in frequency is small as compared with the conventional example. For example, in the frequency band of 1 GHz (1000 MHz), the transfer gain of this embodiment is superior to the conventional example by about 2 to 2.5 dB. Therefore, the characteristics of the semiconductor device of this embodiment can be improved particularly in a high frequency region.

  Hereinafter, advantages of the present embodiment will be described.

  Referring to FIG. 3, in this embodiment, the emitter pad electrode 23E connected to the ground potential is connected to the back electrode 26 through the through electrode 24A, thereby reducing the parasitic inductance of the path connected to the emitter electrode. Can be made.

  Specifically, the emitter pad electrode 23E is connected to a land (not shown) located below the back electrode 26 through the through electrode 24A. Therefore, the emitter electrode 23E and the land (not shown) are connected by the shortest path that penetrates the semiconductor substrate 25. Further, the through electrode 24A has a very large diameter as compared with the thin metal wire. Specifically, the diameter of the fine metal wire is 20 μm and the length is 1 mm, whereas the diameter of the through electrode 24A is 70 μm and the length is 150 μm. As described above, the magnitude of the parasitic inductance is proportional to the length of the path and inversely proportional to the thickness of the path. Therefore, in comparison with the conventional example that is connected using a thin metal wire, in this embodiment, the use of the through electrode 24A having a short path and a large thickness greatly reduces the parasitic inductance of the path connected to the emitter electrode. Is done. Therefore, particularly when the semiconductor device 20A performs switching at a high frequency of 1 GHz or more, the effect of improving the characteristics by using the through electrode 24A is increased.

  It is also possible to connect a pad electrode (collector pad electrode 23C or base pad electrode 23B) other than the emitter pad electrode 23E to the back electrode 26 using the through electrode 24A. However, when the collector pad electrode 23C is connected to the back electrode 26 through the through electrode 24A, the length of the wiring connected to the collector electrode is increased, the parasitic capacitance between the collector and the base is increased, and the high frequency characteristics are deteriorated. End up. The same applies to the case where the base pad electrode 23B is connected to the back electrode 26 via the through electrode 24A. Therefore, as described above, the emitter pad electrode 23E is preferably connected using the through electrode 24A, and the other base pad electrode 23B and the collector pad electrode 23C are preferably connected to the outside using a thin metal wire.

  Furthermore, referring to FIG. 1, according to the present embodiment, since the land 12 can be made smaller than the semiconductor device 20A, the entire circuit device 10A can be reduced in size. Specifically, the pad electrode 23 and the land 12 formed on the surface of the semiconductor device 20 </ b> A are connected via a through electrode 24 </ b> A that penetrates the semiconductor substrate 25. That is, the pad electrode 23 and the land 12 are connected without depending on the fine metal wire. Therefore, it is not necessary to provide a region for wire bonding of the fine metal wire on the surface of the land 12. Thus, the size of the land 12 can be made substantially the same as that of the semiconductor device 20A. Actually, the land 12 is formed slightly larger than the semiconductor device 20A in consideration of the positional deviation when the semiconductor device 20A is fixed. For example, the length L1 of one side of the semiconductor device 20A is 0.3 mm, and the length L2 of one side of the land 12 is about 0.4 mm. Therefore, compared with the conventional example, the length of the side of the land 12 can be reduced to about 1/3.

<Second Embodiment>
Next, a method for manufacturing the semiconductor device 20A whose structure is shown in FIG. 4A will be described with reference to FIGS. First, a method for forming the active region 21 made of a bipolar transistor will be described with reference to FIG.

6A, first, an N ⁺ type buried layer 43 is provided on the surface of a P-type semiconductor substrate 42 having a thickness of about 600 μm by an ion implantation method. Further, an N ⁻ type epitaxial layer 31 is formed on the upper surface of the P type semiconductor substrate 42. The thickness of the N ⁻ type epitaxial layer 31 is about 1.5 μm. Thereafter, the entire surface is oxidized to form an oxide film 32 having a thickness of about 0.05 μm on the upper surface of the N ⁻ -type epitaxial layer 31.

Referring to FIG. 6B, next, a trench 33 is formed so as to surround the active region to be formed, and the inside of the trench 33 is filled with an oxide film. Here, the oxide film 32 and the N ⁻ type epitaxial layer 31 where the trench 33 is formed are selectively removed by lithography. The removal of the oxide film 32 is performed using a CF ₄ gas. The removal of the N ⁻ type epitaxial layer 31 is performed by dry etching using a halogen-based gas. The trench 33 needs to reach the P-type semiconductor substrate 42. The specific depth of the trench 33 is, for example, about 3.5 μm. After the trench 33 is formed, the inside of the trench 33 is filled with the oxide film 32 by performing an oxidation process. Here, instead of the trench 33, isolation by a LOCOS oxide film or a PN junction may be performed.

Referring to FIG. 6C, next, collector contact region 37, external base region 34A, and active base region 34B are formed by ion implantation. The collector contact region 37 is formed until reaching the N ⁺ type buried layer 43, and phosphorus (P) is adopted as an ion species. Furthermore, a P ⁺ -type external base region 34A and a P-type active base region 34B are formed by ion implantation. Boron (B) is employed as the ion species implanted to form the external base region 34A and the active base region 34B.

  Referring to FIG. 6D, next, oxide film 32 is partially removed to provide an opening having a diameter of about 0.5 μm, and emitter electrode 27E, base electrode 27B, and collector electrode 27C are formed. To do. Here, the emitter region 35 is formed by diffusing arsenic ions in the polysilicon constituting the emitter electrode 27E. These electrodes are formed by sequentially depositing Ti, Pt, and Au by vacuum vapor deposition and performing etching so as to obtain a desired shape. The emitter electrode 27E is formed outside the trench 33 as an emitter pad electrode 23E. The collector electrode 27 </ b> C is also formed as a collector pad electrode 23 </ b> C outside the trench 33. Further, although not shown, the base electrode 27 </ b> B is also formed as a base pad electrode outside the trench 33. After each electrode is formed, each electrode is covered with an insulating film in order to protect the wiring portion.

  Further, after the above process is completed, the P-type semiconductor substrate 42 is etched so that the thickness becomes about 100 μm.

  In the above description, the active region is formed on the surface of the P-type semiconductor substrate 42. However, the active region can be formed on the surface of the non-doped semiconductor substrate. In this case, the surface of the non-doped semiconductor substrate is covered with a silicon oxide film, and an active region is formed in the semiconductor layer deposited on the silicon oxide film.

  Next, with reference to FIGS. 7 and 8, a process until the emitter pad electrode 23E and the back electrode 26 are connected using the through electrode 24A will be described.

  With reference to FIG. 7A, first, the back surface of the P-type semiconductor substrate 42 is covered with an etching resist 40. In the resist 40, a region corresponding to the lower part of the emitter pad electrode 23E is partially opened.

Referring to FIG. 7B, next, through-hole 24B having a thickness of about 70 μm and a length of about 150 μm is formed by dry etching the P-type semiconductor substrate 42 and the like using the resist 40 as a mask. . As an etching gas used in dry etching, a gas containing at least SF ₇ , O _2, or C ₄ F ₈ is used. By this step, the back surface of the emitter pad electrode 23E is exposed to the through hole 24B. The specific shape of the through hole 24B may be cylindrical or prismatic. Furthermore, the formation of the through holes 24B can also be performed using wet etching or laser.

  Here, if the through hole 24B is formed after the semiconductor substrate 42 is thinned by combining back grinding, plasma etching, or wet, the etching time can be shortened. For example, the semiconductor substrate 42 may be shaved from the back surface by back grinding, and irregularities formed by the grinding may be removed by plasma or wet. Further, the semiconductor substrate 42 may be removed from the back surface only by wet etching or plasma etching.

  Referring to FIG. 8A, next, a sidewall insulating film 41 is formed on the sidewall of the through hole 24B. As a material of the sidewall insulating film 41, a silicon oxide film, a silicon nitride film, or a resin film can be employed. By covering the side wall of the through hole 24B with the side wall insulating film 41, the conductive material filled in the through hole 24B and the P-type semiconductor substrate 42 can be insulated.

In the method of manufacturing the sidewall insulating film 41, first, the entire back surface of the P-type semiconductor substrate 42 including the inner wall of the through hole 24B is covered with an insulating film made of a SiO ₂ film or a SiN film. These insulating films are formed by plasma CVD, for example. Further, by removing this insulating film by anisotropic etching, the side wall insulating film 41 remains on the side wall of the through hole 24B, and the other part of the insulating film is removed. That is, the insulating film covering the back surface of the emitter pad electrode 23E and the back surface of the P-type semiconductor substrate 42 is removed. Further, when the back electrode to be formed and the P-type semiconductor substrate 42 are insulated, an oxide film may be left on the back surface of the P-type semiconductor substrate 42.

  Referring to FIG. 8B, next, a metal film is formed so as to cover the inner wall of through-hole 24B and the back surface of P-type semiconductor substrate. The metal film formed inside the through hole 24B becomes the through electrode 24A, and the metal film formed on the back surface of the P-type semiconductor substrate 42 becomes the back electrode 26. The through electrode 24A and the back electrode 26 can be formed by plating or sputtering. In the case of forming the back electrode 26 by plating, first, a seed layer (not shown) made of Cu having a thickness of about several hundred nm is formed on the entire inner wall of the through hole 24B and the back surface of the P-type semiconductor substrate 42. . Here, electroless plating is preferable. Next, by performing electroplating using the seed layer as an electrode, a metal film made of Cu having a thickness of about several μm is formed on the inner wall of the through hole 24B and the back surface of the P-type semiconductor substrate 42. As a result, the back electrode 26 electrically connected to the emitter pad electrode 23E through the through electrode 24A is formed.

  Here, the inside of the through hole 24B is completely buried with Cu formed by plating, but this filling may be incomplete. That is, a cavity may be provided inside the through electrode 24A. Further, the back electrode 26 can be formed by sputtering or the like other than plating.

  Furthermore, the through electrode 24A may be formed of a metal material other than the plating film. That is, the through electrode 24A can be formed by embedding a metal such as solder, W, Cu, or Al in the through hole 24B.

  After the above steps are completed, the semiconductor device 20A as shown in FIG. 3 is completed by dividing the P-type semiconductor substrate 42 and the layers above it by dicing. Further, through the steps of die bonding, wire bonding, and resin sealing, a circuit device 10A as shown in FIG. 1 is completed.

  In the above description, the through electrode 24A is formed only below the emitter pad electrode 23E. However, when the collector pad electrode 23C is also connected to the back electrode 26, the through electrode 24A is provided below the collector pad electrode 23C. It is done. In this case, the back electrode 26 is further patterned into a predetermined pattern.

  Furthermore, in the above description, the back electrode 26 is in direct contact with the back surface of the semiconductor substrate 41. However, the back surface of the semiconductor substrate 42 is covered with an insulating film, and the back electrode 26 is formed on the surface of the insulating film. May be.

<Third Embodiment>
In the present embodiment, a method for manufacturing the semiconductor device 20B whose structure is shown in FIG. 4C will be described with reference to FIG. The manufacturing method of this embodiment is basically the same as that of the second embodiment described above, and the difference is that a sidewall insulating film is not formed on the inner wall of the through hole 24B.

  Specifically, referring to FIG. 9A, first, an active region 21 made of, for example, a bipolar transistor is formed. Furthermore, the trench 33 is formed so as to surround the active region 21, thereby isolating the active region 21. In addition to the trench 33, the active region 21 may be separated using a PN junction isolation or a LOCOS oxide film. Further, an electrode connected to each region constituting the active region 21 is formed on the surface of the oxide film 32. Here, the emitter pad electrode 23 </ b> E and the collector pad electrode 23 </ b> C are formed outside the region surrounded by the trench 33 on the upper surface of the oxide film 32.

  Referring to FIG. 9B, next, a through hole 24B penetrating the P-type semiconductor substrate 42 and the like is formed. The back surface of the P-type semiconductor substrate 42 is covered with a resist 40, which is an etching resistant mask, except for a region where the through hole 24B is to be formed. In this state, the P-type semiconductor substrate 42 is dry-etched from the back surface, thereby forming a through hole 24B that penetrates the P-type semiconductor substrate 42, the epitaxial layer 31, and the oxide film 32. By this step, the back surface of the emitter pad electrode 23E is exposed in the through hole 24B.

  With reference to FIG. 9C, next, the through electrode 24 </ b> A is formed inside the through hole 24 </ b> B, and the back electrode 26 is formed on the back surface of the P-type semiconductor substrate 42. In this embodiment, since the inner wall of the through hole 24B is not covered with an insulating film, the conductive material such as copper constituting the through electrode 24A directly contacts the inner wall of the through hole 24B. In other words, the through electrode 24A is electrically connected to the P-type semiconductor substrate 42 and the epitaxial layer 31. However, as described above, the active region 21 is element-isolated by the trench 33, and the through electrode 24 </ b> A is located outside the trench 33. Therefore, even if the side surface of the through electrode 24A is not covered with an insulating film, the through electrode 24A and the active region 21 are not short-circuited.

  Through the above-described steps, the semiconductor device 20B whose structure is shown in FIG.

  According to this embodiment, since an insulating film made of a silicon oxide film or the like is not formed on the inner wall of the through hole 24B, the step of forming this insulating film can be omitted, and the yield can be improved.

  Specifically, when a silicon oxide film is formed on the inner wall of the through hole 24B, the oxide film is formed by a thermal oxidation method or a CVD method. However, in these methods for forming an oxide film, the P-type semiconductor substrate 42 is heated to about 1000 ° C., for example. Therefore, since the P-type semiconductor substrate 42 is exposed to an extremely high temperature, a thermal stress acts on the electrode formed on the surface of the substrate, causing a problem that the emitter pad electrode 23E and the like are separated from the oxide film 32. It was.

  In this embodiment, since an insulating film is not formed on the inner wall of the through hole 24B, the number of processes involving heating such as the thermal oxidation method described above can be reduced. Accordingly, deterioration of the emitter pad electrode 23E and the like due to thermal stress can be prevented, and the yield of the manufacturing process is improved. Furthermore, since the number of processes is reduced, the manufacturing cost can be reduced.

<Fourth embodiment>
In the present embodiment, with reference to FIG. 10 to FIG. 12, the configuration of another form of semiconductor device 20C and a circuit device having the same will be described. In the semiconductor device 20C described here, a plurality of pad electrodes formed on the surface of the semiconductor substrate 25 are connected to a back surface electrode formed on the back surface of the semiconductor substrate 42 through the through electrode 24A. In addition, a plurality of back surface electrodes are formed on the back surface of the semiconductor substrate 25.

  The configuration of the semiconductor device 20C will be described with reference to FIG. FIG. 10A is a perspective view of the semiconductor device 20C, and FIG. 10B is a plan view of the semiconductor device 20C viewed from the back surface.

  Referring to FIG. 10A, the basic configuration of the semiconductor device 20C is the same as that of the semiconductor device 20A shown in FIG. 3, except that each pad electrode formed on the surface of the semiconductor substrate 25 is a through electrode 24A. It is in the point connected with the electrode on the back side via.

  The collector pad electrode 23C, the base pad electrode 23B, and the emitter pad electrode 23E formed on the surface of the semiconductor substrate 25 are each connected to the back electrode formed on the back surface of the semiconductor substrate 25 through the through electrode 24A. . With such a configuration, the semiconductor substrate 25 can be mounted without the fine metal wires.

  Referring to FIG. 10B, a collector back electrode 26C, a base back electrode 26B, and an emitter back electrode 26E are formed on the back surface of the semiconductor substrate 25. The collector back electrode 26C is connected to the collector pad electrode 23C formed on the surface of the semiconductor substrate 25 via the through electrode 24A. The base back electrode 26B is connected to the base pad electrode 23B formed on the surface of the semiconductor substrate 25 through the through electrode 24A. The emitter back electrode 26E is connected to two emitter pad electrodes 23E formed on the surface of the semiconductor substrate 25 through the through electrode 24A.

  The collector back electrode 26C and the base back electrode 26B are arranged in the vicinity of the corners facing each other. Thus, the insulation between the collector back electrode 26C and the base back electrode 26B can be ensured by separating them.

  The emitter back electrode 26E continuously extends from one corner of the back surface of the semiconductor substrate 25 to the opposite corner. The emitter back electrode 26E is formed to have a larger area than the other back electrode. By forming the emitter back electrode 26E large, parasitic inductance can be reduced.

  When each back electrode and the semiconductor substrate 25 are insulated, an insulating layer made of an oxide film, a nitride film, or an insulating resin is disposed on the back surface of the semiconductor substrate 25, and each back electrode is placed on the top surface of the insulating layer. Deploy. When solder is attached to each back electrode, the back surface of the semiconductor substrate 25 may be covered with a solder resist and the back electrode may be partially exposed.

  The structure of the semiconductor device 20C will be further described with reference to FIG. 11A is a perspective view of the semiconductor device 20C, FIG. 11B is a cross-sectional view taken along line BB ′ of FIG. 11A, and FIG. 11C is FIG. It is sectional drawing in CC 'line | wire of ().

  Referring to FIG. 11B, base back electrode 26B and collector back electrode 26C are insulated from P-type semiconductor substrate 42 by insulating film 38. Here, the insulating film 38 is made of an insulating film such as a silicon oxide film, a silicon nitride film, or a resin film. The through electrode 24A connected to the base back electrode 26B and the collector back electrode 26C is insulated from the P-type semiconductor substrate 42 by the sidewall insulating film 41. With such a structure, the collector back electrode 26C and the base back electrode 26B are insulated from other parts of the semiconductor device 20C, and a short circuit between the electrodes is prevented.

  On the other hand, the insulating film 38 is not formed on the back surface of the P-type semiconductor substrate 42 in the region where the emitter back electrode 26E is formed. That is, the emitter back electrode 26E is in direct contact with the back surface of the P-type semiconductor substrate 42, and both are conductive. Therefore, when the emitter back electrode 26E is connected to the ground potential, the P-type semiconductor substrate 42 is also connected to the ground potential. Here, the emitter back electrode 26 </ b> E may also be insulated from the back surface of the P-type semiconductor substrate 42 by the insulating film 38. That is, all the back electrodes formed on the back surface of the semiconductor substrate 42 may be insulated from the semiconductor substrate 42 by the insulating film 38.

  Although the active region 21 is separated by the trench 33, it is necessary to insulate the electrodes (emitter electrode, collector electrode, and base electrode) from each other. Therefore, when an emitter electrode, a collector electrode, and a base electrode are provided, at least two electrodes need to be insulated using the insulating film 38 and the sidewall insulating film 41 as described above.

  Referring to FIG. 11C, the emitter back electrode 26E is connected to an emitter pad electrode 23E formed on the upper surface of the oxide film 32 via two through electrodes 24A. In the figure, the inner wall of the through hole 24A is covered with the sidewall insulating film 41, but the sidewall insulating film 41 can be omitted.

  Here, when the semiconductor device 20C is used with the collector grounded, the base back electrode 26B and the emitter back electrode 26E are insulated from the back surface of the semiconductor substrate 25 by the insulating film 38 or the like. In this case, the collector back electrode 26 </ b> C may be formed directly on the back surface of the semiconductor substrate 25.

  Furthermore, when the semiconductor device 20 </ b> C is used with the base grounded, the collector back electrode 26 </ b> C and the emitter back electrode 26 </ b> E are insulated from the back surface of the semiconductor substrate 25 by the insulating film 38. In this case, the base back electrode 26 </ b> B may be formed directly on the back surface of the semiconductor substrate 25.

  Next, the configuration of the circuit devices 10D and 10E in which the semiconductor device 20C described above is built will be described with reference to FIG.

  With reference to FIG. 12A, a configuration of a circuit device 10D including the circuit board 19 will be described. In the circuit device 10 </ b> D, conductive patterns 18 </ b> A and 18 </ b> B are formed on the surface of the circuit board 19. The emitter back electrode 26E located on the back surface of the semiconductor device 20C is connected to the conductive pattern 18A via solder or the like. Further, the base back electrode 26B located on the back surface of the semiconductor device 20C is connected to the conductive pattern 18B. Although not shown, the collector back electrode is also connected to a conductive pattern formed on the surface of the circuit board 19. Other configurations of the circuit device 10D are the same as those of the circuit device 10B illustrated in FIG. The circuit device 10D has a configuration in which the fine metal wires are omitted.

  Referring to FIG. 12B, in circuit device 10E, conductive patterns 18A and 18B embedded in sealing resin 14 are connected to electrodes formed on the back surface of semiconductor device 20C via solder. Specifically, the base back electrode 26B is connected to the conductive pattern 18A, and the emitter back electrode 26E is connected to the conductive pattern 18B. Other configurations of the circuit device 10E are the same as those of the circuit device 10C illustrated in FIG.

1A and 1B are diagrams illustrating a semiconductor device of the present invention, in which FIG. 1A is a perspective view, and FIG. 1A is a cross-sectional view of a semiconductor device according to the present invention, and FIG. 1A and 1B are diagrams illustrating a semiconductor device of the present invention, in which FIG. 1A is a perspective view, and FIG. BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the semiconductor device of this invention, (A) is sectional drawing, (B) is a top view, (C) is sectional drawing. (A) is an equivalent circuit diagram of the semiconductor device of the present invention, and (B) is a graph showing a simulation result. It is a figure which shows the manufacturing method of the semiconductor device of this invention, and (A)-(D) is sectional drawing. It is a figure which shows the manufacturing method of the semiconductor device of this invention, (A) and (B) are sectional drawings. It is a figure which shows the manufacturing method of the semiconductor device of this invention, (A) and (B) are sectional drawings. It is a figure which shows the manufacturing method of the semiconductor device of this invention, and (A)-(C) is sectional drawing. 1A and 1B are diagrams illustrating a semiconductor device of the present invention, in which FIG. 1A is a perspective view, and FIG. 1A is a perspective view, FIG. 1B is a cross-sectional view, and FIG. 1C is a cross-sectional view. BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the semiconductor device of this invention, (A) And (B) is sectional drawing. It is a perspective view which shows the conventional circuit device.

Explanation of symbols

10A to 10E Circuit device 11A to 11D Lead 12 Land 14 Sealing resin 15 Fixing material 16 Substrate 20A, 20B, 20C Semiconductor device 21 Active region 22 Rewiring 23 Pad electrode 23E Emitter pad electrode 23C Collector pad electrode 23B Base pad electrode 24A Through Electrode 24B Through-hole 25 Semiconductor substrate 26 Back electrode 27E Emitter electrode 27C Collector electrode 27B Base electrode 28 Silicon semiconductor substrate 29 Receiving oxide film layer 30 N ⁺⁺ type epitaxial layer 31 N ^- type epitaxial layer 32 Oxide film 33 Trench 34 Base region 35 Emitter region 37 Collector region 38 Insulating film

Claims (15)

A plurality of pad electrodes formed on the surface of the semiconductor substrate and electrically connected to the active region;
A back electrode provided on the back surface of the semiconductor substrate;
Penetrating the semiconductor substrate in the thickness direction, comprising a through electrode connecting the pad electrode and the back electrode,
A semiconductor device, wherein at least one pad electrode connected to a ground potential is connected to the back electrode through the through electrode.   The semiconductor device according to claim 1, wherein the plurality of pad electrodes are connected to the back electrode through the through electrode. A bipolar transistor is formed in the active region,
2. The semiconductor device according to claim 1, wherein the pad electrode connected to the emitter region of the bipolar transistor is connected to the back electrode through the through electrode. A MOSFET is formed in the active region,
2. The semiconductor device according to claim 1, wherein the pad electrode connected to the source region of the MOSFET is connected to the back electrode through the through electrode. The back electrode of the semiconductor substrate is fixed to a land-like conductive member,
2. The semiconductor device according to claim 1, wherein the pad electrode connected to a ground potential is connected to the conductive member via the through electrode and the back electrode. Other pad electrodes not connected to ground potential
6. The semiconductor device according to claim 5, wherein the semiconductor device is electrically connected to another conductive member through a thin metal wire. The back electrode is in direct contact with the back surface of the semiconductor substrate;
The semiconductor device according to claim 1, wherein the through electrode and the semiconductor substrate have the same potential. A plurality of back electrodes are formed on the back surface of the semiconductor substrate,
The semiconductor device according to claim 1, wherein each of the back electrodes is electrically connected to the pad through the through electrode.   The semiconductor device according to claim 8, wherein the back electrode is insulated from the semiconductor substrate through an insulating film covering the back surface of the semiconductor substrate.   The semiconductor device according to claim 1, wherein all of the pad electrodes connected to the active region are connected to the back electrode through the through electrode. The active region is formed inside a region surrounded by the isolation region,
The through electrode is formed in a through hole penetrating the semiconductor substrate outside the separation region,
The semiconductor device according to claim 1, wherein the through electrode is in contact with an inner wall of the through hole. A semiconductor substrate having a semiconductor layer on which active elements are formed;
A first electrode electrically connected to one diffusion region of the active element;
A pad electrode provided integrally with the first electrode and extending around the semiconductor substrate;
A through electrode provided under the pad electrode and extending from the semiconductor layer surface to the back surface of the semiconductor substrate;
A semiconductor device comprising a back electrode electrically connected to the through electrode and provided on the back surface of the semiconductor substrate.   The active element is a BIP-type or MOS-type transistor, and the first electrode electrically connected to a grounded diffusion region is electrically connected to at least two through electrodes. The semiconductor device according to claim 12. Forming an active region on the surface of the semiconductor substrate;
Forming a pad electrically connected to the active region on the surface of the semiconductor substrate;
Forming a through-hole penetrating the semiconductor substrate located below the pad;
Forming a back surface electrode electrically connected to the pad through a through electrode formed inside the through hole on the back surface of the semiconductor substrate;
Forming the through hole outside a separation region formed so as to surround the active region;
A method of manufacturing a semiconductor device, wherein the through electrode is formed so as to be in direct contact with an inner wall of the through hole.   15. The method of manufacturing a semiconductor device according to claim 14, wherein the isolation region has a trench structure, a LOCOS oxide film, or a PN junction isolation structure.