CN118553621A - Method for manufacturing package substrate - Google Patents

Abstract

The invention discloses a method for manufacturing a packaging substrate, which comprises the steps of firstly manufacturing an asymmetric substrate structure on two opposite surfaces of a bearing piece at the same time, and after the bearing piece is removed, manufacturing circuit layers on two opposite sides of the asymmetric substrate structure at the same time.

Description

Method for manufacturing packaging substrate

Technical Field

The present invention relates to a method for manufacturing a substrate, and in particular to a method for manufacturing an asymmetric packaging substrate.

Background Art

With the development of industrial applications, in recent years, it has gradually developed towards 5G high-frequency communications, augmented reality (AR), virtual reality (VR), etc. Therefore, it is more necessary to develop high-end semiconductor packaging technology to be applied to semiconductor flip-chip packaging or multi-chip packaging such as artificial intelligence chips (AI chips), high-end chips, and multi-chips. Under this packaging requirement, the package size is bound to become larger and larger, and the number of stacking layers is also getting higher and higher, resulting in the circuit design being designed towards high density, fine line spacing, and high electrical connection points to meet the packaging requirements of the above-mentioned chips.

Fig. 1 is a cross-sectional view of an existing package substrate 1. As shown in Fig. 1, the package substrate 1 includes a core board 10 having a first side 10a and a second side 10b opposite to each other, and a first circuit structure 11 is formed on the first side 10a of the core board 10, and a second circuit structure 12 is formed on the second side 10b of the core board 10, wherein the core board 10 has a plurality of conductive through holes 100 connecting the first side 10a and the second side 10b to electrically connect the first circuit structure 11 and the second circuit structure 12, and the number of wiring layers of the first circuit structure 11 and the number of wiring layers of the second circuit structure 12 are different.

However, in the manufacturing process of the existing packaging substrate 1, the first circuit structure 11 is first manufactured on the first side 10a of the core board 10, and then the second circuit structure 12 is manufactured on the second side 10b. Therefore, when manufacturing the second circuit structure 12, it is easy to cause uneven stress distribution due to the different number of wiring layers of the first circuit structure 11 and the second circuit structure 12, resulting in warping of the packaging substrate 1, thereby causing poor production yield of the packaging substrate 1.

Therefore, how to overcome the problems of the above-mentioned existing manufacturing methods has become a topic that needs to be solved urgently.

Summary of the invention

In view of the various deficiencies of the above-mentioned prior art, the present invention provides a method for manufacturing a packaging substrate, comprising: providing a carrier having a first surface and a second surface relative to each other; forming an insulating layer and a core board body in sequence on the first surface and the second surface of the carrier so that each of the insulating layers is combined with the carrier, wherein the core board body has a first side and a second side relative to each other so that each of the core boards is combined with the insulating layer with its first side, and each of the core boards has a plurality of conductive through holes connecting the first side and the second side; forming a second circuit structure on the second side of each of the core boards; removing the carrier to obtain an asymmetric substrate structure; and forming a first circuit structure on the insulating layer, wherein the number of wiring layers of the first circuit structure is different from the number of wiring layers of the second circuit structure.

The aforementioned manufacturing method further includes forming another circuit layer of the second circuit structure while forming the first circuit structure on the insulating layer.

In the aforementioned manufacturing method, the carrier comprises copper foil or prepreg.

In the aforementioned manufacturing method, the core board also has a plurality of inner circuit layers electrically connected to the conductive through holes.

In the aforementioned manufacturing method, the first circuit structure includes the insulating layer and the first circuit layer combined with the insulating layer.

In the above-mentioned manufacturing method, the first circuit structure includes the insulating layer, at least one first dielectric layer disposed on the insulating layer, and a first circuit layer combining the insulating layer and the first dielectric layer. For example, the first dielectric layer is formed on the first side of the core board by lamination.

In the above-mentioned manufacturing method, the second circuit structure includes at least one second dielectric layer and a second circuit layer combined with the second dielectric layer. For example, the second dielectric layer is formed on the second side of the core board by lamination.

In the aforementioned manufacturing method, the insulating layer and the core board are formed on the carrier by pressing.

As can be seen from the above, in the method for manufacturing the package substrate of the present invention, the second circuit structure is mainly manufactured on the first and second surfaces of the carrier at the same time. Therefore, compared with the prior art, the present invention can avoid warping when manufacturing the second circuit structure.

Furthermore, in the method for manufacturing the packaging substrate of the present invention, after removing the carrier, even if the number of wiring layers on the upper and lower sides of the asymmetric substrate structure is not equal (or the structural thicknesses on the upper and lower sides are inconsistent), warping can be avoided because the first circuit structure (such as the first circuit layer) and another circuit layer of the second circuit structure (such as the second circuit layer) are simultaneously manufactured on the first side and the second side of the core board.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a conventional packaging substrate.

2A to 2F are cross-sectional views of a method for manufacturing a packaging substrate according to the present invention.

FIG. 2A-1 is a cross-sectional schematic diagram of another embodiment of the carrier of FIG. 2A .

3 and 4 are cross-sectional views of other different embodiments of the method for manufacturing a package substrate of the present invention.

The reference numerals are described as follows:

1, 2: Package substrate

10, 20: core board

10a, 20a: First side

10b, 20b: Second side

100, 200: Conductive vias

11, 21: First line structure

12, 22: Second line structure

2a: Asymmetric substrate structure

201: Plug material

21b: First conductive blind hole

210: First inner circuit layer

211: Insulation layer

212, 214, 216: First circuit layer

213, 215: first dielectric layer

22a: Metal layer

22b: Second conductive blind hole

220: Second inner circuit layer

221, 223, 225, 227, 229: Second dielectric layer

222, 224, 226, 228, 320: Second circuit layer

410, 420: Inner circuit layer

9: Bearing parts

9a: First surface

9b: Second surface

90, 90a, 90b: copper foil

91: Board body.

DETAILED DESCRIPTION

The following describes the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of people familiar with this technology, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "first", "second", "one", etc. cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

2A to 2F are cross-sectional views of a method for manufacturing a package substrate 2 according to the present invention.

As shown in FIG. 2A , a carrier 9 , a plurality of core boards 20 , a plurality of insulating layers 211 and a plurality of second dielectric layers 221 having metal layers 22 a are provided, wherein the carrier 9 has a first surface 9 a and a second surface 9 b opposite to each other.

In this embodiment, the carrier 9 is a temporary carrier, and its plate body 91 can be an organic polymer plate such as bismaleimide triazine (BT) or a copper foil substrate. For example, the carrier 9 is a copper foil substrate, which includes a copper foil 90, and a peeling layer (not shown) can be provided on the copper foil 90 as required. It should be understood that there are many types of temporary carriers, such as metal plates such as aluminum, copper or stainless steel, plates composed of prepreg with a metal surface, substrates with embedded double copper foils 90a, 90b as shown in FIG. 2A-1, or other types, which can be selected according to cost requirements without special restrictions.

Furthermore, the core board 20 is a single core layer specification, which has a first side 20a and a second side 20b opposite to each other, and a first inner circuit layer 210 and a second inner circuit layer 220 are arranged on the first side 20a and the second side 20b of the core board 20, and the core board 20 has a plurality of conductive through holes 200 connecting the first side 20a and the second side 20b to electrically connect the first inner circuit layer 210 and the second inner circuit layer 220.

In addition, the conductive via 200 is a hollow column, and the hollow part thereof can be filled with a plugging material 201, wherein the plugging material 201 can be of various types, such as conductive glue, ink, etc., and is not particularly limited. It should be understood that in other embodiments, the conductive via 200 can also be a solid metal column without being filled with the plugging material 201.

In addition, the insulating layer 211 is a dielectric layer, such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

As shown in Figure 2B, the core board 20, the insulating layer 211 and the second dielectric layer 221 are symmetrically formed on the first surface 9a and the second surface 9b of the carrier 9 by pressing, so that the core board 20 is combined with the insulating layer 211 with its first side 20a and combined with the second dielectric layer 221 with its second side 20b, and the metal layer 22a is located at the outermost side.

As shown in FIG. 2C , the metal layer 22 a is patterned to form a second circuit layer 222 , and a plurality of second conductive blind vias 22 b electrically connecting the second inner circuit layer 220 and the second circuit layer 222 are formed in the second dielectric layer 221 .

In this embodiment, the second circuit layer 222 and the second dielectric layer 221 can be used as the second circuit structure 22 , so that a second circuit structure 22 is formed on the second side 20 b of each core board 20 .

As shown in FIG. 2D , the number of wiring layers of the second circuit structure 22 can be designed according to demand, so a second dielectric layer 223 having a metal layer can be laminated on the second circuit layer 222 and the second dielectric layer 221 to manufacture a second circuit layer 224 and form an asymmetric substrate structure 2a.

In this embodiment, in order to protect the second circuit layer 224 , a second dielectric layer 225 having a metal layer 22 a is laminated on the second circuit layer 224 , so that the metal layer 22 a is presented on the outer side of the second circuit structure 22 .

As shown in FIG. 2E , the carrier 9 is removed by peeling off the layer to obtain an asymmetric substrate structure 2 a .

In this embodiment, the asymmetric substrate structure 2a has the copper foil 90 for subsequent production of the circuit layer. It should be understood that since there are many ways to produce the circuit layer, in other embodiments, when removing the carrier 9, the copper foil 90 can also be removed without affecting the subsequent production of the circuit layer.

As shown in FIG. 2F , the copper foil 90 is patterned on the insulating layer 211 to form a first circuit layer 212 with the copper foil 90, and a plurality of first conductive blind vias 21b electrically connecting the first inner circuit layer 210 and the first circuit layer 212 are formed in the insulating layer 211 to form a first circuit structure 21. The metal layer 22a can be patterned as required to form a second circuit layer 226 of the second circuit structure 22, thereby obtaining a packaging substrate 2 with an asymmetric wiring configuration, wherein the number of wiring layers of the first circuit structure 21 is different from the number of wiring layers of the second circuit structure 22.

In this embodiment, the first circuit structure 21 includes the insulating layer 211 and the first circuit layer 212 combined with the insulating layer 211, and the second circuit structure 22 includes multiple second dielectric layers 221, 223, 225, and second circuit layers 222, 224, 226 combined with the second dielectric layers 221, 223, 225. Therefore, the number of wiring layers of the second circuit structure 22 is three, which is one more than the number of wiring layers of the first circuit structure 21.

Furthermore, the first circuit structure 21 can form the required number of wiring layers on the first side 20a of the core board 20 by pressing, such as the multiple first dielectric layers 213, 215 and three first circuit layers 212, 214, 216 shown in Figure 3; similarly, the second circuit structure 22 can form the required number of wiring layers on the second side 20b of the core board 20 by pressing, such as the five second circuit layers 222, 224, 226, 228, 320 shown in Figure 3, and additional second dielectric layers 227, 229.

In addition, a plurality of inner circuit layers 410 , 420 electrically connected to the conductive vias 200 may be disposed in the core board 20 as required, as shown in FIG. 4 .

In addition, the materials of the dielectric layers of the first circuit structure 21 and the second circuit structure 22 include inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride or other suitable materials), organic materials (such as polyimide (PI), polybenzazole (PBO), prepreg (PP), epoxy resin (Epoxy), benzocyclobutene (BCB) or other suitable materials), and the materials of the circuit layers of the first circuit structure 21 and the second circuit structure 22 are copper or other metals.

Therefore, the manufacturing method of the present invention mainly manufactures the circuit structure on the first surface 9a and the second surface 9b of the carrier 9 at the same time, so that after removing the carrier 9, the asymmetric substrate structure 2a can be obtained, and then the packaging substrate 2 can be further manufactured. Therefore, compared with the prior art, the present invention can prevent the packaging substrate 2 from warping when manufacturing the second circuit structure 22 by using the carrier 9, and after removing the carrier 9, even if the number of wiring layers on the upper and lower sides of the asymmetric substrate structure 2a is not equal (or the structural thickness is inconsistent), warping can still be avoided because the first circuit layer 212, 214, 216 and the second circuit layer 226, 228, 320 are manufactured on the first side 20a and the second side 20b of the core board 20 at the same time.

In summary, the method for manufacturing the packaging substrate of the present invention uses the carrier to simultaneously manufacture an asymmetric substrate structure on two opposite sides thereof, and after removing the carrier, simultaneously manufactures the circuit layer on two opposite sides of the asymmetric substrate structure. Therefore, the method for manufacturing the packaging substrate of the present invention can avoid the situation of wiring on one side to avoid the problem of warping, thereby maintaining structural reliability and effectively improving product yield.

The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Anyone skilled in the art can modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims (10)

1. A method of fabricating a package substrate, comprising:

providing a carrier having opposite first and second surfaces;

Sequentially forming an insulating layer and a core plate body on the first surface and the second surface of the bearing piece so as to enable each insulating layer to be combined on the bearing piece, wherein each core plate body is provided with a first side and a second side which are opposite to each other, each core plate body is combined with the insulating layer by the first side, and the core plate body is provided with a plurality of conductive through holes which are communicated with the first side and the second side;

Forming a second circuit structure on the second side of each core board body;

Removing the bearing piece to obtain an asymmetric substrate structure; and

And forming a first circuit structure on the insulating layer, wherein the wiring layer number of the first circuit structure is different from the wiring layer number of the second circuit structure.

2. The method of claim 1, further comprising forming another circuit layer of the second circuit structure simultaneously with the first circuit structure on the insulating layer.

3. The method of claim 1, wherein the carrier comprises copper foil or prepreg.

4. The method of claim 1, wherein the core board further comprises a plurality of inner circuit layers electrically connected to the conductive vias.

5. The method of claim 1, wherein the first circuit structure comprises the insulating layer and a first circuit layer combined with the insulating layer.

6. The method of claim 1, wherein the first circuit structure comprises the insulating layer, at least one first dielectric layer disposed on the insulating layer, and a first circuit layer connecting the insulating layer and the first dielectric layer.

7. The method of claim 6, wherein the first dielectric layer is formed on the first side of the core board body by lamination.

8. The method of claim 1, wherein the second circuit structure comprises at least one second dielectric layer and a second circuit layer combined with the second dielectric layer.

9. The method of claim 8, wherein the second dielectric layer is formed on the second side of the core board body by lamination.

10. The method of claim 1, wherein the insulating layer and the core plate are formed on the carrier by pressing.