JP2017228692A - Semiconductor package substrate and manufacturing method thereof - Google Patents

Abstract

[PROBLEMS] To reduce warping and to have high connection reliability with a semiconductor element and a printed wiring board even when the semiconductor chip is mounted on an asymmetrical structure having a larger number of built-up layers than on the other side. In addition, a semiconductor package that can be efficiently manufactured and a manufacturing method thereof are provided.
A semiconductor package substrate having a first main surface and a second main surface, the core substrate being provided on a first main surface side and a second main surface side of the core substrate, a wiring layer and an insulating resin layer And the number of wiring layers formed on the first main surface side is greater than the number of wiring layers formed on the second main surface side, and the wiring on the first main surface side The thickness of the layer is thinner than the thickness of the wiring layer on the second main surface, and the via diameter for conducting between the layers of the circuit wiring layer formed on the first main surface side is formed on the second main surface side. A semiconductor package substrate having a smaller total diameter than the via diameter and equal in total thickness of the insulating resin layer formed on the first main surface side and the total thickness of the insulating resin layer formed on the second main surface side.
[Selection] Figure 2 (h)

Description

  The present invention relates to a semiconductor package substrate for mounting a semiconductor chip and a manufacturing method thereof, and more particularly to miniaturization of a circuit of the semiconductor package substrate, improvement of dimensional stability, improvement of connection reliability, and cost reduction.

  In order to meet the recent demand for downsizing and higher functionality of electronic devices, a stacked multichip package in which a plurality of semiconductor chips are stacked in a semiconductor device has been developed. A stacked multichip package is suitable for miniaturization and high integration because a plurality of semiconductor chips are stacked to form a single package, and is mainly commercialized for memory products such as DRAM. However, in the conventional multi-chip package, each chip to be stacked and the package substrate are connected by wire bonding, so that the number of terminals that can be drawn from each chip is small. It is difficult to secure the wire bonding pads, and it is difficult to stack a large number of chips.

  On the other hand, recently, a chip stacking technique using a through silicon via (TSV; Through Silicon Via) as shown in FIG. 1A has been developed. TSV is a through electrode provided on a silicon substrate, and electrical connection between stacked chips and between a chip and a package substrate can be performed using TSV. FIG. 1A shows an example of a stacked multichip package (also called a 3D package) in which a logic chip and a memory chip are three-dimensionally stacked by TSV. Reference numeral 101 denotes a memory chip. Here, a case where four memory chips 101 are stacked is shown. Reference numeral 105 denotes a logic chip for the memory controller. The memory chips 101 and the logic chip 105 and the package substrate 104 are electrically connected via the TSVs 102 and are connected by the bumps 103. The bump 103 is made of a metal such as solder or copper. With such chip stacking technology using TSV, it is possible to easily increase the number of chips to be stacked since wires that have been used conventionally are no longer necessary, and the connection distance between chips and between the chip and the package substrate can be increased. It is shortened and is advantageous for high-speed signal transmission. Furthermore, while conventional wire bonding wires have a diameter of 20-30 μm, TSVs can be formed with a diameter of 10 μm or less, so that more terminals can be drawn out and high capacity communication is possible. There are many advantages such as being possible.

  However, many processes are required for manufacturing a semiconductor chip with TSV, and therefore, it takes time and cost to manufacture. Further, in the case of the 3D package shown in FIG. 1A in which the TSV is formed on the logic chip, the memory chip and the logic chip are connected with the TSV having the same pitch. Therefore, the TSV bump pitch between the manufacturers of the logic chip and the memory chip. It is necessary to establish a unified standard. In this case, the design restriction of the logic IC occurs, and there is a problem that the design cost is high. Further, in the case of a 3D package, chips manufactured by a logic chip manufacturer and a memory chip manufacturer must be joined by an assembly manufacturer and then mounted on a semiconductor package substrate. If a failure occurs after assembling the semiconductor package, there are many problems such as quality assurance and manufacturing responsibility that it is not possible to clarify whether it is a failure at the assembly manufacturer or a manufacturing failure of any chip manufacturer. It has become.

  From the above, the multi-chip package (FIG. 1 (b)) in which the three-dimensional chip of the DRAM memory and the logic chip that are relatively easy to stack with the TSV are mounted on the semiconductor package substrate is most realistic. It is considered (so-called 2.5D package). In the 3D package, the signal wiring between the memory and the logic is connected by a minute TSV. However, in the case of the 2.5D package, the signal line connection between a plurality of semiconductor chips needs to be planarly connected on the semiconductor package substrate. It becomes. Therefore, since the number of wirings is inevitably remarkably required on the semiconductor package substrate side, the demand for finer and multi-layered becomes more severe. Therefore, the 2.5D package is mounted on a silicon interposer (106 in FIG. 1B) manufactured by a semiconductor process that can finely connect the three-dimensional stacked memory and the logic chip. A method for mounting a silicon interposer on which a semiconductor chip is mounted on a semiconductor package substrate 104 has been proposed.

JP 2009-295924 A

  However, in the 2.5D package shown in FIG. 1B, since the silicon interposer 106 is further interposed between the semiconductor package substrate 104 and the semiconductor chip, the efficiency is low and it is difficult to reduce the height. The problem of becoming. Since the silicon interposer is manufactured by a wafer process, there is a problem that the cost is significantly higher than the price of a semiconductor package substrate manufactured with a panel size larger than the wafer. Since silicon is a semiconductor, in order to form circuit wiring, it is necessary to form an oxide film once to insulate, and then to form circuit wiring thereon. Therefore, there is a problem that the transmission characteristic of the circuit wiring formed on the silicon interposer is worse than that of a glass fiber reinforced resin substrate which is an insulator or a circuit formed on the glass substrate. Therefore, a semiconductor package substrate other than silicon, that is, a semiconductor package substrate (so-called organic interposer) 107 having a glass interposer or glass fiber reinforced resin substrate as a core as shown in FIG. 1C is more efficient and inexpensive. It is said that this is a desirable form, and research and development of glass interposers and organic interposers have been activated as alternative technologies for silicon interposers.

  Here, a main manufacturing method of the semiconductor package substrate will be briefly described with an example of an organic interposer. The semiconductor package substrate is manufactured by a built-up method. First, a multilayer wiring board which is a core substrate on which two or more layers of circuit wiring are formed is prepared by using a known printed wiring board manufacturing method. An interlayer insulating resin is laminated on the front and back surfaces of the wiring board by a vacuum press and thermally cured. Subsequently, via holes for conducting an interlayer circuit are formed on the front and back surfaces using a laser processing machine. After removing the laser smear by treating with a hot alkaline permanganate solution, electroless plating is performed to make the resin surface conductive. Further, a resist layer is formed on the front and back of the substrate, and a circuit pattern is formed using the resist by photolithography. Thereafter, by using the electroless plating layer as a seed layer and performing electrolytic copper plating, vias that are vertical holes for wiring and interlayer conduction are simultaneously formed using a resist pattern as a mold. A circuit wiring is formed by removing the resist and etching away unnecessary electroless plating layers. The built-up multilayer wiring layer is formed by repeating the etching removal of the electroless plating layer from the laminate of the interlayer insulating resin a plurality of times.

  As a technical problem of creating a 2.5D semiconductor package substrate, wiring of a built-up layer formed on a core substrate on which a plurality of semiconductor chips on the semiconductor package substrate are mounted (referred to as a first main surface) It is necessary to form the layer in a fine and multi-layered manner. The reason is that, in the case of a 2.5D semiconductor package substrate, the number of semiconductor chips to be mounted increases, so that the number of signal lines for electrically connecting semiconductor elements to each other as compared with the conventional package substrate as described above. This is because the number is significantly increased. Specifically, the line and space (L / S) = 10/10 μm is the limit in the conventional semiconductor package substrate, but the fine multilayer wiring of L / S = 5/5 μm or less in the 2.5D semiconductor package substrate There is an increasing need to form layers. On the other hand, the wiring density of the built-up layer on the BGA side (second main surface) that is the connection terminal between the semiconductor package substrate and the mother board is not necessarily high, but the wiring density of the conventional semiconductor package substrate Can be handled by the manufacturing method. From the above, when manufacturing a 2.5D semiconductor package substrate, the first main surface side compared to the second main surface build-up layer that can be handled by a conventional semiconductor package substrate manufacturing method of LS = 10 μm or more It is necessary to form a wiring density of the built-up layer of L / S = 5 or less and to form a multilayer than the second main surface.

  However, there is a problem of warping of the package substrate as a problem in that the build-up resin having the same layer thickness is formed in a multilayer and denser than the opposite side surface to form an asymmetric laminate layer structure with the core substrate as the center. Built-up resin, which is a thermosetting resin, is thermoset after laminating, but when insulating resin with the same thickness is laminated with asymmetrical number of layers, the larger the number of laminate layers, the residual stress due to curing shrinkage Is accumulated in the resin layer. As a result, when a side having a larger number of laminate layers is arranged on the upper surface and a side having a smaller number of laminate layers is arranged on the lower surface, a downward curved curved warp is generated. The warpage in the semiconductor package substrate is a major factor causing poor connection with the semiconductor chip. In particular, in the case of a 2.5D semiconductor package substrate, since the terminal pitch with the semiconductor chip is required to be extremely narrow, the warpage problem is a major problem that determines the yield at the time of mounting. There is a need.

  Furthermore, there is a manufacturing problem as a problem of taking the number of laminate layers asymmetrical with the core substrate as the center. For example, when one layer is laminated on either the front or back side, a built-up resin layer is inevitably laminated on one side of the circuit board formed on the front and back sides, and the circuit pattern is exposed without laminating the opposite side. Leave it in the state. The laminated single-sided resin forms a via in a laser process and then enters a process of removing laser smear with a hot alkaline permanganate. In this case, the exposed single-sided circuit side on the non-resin laminated side is exposed to the permanganic acid solution, so that the resin is damaged. Damage to the resin causes deterioration of the adhesion of the formed circuit and resin deterioration, and causes deterioration in yield and electrical reliability. Although there is a method of providing a protective film on a single-sided circuit, it is necessary to select a film having heat alkaline permanganate resistance and to prepare a protective film that can be peeled without damaging the formed circuit. Therefore, in order to realize an asymmetric structure, a method for protecting a circuit on one side using a protective film is not practical in terms of cost and process. Due to the above-described warpage and process reasons, there is a demand for a package substrate structure and a method for manufacturing the same that can manufacture a substrate having a multilayer wiring on one side while avoiding the problem of warpage and with good yield and low cost.

  In recent years, the required characteristics of semiconductor package substrates are required not only for miniaturization but also for high connection reliability. A major factor of connection reliability is a difference in thermal expansion coefficient between the semiconductor package substrate and the semiconductor chip. The thermal expansion coefficient of the semiconductor package needs to be able to maintain a good connection within the product life even in the thermal history (up to 260 ° C.) in the assembly and mounting process or in the operating thermal cycle of the semiconductor device after packaging. Therefore, the material design is such that the thermal expansion coefficient of the semiconductor package substrate approaches 3 ppm of the semiconductor chip. In particular, in recent years, it has been desired that the thermal expansion coefficient of the semiconductor package substrate can be adjusted within 3 to 15 ppm with the narrowing of the connection terminals of the semiconductor chip. On the other hand, in the connection between the semiconductor package substrate and the printed wiring board (BGA side), the thermal expansion coefficient of the printed wiring board is 20 ppm or more and is still large. When the thermal expansion coefficient of the semiconductor package substrate is close to that of silicon to ensure connection reliability with the semiconductor chip (primary mounting reliability), on the other hand, connection reliability with the printed wiring board (secondary mounting reliability) There is a problem that it is difficult to maintain the property. Also in this respect, it is desirable from the viewpoint of connection reliability that the circuit wiring on the BGA side of the semiconductor package and the via hole are L / S = 10 or more which is the wiring rule of the semiconductor package substrate so far. Also from the above viewpoint, the circuit on the first main surface on which the semiconductor chip is mounted is a fine multilayer circuit, and the BGA side circuit on the second main surface is preferably rough according to the conventional wiring rule from the viewpoint of reliability of secondary mounting. .

  Further, the connection between the BGA side circuit and the printed wiring board is made by forming a solder bump as a connection terminal by a screen printing method. In the screen printing method, the openings of the screen plate are aligned and placed on the external connection terminals on the surface layer of the semiconductor package substrate, the solder paste is printed with a squeegee, and the solder paste is melted by thermal reflow to solder bumps. Form. In solder paste printing, the solder of each bump is considered due to variations in the amount of solder paste supplied into the mask opening and variations in the ratio between the amount of paste remaining on the mask side and the amount of paste remaining on the substrate side when the mask is pulled away. The volume variation of the paste is large, which leads to the variation of the bump height, and there is concern about the reliability of connection with the printed wiring board.

  The present invention has been made to solve the above-described problems, and an object of the present invention is a semiconductor package substrate that is built up on both sides with a core substrate as a center, on which a semiconductor chip is mounted. Even if it has an asymmetric structure where the number of built-up layers on the side is greater than that on the other side, the semiconductor package can be efficiently manufactured with low warpage and high connection reliability with semiconductor elements and printed wiring boards It is to provide a substrate and a manufacturing method thereof.

  The present invention relates to a semiconductor package substrate having a first main surface on which a semiconductor chip is mounted and a second main surface on which external connection terminals for electrical connection with a printed wiring board are formed, A layer of a wiring layer provided on the first main surface side, including a core substrate, and a circuit wiring layer provided on the first main surface side and the second main surface side of the core substrate and including a wiring layer and an insulating resin layer The number of wiring layers is larger than the number of wiring layers formed on the second main surface side, and the thickness of the wiring layer on the first main surface side is thinner than the thickness of the wiring layer on the second main surface, The via diameter for conducting between the layers of the circuit wiring layer formed on the side is smaller than the via diameter formed on the second main surface side, and the total thickness of the insulating resin layer formed on the first main surface side The total thickness of the insulating resin layer formed on the second main surface side is equal, and the first main surface side protrudes from the outermost surface of the first main surface. It is characterized in that the Okoshijo electrode is provided.

  The core substrate is preferably a glass substrate or a glass fiber reinforced resin substrate on which at least two circuit wiring layers are formed.

  The thickness of the metal layer provided on the outermost layer of the first main surface and the second main surface is preferably thicker than the thickness of the metal layer provided on the inner layer of the first main surface and the second main surface.

  The present invention also relates to a method of manufacturing a semiconductor package substrate having a first main surface on which a semiconductor chip is mounted and a second main surface on which external connection terminals for electrical connection with a printed wiring board are formed. A first step of laminating insulating resin layers having the same thickness on both surfaces of the core substrate, and a second step of forming vias and wiring layers only on the first main surface side of the core substrate. Repeating the third step and the second step and the third step a plurality of times to laminate the insulating resin layer of the same thickness on the outermost surfaces of the first main surface side and the second main surface side so as to cover the via and the wiring layer A fourth step of forming a circuit wiring layer composed of a wiring layer and an insulating resin layer on the first main surface side of the core substrate; a via and a connection electrode on the first main surface side; and a second main surface side And a fifth step of forming a via and a wiring layer.

  According to the present invention, a semiconductor package substrate is built-up on both sides with a core substrate as a center, and the asymmetric wiring in which the number of built-up layers on one side surface on which a semiconductor chip is mounted is larger than that on the other surface side. Even if it has a layered structure, it is possible to provide a semiconductor package substrate and a method for manufacturing the same that have less warping, have high connection reliability with a semiconductor element and a printed wiring board, and can be efficiently manufactured.

4A and 4B are schematic diagrams of a stacked multi-chip package, where FIG. 5A shows a 3D package, FIG. 5B shows a 2.5D package through a silicon interposer, and FIG. 5C shows a 2.5D package without a silicon interposer. The schematic diagram which shows the manufacturing process of the semiconductor package board | substrate in this invention The schematic diagram which shows the manufacturing process of the semiconductor package board | substrate in this invention The schematic diagram which shows the manufacturing process of the semiconductor package board | substrate in this invention The schematic diagram which shows the manufacturing process of the semiconductor package board | substrate in this invention The schematic diagram which shows the manufacturing process of the semiconductor package board | substrate in this invention The schematic diagram which shows the manufacturing process of the semiconductor package board | substrate in this invention The schematic diagram which shows the manufacturing process of the semiconductor package board | substrate in this invention The schematic diagram which shows the manufacturing process of the semiconductor package board | substrate in this invention The schematic diagram which shows the manufacturing process of the semiconductor package board | substrate in this invention

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 (a) to 2 (i). In the present embodiment, the build-up layer on the first main surface side on which the semiconductor package substrate is mounted is four layers, the core substrate is four layers, and the second main surface (BGA side) which is the connection terminal side with the printed wiring board. The case where the built-up layer has a single 4-4-1 layer structure will be described. This description is an example and does not limit the layer structure of the semiconductor package substrate of the present invention.

  First, the core substrate 201 shown in FIG. 2A is prepared. The core substrate 201 is created by a conventional method for manufacturing a printed wiring board. A core substrate 201 shown in FIG. 2A is obtained by providing through holes 202 and interlayer conduction vias 203 on a substrate such as a glass fiber reinforced epoxy resin substrate and connecting wiring layers 204 on both sides of the substrate. As the core substrate 201, a substrate in which through holes and circuits are formed in a glass substrate may be used. In addition, the core substrate 201 may be a substrate having a circuit pattern formed on the front and back of the substrate, or may be a multi-layer circuit in which a plurality of inner layer circuits are formed. It is not limited. The total thickness of the core substrate 201 is desirably 0.05 mm or more and 3 mm or less. When the thickness is 0.05 mm or less, it may be difficult to manufacture with a good yield because the conveyance becomes difficult. Further, since the rigidity is lost when the package substrate is used, a problem of warpage is likely to occur. When the thickness is 3 mm or more, the package substrate is too thick and is not suitable for downsizing of electronic devices. More preferably, the thickness is 0.1 mm or more and 2 mm or less. The circuit metal of the core substrate is not limited in the present invention, but copper and its alloys are desirable because of its conductivity and easy formation.

  Subsequently, as shown in FIG. 2B, insulating resin layers 205 are formed on the top and bottom surfaces of the core substrate. The insulating resin layer 205 may be an epoxy-phenol resin, a photosensitive polyimide resin, a benzocyclobutene resin, a polybenzoxazole resin, a cycloolefin resin, or a modified product thereof. Furthermore, it may be a photosensitive or non-photosensitive resin, and may have a reinforced resin structure reinforced with glass fiber or engineering plastic fiber as necessary, and is appropriately filled with an inorganic or organic filler. You may do it. The kind of insulating resin is not particularly limited in the present invention.

  In the semiconductor package substrate of the present invention, as shown in FIG. 2B, the insulating resin layer 205 is formed on the front and back surfaces of the core substrate so as to have the same thickness. The thickness of the resin layer to be formed is desirably 2 μm or more and 40 μm from the surface of the metal circuit wiring on the core substrate. When the thickness of the insulating resin layer 205 is 2 μm or less, there is a possibility that insulation reliability between layers cannot be secured. When the thickness of the insulating resin layer 205 is 40 μm or more, a fine via hole cannot be formed because it is too thick, which causes a problem that a fine wiring layer cannot be formed. The thickness of the insulating resin layer 205 is more preferably 5 μm or more and 15 μm or less. In the present invention, the resin is formed on the first main surface and the second main surface so as to have the same thickness. It has been found by experiments of the present inventors that the warpage of the package substrate is due to the residual stress when the front and back resins are cured. Therefore, at least in the resin layer forming step, it is necessary to form a resin layer having the same thickness on the front and back, and to perform the curing process simultaneously on the front and back. The curing treatment may be heat treatment or UV curing, and the treatment is performed by an appropriate method depending on the resin used.

  As a method for forming the insulating resin layer 205, lamination, a vacuum laminating method, and a vacuum pressing method can be applied as long as the resin is a film-like resin. If it is liquid, it can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, ink jet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. The insulating resin forming method is not limited by the present invention.

  Subsequently, as shown in FIG. 2B, a via 206 is formed only on the first main surface. The via can be formed by, for example, laser processing. When the insulating resin layer 205 is a photosensitive insulating resin, a via may be formed by a photolithography method. In the case of laser processing, it is desirable to use a UV laser or excimer laser because a small diameter via can be formed. In the semiconductor package substrate of the present invention, the wiring density of the built-up layer on the first main surface is high and becomes a multilayer. In order to make the wiring layer of the first main surface high-layered, first, vias are formed only on the first main surface. In the method of manufacturing a semiconductor package substrate according to the present invention, the process of forming vias and wirings on only one side is performed at least once in the build-up process. The via diameter is desirably 5 μm or more and 40 μm or less. When the via diameter is 5 μm or less, it is difficult not only to form a via, but also to ensure the connection reliability of the via by a thermal cycle. When the via diameter is 40 μm or more, the wiring density of the built-up wiring layer on the first main surface cannot be made fine and high. A more preferable via diameter is 10 μm or more and 20 μm or less. After forming the via, a cleaning process inside the via is performed. In the cleaning process, a desmear process by immersion in a permanganic acid solution or a cleaning process by plasma process is performed.

  Subsequently, as shown in FIG. 2C, the wiring layer 208 is formed only on the first main surface. More specifically, after a seed layer (not shown) made of metal is formed on the insulating resin layer 205, a resist layer 207 is formed on both surfaces. The seed layer is formed only on the first main surface side or on both the first main surface side and the second main surface side. Next, a pattern is formed only on the resist layer 207 on the first main surface by photolithography. The resist layer 207 exists on the entire surface without forming a circuit pattern on the second main surface side. Subsequently, the wiring layer 208 is formed only on the first main surface side by electrolytic plating (semi-additive method) using the seed layer. The thickness of the seed layer in this step is preferably 0.05 μm or more and 1 μm or less. When the thickness of the seed layer is 0.05 μm or less, the resistance of the seed layer becomes high, so in the electrolytic plating process, it becomes impossible to uniformly energize the substrate surface, so that circuit wiring of a uniform height is formed in the substrate surface. become unable. Furthermore, the seed layer may be dissolved before being immersed in the electrolytic plating solution and energized, resulting in a problem that a circuit cannot be formed. On the other hand, as a problem when the seed layer becomes thick, the circuit pattern is also etched at the same time in the subsequent seed layer removal step, so that the circuit is thinned. If it is too thick, the circuit wiring itself disappears or peels off, causing a problem that the wiring cannot be formed. As a result of the study by the present inventors, when the seed layer thickness is larger than 1 μm, it is impossible to form a fine wiring with L / S = 5 μm or less. Therefore, it is desirable that it is 0.05 μm or more and 1 μm or less. The seed metal is selected from copper, nickel, titanium, gold, and chromium, but is not limited by the present invention. The seed layer forming method can be selected from vapor deposition, sputtering, and electroless plating. A resist layer 207 is formed on the seed layer thus formed. The formation of the resist layer 207 may be either a liquid resist or a dry film resist. As a method for forming the resist layer, a known method is appropriately used. The thickness of the resist layer for forming the inner layer circuit on the first main surface side is preferably 15 μm or less. When the thickness of the resist layer is larger than 15 μm, it becomes impossible to form fine wiring with L / S = 5 μm or less. The resist pattern can be formed by known photolithography. Furthermore, the thickness of the wiring layer 208 on the first main surface side formed by electrolytic plating is desirably 10 μm or less. When the thickness of the wiring layer 208 is larger than 10 μm, it is necessary to make the thickness of the resist pattern larger than 10 μm, so that the resolution of the resist cannot be secured, and it becomes impossible to form a fine circuit with L / S = 5 μm or less. . Therefore, the thickness of the wiring layer 208 is desirably 10 μm or less.

  Subsequently, the resist layer 207 on the front and back sides of the substrate is peeled off, and then the unnecessary seed layer on the front and back sides is removed by etching, thereby forming a built-up wiring layer only on the first main surface shown in FIG. A finished substrate is obtained. A wiring layer 208 is formed only on the first main surface of the substrate shown in FIG.

  Subsequently, the insulating resin layer formation on both sides of the substrate and the circuit formation only on the first main surface are repeated twice in the same manner, and the insulating resin layer 205 is further laminated, whereby 3-4-0 shown in FIG. A built-up multilayer wiring board having an asymmetric layer structure is prepared. According to the method of the present invention, the total thickness of the built-up wiring layer on the first main surface side of the multilayer wiring board and the built-up wiring on the second main surface even in the asymmetric layer structure in which the number of built-up layers is remarkably biased. Since the layer thicknesses of the layers are approximately equal, the amount of cure shrinkage is equal and can be balanced to minimize package warpage. Further, since the resin etching process such as desmear or plasma process is performed only once for each insulating resin layer, the surface of the insulating resin layer is not deteriorated. Therefore, a package substrate having excellent insulation reliability can be created.

  Subsequently, as shown in FIG. 2 (f), a small diameter via 206 having a diameter of 5 μm or more and 40 μm or less is formed on the first main surface side, and a diameter larger than that of the via formed on the first main surface is formed on the second main surface side. A large via 209 is formed. In the structure of the semiconductor package substrate according to the present invention, the via 209 formed on the second main surface passes through the plurality of insulating resin layers and reaches the surface of a predetermined via receiving pad. In FIG. 2F, four layers are described as an example, but the total number is not limited to this example. The diameter of the via 209 on the second main surface side is preferably larger than the diameter of the via 206 on the first main surface side and has a via diameter of 20 μm to 100 μm. When the diameter of the via 209 is smaller than 20 μm, it may not be possible to penetrate to a desired via receiving pad depending on the resin thickness laminated on the second main surface. When the diameter of the via 209 is larger than 100 μm, the diameter may be too large in the subsequent electrolytic copper plating process, and the metal plating may not be filled in the via. Therefore, it is desirable to be 20 μm or more and 100 μm or less. Although it is a via formation method of the 2nd principal surface, it is desirable that it is laser processing. The laser can be selected from a carbon dioxide laser and an ultraviolet laser. According to the semiconductor package substrate of the present invention, a fine circuit having an L / S of 5 μm or less has only to be formed on one side, and the process can be simplified. In particular, since it becomes possible to eliminate several times of pattern exposure processes on the back surface, a fine circuit can be efficiently manufactured with a high yield. Subsequently, after the via is formed, a cleaning process inside the via is performed by desmearing by immersion in a permanganic acid solution or by plasma processing. Subsequently, a seed metal layer (not shown) is formed on the surface of the insulating resin layer 205 by electroless plating or sputtering film formation. The thickness of the seed metal layer is not defined by the present invention, but it is preferably 0.02 μm or more and 1 μm or less as in the above.

  Subsequently, as shown in FIG. 2 (g), a resist layer 207 is formed on the seed metal layer, a pattern is formed by photolithography, and then the first main surface is connected to a semiconductor chip by electrolytic plating. If the protruding electrode 210a is the second main surface, a BGA pad 210b and / or wiring (not shown) serving as a connection terminal to the printed wiring board is formed. As shown in FIG. 2G, according to the method of the present invention, the wiring formed on the second main surface is rougher than the wiring layer 204 formed on the first main surface side, and the diameter of the via 209 is also large. Therefore, in order to fill the inside of the via 209 with the plating film, the plating thickness is inevitably increased. When the diameter of the via 209 is 20 μm or more and 100 μm or less, the thickness of the circuit pattern on the second main surface is desirably 10 μm or more and 40 μm or less, and more desirably 10 μm or more and 25 μm or less. On the other hand, the protruding electrode 210a, which is a connection terminal to the semiconductor chip, can absorb the expansion and contraction due to the thermal shock of the substrate as the protruding height is higher. Therefore, it is desirable that the protruding electrode 210a can be formed as high as possible within the practical height range. More preferably, the thickness is the same as that of the wiring on the second main surface because it can be formed simultaneously in the process. That is, the protruding electrode 210a formed on the first main surface is desirably 10 μm or more and 40 μm or less. According to the present invention, the projecting electrode on the first main surface, which requires a thick plating thickness, and the circuit on the second main surface are formed at the same time, which is efficient. Furthermore, a surface treatment layer may be formed on the bump electrode or the BGA pad in the state after the electrolytic plating in FIG. As the type of surface treatment, Ni—Au plating, Ni—Pd—Au plating, OSP, tin plating, Sn—Ag plating, molten solder plating, or the like may be performed. Further, a solder layer may be formed after the surface treatment. Conventionally known techniques can be used for the surface treatment and the solder forming method.

  Subsequently, as shown in FIG. 2 (h), after peeling off the resist layer 207, the unnecessary metal seed layer is removed by etching, a solder resist layer is formed on the front and back of the substrate, and a solder resist pattern is formed by photolithography. By forming 211, the semiconductor package substrate according to the present invention is manufactured.

  Further, as shown in FIG. 2I, a plurality of semiconductor chips 212 are mounted on the first main surface, and solder balls 213 are formed on the BGA pads 210b, thereby completing a semiconductor package product.

Example 1
Examples of the present invention are shown below. In the embodiment of the present invention, a substrate having a 4-4-1 structure was manufactured as shown in FIG. An embodiment of the present invention will be described with reference to FIGS. 2A to 2D. An insulating resin layer is formed by laminating a 15 μm-thick insulating resin on both surfaces of a core substrate on which a four-layer circuit wiring manufactured by a conventional printed wiring board manufacturing method is formed, and then thermosetting it. did. Subsequently, via holes with a via diameter of 20 μm were formed only on the first main surface side of the semiconductor package substrate by a UV-YAG laser. At this time, no interlayer connection via hole is formed in the resin on the second main surface side. Subsequently, the substrate was immersed in an alkaline permanganate bath to remove laser smear, and an electroless plating layer was formed at 0.5 μm. Subsequently, a dry film resist having a thickness of 10 μm was formed on the first and second main surfaces by a laminating method. Subsequently, only the first main surface was exposed with a stepper exposure machine using a photomask having a minimum circuit pattern of L / S = 5/5. The dry film resist on the second main surface was exposed to the whole surface, and a resist layer was formed on the front surface of the second main surface. Subsequently, spray development was performed with a 1% sodium carbonate solution. Furthermore, circuit wiring was prepared with a circuit thickness of 7 μm by electrolytic plating.

  Subsequently, the production of the semiconductor package substrate of the present invention will be described through the steps of FIGS. As shown in FIG. 2E, the above build-up process was repeated three times to complete the fourth layer of resin laminate. Subsequently, as shown in FIG. 2 (f), a via hole of 20 μm is formed on the first main surface using a UV-YAG laser, and a via diameter of 60 μm is formed on the second main surface using the same laser processing machine. A via hole was formed. Subsequently, it was immersed in a permanganic acid solution, and after removing smear, electroless plating was formed to a thickness of 1 μm. Further, a dry film resist was formed on both sides with a thickness of 25 μm. A protruding electrode pattern was formed on the first main surface side with a diameter of 30 μm and a pitch of 50 μm, and a protruding electrode pattern was formed on the second main surface with a diameter of 150 μm and a pitch of 500 μm. Subsequently, electrolytic copper plating was formed on the front and back surfaces with a thickness of 20 μm. Subsequently, Sn—Ag solder plating was performed at a height of 3 μm after electrolytic Ni—Ag plating on both surfaces. After removing the resist, the seed layer was removed by etching.

(Comparative Example 1)
In Comparative Example 1, only one layer was formed without laminating four layers of resin on the second main surface described in Example 1. After laminating an insulating resin of 15 μm on both surfaces on the core substrate, vias are formed on the first main surface with a thickness of 20 μm, and desmear treatment, electroless plating, and photoresist patterning are performed. A circuit was formed on the first main surface, and a resist layer was formed on the second seed surface by exposing the resist to the front surface. After removing the resist and electrolytic plating, the seed layer was removed. Further, a resin layer was formed only on the first main surface, and no resin was formed on the second main surface, and the same procedure as in Example 1 was performed. The outermost layer was formed in the same manner as in Example 1.

(Comparative Example 2)
In Comparative Example 2, solder bumps were formed by a conventional ball mounting method without forming protruding electrodes on the first main surface. The solder bumps were formed by mounting solder balls having a pitch of 50 μm and a diameter of 30 μm by a ball mounting method.

(Comparative Example 3)
In Comparative Example 3, a wiring having a minimum pattern width LS = 5 μm was also formed on the second main surface. The layer structure is the target structure of 2-4-2. A wiring board of Comparative Example 3 was prepared in the same manner as in Example 1 except that the wiring on the second main surface was prepared with the same construction method and wiring width as the first main surface.

Table 1 shows the evaluation results of the semiconductor package substrates according to Example 1 and the comparative example of the present invention. The amount of warpage in Table 1 is the lifting height from the flat surface when the semiconductor package substrate is placed on the flat surface, and is positive when the peripheral portion is lifted from the flat surface (when the flat surface side is a convex surface). The case where the center part floats from the flat surface (when the flat surface side becomes a concave surface) is expressed by a negative value. In addition, the primary mounting evaluation represents a non-defective product ratio (ratio of electrical normal connection) when the semiconductor chip is mounted on the first main surface, and the secondary mounting evaluation is performed using the semiconductor package substrate as a printed wiring board. The percentage of non-defective products when mounted on (the ratio of electrical connection normally).

  In Example 1 of the present invention, the production yield can be made well. In Comparative Example 1, since desmear treatment is performed four times more than one resin layer on the second main surface, peeling of the wiring on the second main surface side and the BGA pad was observed, resulting in a low yield. . Since Comparative Example 2 was the same process as Example 1 except that no protruding electrode was formed on the first main surface, the yield was good, but the connection terminals between the first main surface and the semiconductor chip were solder bumps. Therefore, the difference in thermal expansion coefficient between the semiconductor chip and the semiconductor package substrate could not be absorbed, and the pass rate of the primary mounting evaluation was low. Comparative Example 3 is a structure in which the built-up layer configuration of the first main surface and the second main surface is symmetric, and has a configuration in which fine wiring is formed on both surfaces. The secondary mounting evaluation is low due to the observation of wiring separation caused by contact.

  As a result of the examples and comparative examples of the present invention, the semiconductor package substrate according to the present invention can contribute to miniaturization and high reliability of the semiconductor chip. That is, it is possible to efficiently form a fine multilayer wiring required only on the first main surface with a high yield. Furthermore, it is possible to ensure the secondary mounting reliability by forming the relatively thick wiring as before on the second main surface. Although the total number of wirings on the front and back sides is asymmetric, the total thickness of the laminated resin is symmetric, so that warpage can be effectively suppressed. Therefore, it is possible to prevent a decrease in yield due to a decrease in mountability due to warpage, and further a decrease in reliability.

  The present invention can be used for a semiconductor package in which a plurality of semiconductor chips are mounted.

101 ... Memory chip 102 ... TSV; Through Silicon Via
103 ... Bump 104 ... Package substrate 105 ... Logic chip 106 ... Silicon interposer 107 ... Package substrate 201 having a glass interposer or an organic interposer as a core ... Core substrate 202 ... Through hole 203 ... via 204 ... wiring layer 205 ... insulating resin layer 206 ... via 207 ... resist layer 208 ... wiring layer 209 ... via 210a ... projection electrode 210b ... BGA (Ball Grid Array) pad 211 ... Solder resist pattern 212 ... Semiconductor chip 213 ... Solder ball

Claims (4)

A semiconductor package substrate having a first main surface on which a semiconductor chip is mounted and a second main surface on which external connection terminals for electrical connection with a printed wiring board are formed,
A core substrate;
A circuit wiring layer provided on the first main surface side and the second main surface side of the core substrate, comprising a wiring layer and an insulating resin layer;
The number of wiring layers formed on the first main surface side is larger than the number of wiring layers formed on the second main surface side,
The thickness of the wiring layer on the first main surface side is thinner than the thickness of the wiring layer on the second main surface,
The via diameter for conducting between the layers of the circuit wiring layer formed on the first main surface side is smaller than the via diameter formed on the second main surface side,
The number of insulating resin layers formed on the first main surface side is equal to the number of insulating resin layers formed on the second main surface side,
A projecting electrode protruding from the outermost surface of the first main surface is provided on the first main surface side.   The semiconductor package substrate according to claim 1, wherein the core substrate is a glass substrate or a glass fiber reinforced resin substrate on which at least two circuit wiring layers are formed.   The thickness of the metal layer provided on the outermost layer of the first main surface and the second main surface is greater than the thickness of the metal layer provided on the inner layer of the first main surface and the second main surface. The semiconductor package substrate according to claim 1. A method for manufacturing a semiconductor package substrate having a first main surface on which a semiconductor chip is mounted and a second main surface on which external connection terminals for electrical connection with a printed wiring board are formed,
A first step of laminating insulating resin layers of the same thickness on both sides of the core substrate;
A second step of forming a via and a wiring layer only on the first main surface side of the core substrate;
A third step of laminating an insulating resin layer of the same thickness on the outermost surfaces of the first main surface side and the second main surface side so as to cover the formed via and wiring layer;
A fourth step of repeating the second step and the third step a plurality of times to form a circuit wiring layer comprising the wiring layer and the insulating resin layer on the first main surface side of the core substrate;
And a fifth step of forming a via and a connection electrode on the first main surface side and forming a via and a wiring layer on the second main surface side.