CN118281078B - Semiconductor structure and its formation method - Google Patents
Semiconductor structure and its formation methodInfo
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- CN118281078B CN118281078B CN202410425660.8A CN202410425660A CN118281078B CN 118281078 B CN118281078 B CN 118281078B CN 202410425660 A CN202410425660 A CN 202410425660A CN 118281078 B CN118281078 B CN 118281078B
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Abstract
一种半导体结构及其形成方法，其中方法包括：提供衬底，所述衬底包括绝缘层和位于所述绝缘层上的衬底层；在部分所述衬底表面形成栅极；在所述栅极侧壁形成主侧墙；在形成所述主侧墙之后，在所述衬底表面形成第一外延层；以所述主侧墙和所述栅极为掩膜，向所述第一外延层表面注入第一掺杂离子，在所述第一外延层和所述衬底内形成源漏掺杂区，利于降低源和漏串联电阻，提高载流子速率，降低结电容以及增强电流密度，利于抑制短沟道效应，提高MOSFET器件性能。
A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate including an insulating layer and a substrate layer located on the insulating layer; forming a gate on a portion of the substrate surface; forming a main sidewall on the gate sidewall; forming a first epitaxial layer on the substrate surface after forming the main sidewall; using the main sidewall and the gate as a mask, implanting first doped ions into the surface of the first epitaxial layer to form source and drain doped regions in the first epitaxial layer and the substrate, which is beneficial for reducing the source and drain series resistance, increasing the carrier velocity, reducing the junction capacitance and enhancing the current density, and is beneficial for suppressing the short-channel effect and improving the performance of the MOSFET device.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
A Metal-Oxide-semiconductor field effect transistor (abbreviated as MOSFET) is one of the most widely used device structures at present. MOSFETs are four-terminal devices having source, gate, drain and body terminals, the function of which is primarily determined by the flow of carriers in the channel width, which enter the channel through the source and exit through the drain.
Along with the continuous development of semiconductor technology, the nodes of the semiconductor technology are continuously miniaturized, the transistors are continuously reduced, parasitic capacitance, short channel effect and device subthreshold current become main factors for preventing the further development of the semiconductor technology, in the process technology, the short channel effect can be controlled by improving the doping concentration of a channel position, but the coulomb scattering problem can be led out by a highly doped channel, so that the carrier mobility is reduced, and the speed of the device is reduced.
In summary, the performance of MOSFET devices formed in the prior art is in need of improvement.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of the formed semiconductor structure.
In order to solve the technical problems, the technical scheme of the invention provides a semiconductor structure, which comprises a substrate, a grid electrode, a main side wall, a first epitaxial layer and a source-drain doping region, wherein the substrate comprises an insulating layer and a substrate layer positioned on the insulating layer, the grid electrode is positioned on part of the surface of the substrate, the main side wall is positioned on the side wall of the grid electrode and the surface of the substrate, the first epitaxial layer is positioned on the substrate on two sides of the grid electrode and the main side wall, and the first epitaxial layer is positioned on two sides of the grid electrode and the main side wall and the source-drain doping region is positioned in the substrate.
The semiconductor device comprises a grid electrode, a grid electrode side wall, a light doping region and a light doping region, wherein the grid electrode side wall is arranged between the grid electrode side wall and the main side wall, the light doping region is arranged in a substrate at two sides of the grid electrode and surrounds the source and drain doping region, and the conductivity types of the source and drain doping region and the light doping region are the same.
Optionally, the lightly doped region part also extends to the bottom of the offset side wall, and the lightly doped region part also extends to the bottom of the grid electrode.
The semiconductor device comprises a grid, a first epitaxial layer, a light doped region, a source drain doped region, a second epitaxial layer, a main side wall, a first epitaxial layer, a second epitaxial layer, a source drain doped region and a source drain doped region, wherein the second epitaxial layer is positioned on the surfaces of the substrate on two sides of the grid and the offset side wall, the main side wall and the first epitaxial layer are positioned on the surfaces of the second epitaxial layer, the light doped region is also positioned in the second epitaxial layer on two sides of the offset side wall and the grid, and the source drain doped region is also positioned in the second epitaxial layer on two sides of the grid and the main side wall.
Optionally, the source-drain doped region also extends to the bottom of the main side wall.
Optionally, the device further comprises a halo region which is positioned in the substrate at two sides of the offset side wall and the grid electrode and surrounds the source-drain doped region, the depth of the halo region is larger than that of the lightly doped region, and the conductivity types of the source-drain doped region and the halo region are different.
Optionally, the depth of the source-drain doped region is greater than the depth of the lightly doped region.
Optionally, the material of the insulating layer comprises silicon oxide, and the material of the substrate layer comprises silicon.
Optionally, the bottom of the source-drain doped region is not contacted with the surface of the insulating layer.
Optionally, the bottom of the source-drain doped region is in contact with the surface of the insulating layer.
Optionally, the semiconductor device further comprises a contact layer positioned on part of the surface of the source-drain doped region, wherein the material of the contact layer comprises metal silicide.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the steps of providing a substrate, forming a grid electrode on part of the surface of the substrate, forming a main side wall on the side wall of the grid electrode, forming a first epitaxial layer on the surface of the substrate after the main side wall is formed, and implanting first doping ions into the surface of the first epitaxial layer by taking the main side wall and the grid electrode as masks, and forming source-drain doping regions in the first epitaxial layer and the substrate.
Optionally, after the grid electrode is formed and before the main side wall is formed, the method comprises the steps of forming offset side walls on the side walls of the grid electrode, implanting second doping ions into the surface of the substrate by taking the offset side walls and the grid electrode as masks, forming an initial lightly doped region in the substrate, wherein the conductivity types of the source and drain doping regions are the same as those of the initial lightly doped region, and the initial lightly doped region outside the source and drain doping region is a lightly doped region.
Optionally, the initial lightly doped region part also extends to the bottom of the offset side wall, and the forming method of the initial lightly doped region further comprises a second annealing process after the second doped ion implantation process so as to diffuse the second doped ions to the bottom of the offset side wall.
Optionally, the initial lightly doped region part also extends to the bottom of the grid electrode, and the forming method of the initial lightly doped region further comprises a second annealing process after the second doped ion implantation process so as to diffuse the second doped ions to the bottom of the grid electrode.
Optionally, after forming the offset side wall and before forming the initial lightly doped region, a second epitaxial layer is formed on the surfaces of the substrate on two sides of the grid electrode and the offset side wall, the initial lightly doped region is formed by implanting second doped ions into the second epitaxial layer, after forming the initial lightly doped region, the main side wall is formed and is further located on the surface of the second epitaxial layer, the first epitaxial layer is formed on the surface of the second epitaxial layer, and the first doped ions are also implanted into the second epitaxial layer to form the source-drain doped region.
Optionally, the source-drain doped region also extends to the bottom of the main side wall, and the forming method of the source-drain doped region further comprises a first annealing process after the first doped ion implantation process so as to diffuse the first doped ions to the bottom of the main side wall.
Optionally, after the offset side wall is formed and before the main side wall is formed, the method further comprises the steps of taking the offset side wall and the grid electrode as masks, implanting third doped ions into the second epitaxial layer, wherein the implantation depth of the third doped ions is larger than that of the second doped ions, and forming an initial halo region, and taking the initial halo region outside the source drain doped region as a halo region.
Optionally, the initial halo region is formed after the initial lightly doped region is formed.
Optionally, the second epitaxial layer forming process includes a selective epitaxial growth process.
Optionally, the method for forming the grid electrode comprises the steps of forming a grid electrode material layer on the surface of the substrate, forming a hard mask layer on the surface of a part of the grid electrode material layer, and etching the grid electrode material layer by taking the hard mask layer as a mask to form the grid electrode.
Optionally, the forming process of the first epitaxial layer includes a selective epitaxial growth process.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure, the substrate comprises the insulating layer and the substrate layer positioned on the insulating layer, the first epitaxial layer is formed on the surface of the substrate, first doping ions are injected into the surface of the first epitaxial layer, the source-drain doping region is formed in the first epitaxial layer and the substrate, the insulating layer limits the depth of a channel, the source-drain doping region protrudes out of the channel, the series resistance of the source and the drain is reduced, the carrier speed is improved, the junction capacitance is reduced, the current density is enhanced, the short channel effect is suppressed, and the performance of the MOSFET device is improved.
Further, the second epitaxial layer is used for accurately positioning the implantation precision of the second doping ions, so that the stability of the formed device is improved.
Further, the lightly doped region facilitates suppression of hot carrier injection effects (Hot Carrier Injection, abbreviated HCI).
Further, the halo region is utilized to reduce the occurrence of source-drain punch-through anomalies.
In the semiconductor structure provided by the technical scheme of the invention, the substrate comprises the insulating layer and the substrate layer positioned on the insulating layer, the insulating layer limits the depth of the channel, and the source-drain doped region protrudes out of the channel, so that the structure is beneficial to reducing the series resistance of the source and the drain, improving the carrier speed, reducing the junction capacitance and enhancing the current density, and is beneficial to inhibiting the short channel effect and improving the performance of the MOSFET device.
Further, the lightly doped region facilitates suppression of hot carrier injection effects (Hot Carrier Injection, abbreviated HCI).
Further, the halo region is utilized to reduce the occurrence of source-drain punch-through anomalies.
Drawings
Fig. 1 to 7 are schematic structural views of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
Note that "surface", "upper", as used herein, describes a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
As described in the background, the performance of MOSFET devices formed in the prior art is in need of improvement.
In order to solve the above problems, in the structure of a semiconductor structure and the method for forming the same, a substrate comprises an insulating layer and a substrate layer on the insulating layer, a first epitaxial layer is formed on the surface of the substrate, first doping ions are injected into the surface of the first epitaxial layer, source-drain doping regions are formed in the first epitaxial layer and the substrate, the insulating layer limits the depth of a channel, the source-drain doping regions protrude out of the channel, the structure of reducing the series resistance of the source and the drain, improving the carrier velocity, reducing the junction capacitance and enhancing the current density, and the method is beneficial to inhibiting the short channel effect and improving the performance of a MOSFET device.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 7 are schematic structural views of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 including an insulating layer 101 and a substrate layer 102 on the insulating layer 101.
The insulating layer 101 is used to limit the channel depth of the formed MOS device.
In this embodiment, the thickness of the substrate layer 102 is 17nm. In other embodiments, the thickness of the substrate layer may be adjusted according to actual needs. It should be noted that, the thickness described herein refers to a dimension perpendicular to the surface of the substrate 100.
In this embodiment, the material of the insulating layer 101 includes silicon oxide.
In this embodiment, the material of the substrate layer 102 includes silicon. In other embodiments, the material of the substrate layer may also be a material such as silicon germanium, or the like.
Referring to fig. 2, a gate 103 is formed on a portion of the surface of the substrate 100.
In this embodiment, the method for forming the gate 103 includes forming a gate material layer (not shown) on the surface of the substrate 100, forming a hard mask layer 104 on a portion of the surface of the gate material layer, and etching the gate material layer with the hard mask layer 104 as a mask until the surface of the substrate 100 is exposed, thereby forming the gate 103.
In this embodiment, the material of the gate 103 is polysilicon.
In this embodiment, a gate oxide layer 105 is further disposed between the substrate 100 and the gate 103. The method for forming the gate oxide layer 105 includes forming a gate oxide material layer (not shown) on the surface of the substrate 100 before forming the gate material layer, and forming the gate oxide layer 105 with the gate oxide material layer.
And forming a main side wall on the side wall of the grid electrode 103. In this embodiment, please refer to fig. 3 to 4 after the gate 103 is formed and before the main sidewall is formed.
Referring to fig. 3, offset spacers 106 are formed on the sidewalls of the gate 103.
The material of the offset sidewall 106 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, and silicon oxycarbonitride. In this embodiment, the material of the offset sidewall 106 is aluminum oxide (Al 2O3).
In this embodiment, the method for forming the offset spacers 106 includes forming a first dielectric material layer (not shown in the figure) on the gate 103 and the surface of the substrate 100, and etching back the first dielectric material layer until the surface of the substrate 100 and the top surface of the gate 103 are exposed.
In this embodiment, the forming process of the first dielectric material layer includes an atomic layer deposition process. The atomic layer deposition process is beneficial to improving the thickness uniformity of a formed material film.
Referring to fig. 4, with the offset spacers 106 and the gate 103 as masks, second doping ions are implanted into the surface of the substrate 100, so as to form an initial lightly doped region 107 in the substrate 100.
The conductivity type of the source drain doped region is the same as that of the initial lightly doped region 107. In this embodiment, the conductivity types of the source-drain doped region and the initial lightly doped region 107 are both N-type for forming an NMOS device. In another embodiment, the conductivity type of the source-drain doped region and the initial lightly doped region is P-type for forming a PMOS device.
In this embodiment, after the offset spacers 106 are formed and before the initial lightly doped regions 107 are formed, a second epitaxial layer 108 is further formed on the gate 103 and the surfaces of the substrate 100 on both sides of the offset spacers 106.
In this embodiment, the second epitaxial layer 108 is formed by a selective epitaxial growth process.
In this embodiment, the method for forming the initial lightly doped region 107 further includes implanting the second doping ions into the second epitaxial layer 108. The second epitaxial layer 108 is used to precisely position the accuracy of the implantation of the second dopant ions, which is beneficial to improving the stability of the device.
In this embodiment, the initial lightly doped region 107 further extends to the bottom of the gate 103, and the method for forming the initial lightly doped region 107 further includes a second annealing process after the second doping ion implantation process to diffuse the second doping ions to the bottom of the gate 103.
In another embodiment, the initial lightly doped region part also extends to the bottom of the offset side wall, and the forming method of the initial lightly doped region further comprises a second annealing process after the second doped ion implantation process so as to diffuse the second doped ions to the bottom of the offset side wall.
In this embodiment, after the offset spacers 106 are formed and before the main spacers are formed, third doped ions are further implanted into the second epitaxial layer 108 by using the offset spacers 106 and the gate 103 as masks, and the implantation depth of the third doped ions is greater than that of the second doped ions, so as to form an initial halo region (not shown in the figure).
The source-drain doped region and the initial halo region have different conductivity types. In this embodiment, the conductivity type of the initial halo region is P-type. In another embodiment, the conductivity type of the initial halo region is N-type. In yet another embodiment, the initial halo region may not be formed.
In this embodiment, after the initial lightly doped region 107 is formed, the initial halo region (not shown in the figure) is formed.
Referring to fig. 5, a main sidewall 109 is formed on the sidewall of the gate 103.
Specifically, after the initial lightly doped region 107 is formed, the main sidewall 109 is formed, and the main sidewall 109 is further located on the surface of the second epitaxial layer 108.
The material of the main side wall 109 comprises a dielectric material including one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, and silicon oxycarbonitride. In this embodiment, the material of the main side wall 109 is silicon nitride.
Referring to fig. 6, after the main sidewall 109 is formed, a first epitaxial layer 110 is formed on the surface of the substrate 100.
Specifically, the first epitaxial layer 110 is formed on the surface of the second epitaxial layer 108.
Referring to fig. 7, first doping ions are implanted into the surface of the first epitaxial layer 110 by using the main sidewall 109 and the gate 103 as masks, so as to form source-drain doped regions 111 in the first epitaxial layer 110 and the substrate 100.
The insulating layer 101 limits the depth of the channel, and the doped source/drain region 111 protrudes out of the channel, which is beneficial to reducing the series resistance of the source and the drain, improving the carrier rate, reducing the junction capacitance and enhancing the current density, and is beneficial to inhibiting the short channel effect and improving the performance of the MOSFET device.
In this embodiment, the bottom of the source-drain doped region 111 is in contact with the surface of the insulating layer 101. The bottom of the source-drain doped region 111 is in contact with the surface of the insulating layer 101, so as to form a fully depleted (Fully Depleted abbreviated as FD) structure. In another embodiment, the bottom of the source-drain doped region may not contact the surface of the insulating layer, so as to form a partially depleted (PARTIALLY DEPLETED, abbreviated as PD) structure.
In this embodiment, the forming process of the first epitaxial layer 110 includes a selective epitaxial growth process.
In this embodiment, the first dopant ions are also implanted into the second epitaxial layer 108 to form the source-drain doped region 111.
In this embodiment, the initial lightly doped region 107 (as shown in fig. 6) outside the source/drain doped region 111 is also referred to as a lightly doped region 112. The lightly doped region 112 facilitates suppression of hot carrier injection effects (Hot Carrier Injection, abbreviated HCI).
In this embodiment, the initial halo region outside the source-drain doped region 111 is also referred to as a halo region (not shown in the figure). The halo region is used for reducing the occurrence of source-drain punch-through abnormality.
In this embodiment, the source-drain doped region 111 further extends to the bottom of the main sidewall 109, and the method for forming the source-drain doped region 111 further includes a first annealing process after the first doped ion implantation process to diffuse the first doped ions to the bottom of the main sidewall 109.
In this embodiment, after the source-drain doped region 111 is formed, a contact layer 113 is further formed on a portion of the surface of the source-drain doped region 111.
In this embodiment, the material of the contact layer 113 includes metal silicide. The contact layer 113 is used to reduce the contact resistance between the conductive layer formed later and the source/drain doped region 111.
Correspondingly, the embodiment of the invention also provides a semiconductor structure formed by adopting the method, and referring to fig. 7, the substrate 100 is continued, the substrate 100 comprises an insulating layer 101 and a substrate layer 102 positioned on the insulating layer 101, a grid 103 positioned on part of the surface of the substrate 100, a main side wall 109 positioned on the side wall of the grid 103 and the surface of the substrate 100, a first epitaxial layer 110 positioned on the substrate 100 at two sides of the grid 103 and the main side wall 109, and source-drain doping regions 111 positioned in the first epitaxial layer 110 and the substrate 100 at two sides of the grid 103 and the main side wall 109.
The insulating layer 101 limits the depth of the channel, and the doped source/drain region 111 protrudes out of the channel, which is beneficial to reducing the series resistance of the source and the drain, improving the carrier rate, reducing the junction capacitance and enhancing the current density, and is beneficial to inhibiting the short channel effect and improving the performance of the MOSFET device.
In this embodiment, the semiconductor structure further includes an offset sidewall 106 located between the sidewall of the gate 103 and the main sidewall 109, a lightly doped region 112 located in the substrate 100 at two sides of the offset sidewall 106 and the gate 103 and surrounding the source-drain doped region 111, where the conductivity types of the source-drain doped region 111 and the lightly doped region 112 are the same. The lightly doped region 112 facilitates suppression of hot carrier injection effects (Hot Carrier Injection, abbreviated HCI).
In this embodiment, the lightly doped region 112 further extends to the bottom of the offset sidewall 106, and the lightly doped region 112 further extends to the bottom of the gate 103.
In this embodiment, the semiconductor structure further includes a second epitaxial layer 108 on the surfaces of the substrate 100 on both sides of the gate 103 and the offset sidewall 106, the main sidewall 109 and the first epitaxial layer 110 are on the surfaces of the second epitaxial layer 108, the lightly doped region 112 is further located in the second epitaxial layer 108 on both sides of the offset sidewall 106 and the gate 103, and the source-drain doped region 111 is further located in the second epitaxial layer 108 on both sides of the gate 103 and the main sidewall 109.
In this embodiment, the source-drain doped region 111 further extends to the bottom of the main sidewall 109.
In this embodiment, the semiconductor structure further includes a halo region (not shown) located in the substrate 100 at two sides of the offset sidewall 106 and the gate 103 and surrounding the source-drain doped region 111, where the depth of the halo region is greater than the depth of the lightly doped region 112, and the conductivity types of the source-drain doped region 111 and the halo region are different. The halo region is used for reducing the occurrence of source-drain punch-through abnormality.
In this embodiment, the depth of the source-drain doped region 111 is greater than the depth of the lightly doped region 112.
In this embodiment, the material of the insulating layer 101 includes silicon oxide, and the material of the substrate layer 102 includes silicon.
In this embodiment, the bottom of the source-drain doped region 111 is in contact with the surface of the insulating layer 101. In another embodiment, the bottoms of the source-drain doped regions are not in contact with the surface of the insulating layer.
In this embodiment, the semiconductor structure further includes a contact layer 113 located on a portion of the surface of the source-drain doped region 111, where a material of the contact layer 113 includes a metal silicide. The contact layer 113 is used to reduce the contact resistance between a conductive layer (not shown) and the source drain doped region 111.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (18)
1. A semiconductor structure, comprising:
A substrate comprising an insulating layer and a substrate layer on the insulating layer;
A gate electrode located on a portion of the substrate surface;
the main side wall is positioned on the side wall of the grid electrode and the surface of the substrate;
The first epitaxial layer is positioned on the substrate at the two sides of the grid electrode and the main side wall;
The first epitaxial layer and the source-drain doped region are positioned on two sides of the grid electrode and the main side wall;
offset spacers located between the gate sidewalls and the main sidewalls;
The lightly doped region is positioned in the substrate at two sides of the offset side wall and the grid electrode and surrounds the source-drain doped region, and the conductivity types of the source-drain doped region and the lightly doped region are the same;
The second epitaxial layers are positioned on the surfaces of the substrate at two sides of the grid electrode and the offset side wall, and the main side wall and the first epitaxial layer are positioned on the surfaces of the second epitaxial layers;
The lightly doped region is also positioned in the second epitaxial layer at the two sides of the offset side wall and the grid electrode;
The source-drain doped region is also positioned in the second epitaxial layer at the two sides of the grid electrode and the main side wall.
2. The semiconductor structure of claim 1, wherein said lightly doped region portion further extends to a bottom of said offset sidewall and said lightly doped region portion further extends to a bottom of said gate.
3. The semiconductor structure of claim 1, wherein the source drain doped region further extends to the bottom of the main sidewall.
4. The semiconductor structure of claim 1, further comprising a halo region within the offset sidewall and the gate substrate and surrounding the source drain doped region, the halo region having a depth greater than a depth of the lightly doped region, the source drain doped region and the halo region having different conductivity types.
5. The semiconductor structure of claim 1, wherein a depth of the source drain doped region is greater than a depth of the lightly doped region.
6. The semiconductor structure of claim 1, wherein the material of the insulating layer comprises silicon oxide and the material of the substrate layer comprises silicon.
7. The semiconductor structure of claim 1, wherein a bottom of said source drain doped region is not in contact with a surface of said insulating layer.
8. The semiconductor structure of claim 1, wherein a bottom of said source drain doped region is in contact with a surface of said insulating layer.
9. The semiconductor structure of claim 1, further comprising a contact layer on a portion of a surface of said source drain doped region, wherein a material of said contact layer comprises a metal silicide.
10. A method of forming a semiconductor structure, comprising:
Providing a substrate, wherein the substrate comprises an insulating layer and a substrate layer positioned on the insulating layer;
Forming a grid electrode on part of the surface of the substrate;
forming offset side walls on the side walls of the grid electrode;
forming a second epitaxial layer on the surfaces of the substrate at two sides of the grid electrode and the offset side wall;
Injecting second doping ions into the surface of the substrate by taking the offset side wall and the grid electrode as masks, and forming initial lightly doped regions in the substrate and the second epitaxial layer;
after the initial lightly doped region is formed, forming a main side wall on the side wall of the grid electrode, wherein the main side wall is also positioned on the surface of the second epitaxial layer;
forming a first epitaxial layer on the surface of the second epitaxial layer after forming the main side wall;
And implanting first doping ions into the surface of the first epitaxial layer by taking the main side wall and the grid electrode as masks, forming source-drain doping regions in the first epitaxial layer, the second epitaxial layer and the substrate, and taking the initial lightly doped region outside the source-drain doping regions as a lightly doped region, wherein the conductivity types of the source-drain doping regions and the initial lightly doped region are the same.
11. The method of claim 10, wherein said initial lightly doped region portion further extends to said offset sidewall bottom portion, and wherein said initial lightly doped region formation method further comprises a second annealing process after said second dopant ion implantation process to diffuse said second dopant ions to said offset sidewall bottom portion.
12. The method of forming a semiconductor structure as claimed in claim 10, wherein said initial lightly doped region portion further extends to said gate bottom, said initial lightly doped region forming method further comprising a second annealing process after said second dopant ion implantation process to diffuse said second dopant ions to said gate bottom.
13. The method of claim 10, wherein said source drain doped region further extends to a bottom of said main sidewall, said forming further comprising a first anneal process after said first dopant ion implantation process to diffuse said first dopant ions to a bottom of said main sidewall.
14. The method of forming a semiconductor structure of claim 10, further comprising implanting third dopant ions into said second epitaxial layer with said offset sidewall and said gate electrode as masks after forming said offset sidewall and before forming said main sidewall, said third dopant ions having an implantation depth greater than an implantation depth of said second dopant ions to form an initial halo region, and said initial halo region outside said source drain dopant region being a halo region.
15. The method of forming a semiconductor structure of claim 14, wherein the initial halo region is formed after the initial lightly doped region is formed.
16. The method of forming a semiconductor structure of claim 10, wherein the second epitaxial layer forming process comprises a selective epitaxial growth process.
17. The method for forming a semiconductor structure according to claim 10, wherein the method for forming a gate electrode comprises forming a gate electrode material layer on a surface of the substrate, forming a hard mask layer on a part of the surface of the gate electrode material layer, and etching the gate electrode material layer by using the hard mask layer as a mask to form the gate electrode.
18. The method of forming a semiconductor structure of claim 10, wherein the first epitaxial layer forming process comprises a selective epitaxial growth process.
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| CN202410425660.8A CN118281078B (en) | 2024-04-09 | Semiconductor structure and its formation method |
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| CN202410425660.8A CN118281078B (en) | 2024-04-09 | Semiconductor structure and its formation method |
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| CN118281078B true CN118281078B (en) | 2026-02-10 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465376A (en) * | 2013-09-17 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN105529360A (en) * | 2014-09-30 | 2016-04-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465376A (en) * | 2013-09-17 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN105529360A (en) * | 2014-09-30 | 2016-04-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
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