KR960000229B1 - Making method of vertical channel mosfet using trench structure - Google Patents

Abstract

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Description

Manufacturing Method of MOSFET with Vertical Channel Using Trench Structure

1 is a cross-sectional view of a conventional transistor having an LDD structure.

2 is a process diagram of manufacturing a trench transistor according to the present invention.

* Explanation of symbols for main parts of the drawings

1 semiconductor substrate 2 channel region

3: gate oxide film 3 ': gate electrode

4: low concentration impurity ion implantation region 5: high concentration impurity ion implantation region

6 spacer oxide film 7 buffer oxide film

8: trench 9: polysilicon film

10 oxide film 11: metal film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOSFET having a vertical channel using a trench structure applicable to semiconductor devices such as DRAM, SRAM, ROM, and the like.

In general, as the size of the device is miniaturized to realize high integration (64M, 256M, DRAM ...) of semiconductor products, short channel (Drain Induced Barrier Lowering) due to the reduction of the thickness and channel length of the gate oxide layer As a result, the punch-through characteristic is greatly deteriorated, and normal operation of the device becomes impossible. Therefore, the impurity ion implantation concentration of the channel has been increased.

Referring to FIG. 1, a semiconductor substrate, a channel region, a gate oxide film, a gate electrode 4, a low concentration impurity ion implantation region, and a high concentration impurity ion implantation are shown in FIG. Regions 6 denote spacer oxide films, respectively.

As shown in the drawing, the conventional MOS transistor is an LDD (Lightly Doped Drain) MOSFET structure, which forms a gate oxide film 3 on a semiconductor substrate 1 and is located below the gate oxide film 3. A high concentration of impurity ions are implanted into the semiconductor substrate 1 to control the threshold voltage to form the channel region 2. Subsequently, a gate electrode 3 'is formed on the gate oxide film 3, and a low concentration of impurities are implanted to form an ion implantation region 4 with low concentration of impurities. Finally, a high concentration impurity ion implantation region 5 has been formed by forming a spacer oxide film 6 on the sidewall of the gate electrode and then implanting a high concentration impurity.

However, in the conventional MOS transistor, carrier mobility decreases due to an increase in channel concentration. As a result, there is a problem in that the conductivity (Gm) and current characteristics of the channel are decreased, and the reliability of the device due to high energy electrons is deteriorated.

Accordingly, the present invention devised to solve the above problems provides a method of manufacturing a MOSFET having a vertical channel using a trench structure that can improve the performance of a transistor by forming a long channel of low concentration. The purpose is.

In order to achieve the above object, the present invention provides a first step of forming a channel region by forming a buffer oxide layer on a semiconductor substrate and implanting high concentration ions for controlling a threshold voltage, and high concentration for source and drain formation after the first step. A second step of forming an impurity ion implantation region, a third step of forming a trench by etching a predetermined portion of the semiconductor substrate after the second step, and after the third step, a gate oxide film and a polysilicon film are sequentially deposited to form the trench A fourth step of forming a gate electrode by selectively etching the polysilicon film except for the polysilicon of the portion is formed.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to FIG. 2. In the drawings, 2 is a channel region, 5 is a high concentration impurity ion implantation region, 7 is a buffer oxide layer, 8 is a trench, and 9 is a poly The silicon film, 10 is an oxide film, and 11 is a metal film, respectively.

First, the buffer oxide film 7 is formed on the semiconductor substrate 1 in order to compensate for the disadvantages of the conventional LDD MOSFET structure (FIG. 2 (a)).

In order to control the threshold voltage, a high concentration of ion implantation is performed to form the channel region 2 (FIG. 2B).

Subsequently, a high concentration impurity ion implantation region 5 is formed by implanting a high concentration impurity to form a source and a drain (FIG. 2C).

Subsequently, a portion of the semiconductor substrate 1 is etched to form a trench 8 (FIG. 2D).

After the trench 8 is formed, the gate oxide film 3 and the polysilicon film 9 are sequentially deposited (FIG. 2E).

Finally, except the polysilicon of the portion where the trench 8 is formed, the polysilicon film 9 is selectively etched to form a gate electrode 3 ', and then an oxide film 10 is deposited. The oxide film 10 is selectively etched to form contact holes to form source and drain contacts by depositing the metal film 11 (FIG. 2F).

The transistor of the present invention suppresses the threshold voltage and the punch-throw as the concentration and the length of the channel region implanted at a high concentration. Therefore, since the concentration in the channel region is low to the well concentration level of the substrate except near the ion implantation region, the mobility is decreased due to the increase of the channel concentration, the conductivity of the channel (Gm) and the current as in the conventional LDD structure. Can be prevented. In addition, since the channel is formed in the trench structure, the effective channel length is increased, so that the short channel effect and the punch-through characteristic are improved than the conventional structure. In addition, since the gate is formed after the source and drain impurity ions are implanted, the effect of the mask misalignment is reduced.

Claims (1)

In a method of manufacturing a MOSFET having a vertical channel using a trench structure, a buffer oxide layer 7 is formed on a semiconductor substrate 1 and ion implantation is performed to control a threshold voltage. Forming a high concentration impurity ion implantation region 5 by implanting a high concentration impurity to form a source and a drain after the first step, and after the second step of the semiconductor substrate 1 A third step of forming a trench 8 by etching a predetermined portion, and after the third step, the gate oxide film 3 and the polysilicon film 9 are sequentially deposited to deposit the poly at the site where the trench 8 is formed. And a fourth step of selectively etching the polysilicon layer 9 to form the gate electrode 3 ', except for silicon. The method's transistor (MOSFET).