CN103531627B - Semiconductor device and manufacture method thereof - Google Patents

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. After forming a groove by etching a semiconductor substrate in a source/drain area, a liner layer is formed by selective chemical vapor deposition and etched to form a liner layer on both side walls of the groove. Form a diffusion barrier layer whose conductivity type is the same as that of the semiconductor substrate and whose impurity concentration is higher than that of the semiconductor substrate, and continue to epitaxially form a source/drain region of the opposite conductivity type to the diffusion barrier layer in the groove. Therefore, due to the source/drain A diffusion barrier layer opposite to the conductivity type of the source/drain region is set between the electrode regions, which neutralizes the impurities laterally diffused from the source/drain region to the channel region, so that there is no need to increase the thickness of the side wall of the gate, reducing The volume of the entire device is reduced, and the series resistance between the source and the drain is reduced.

Description

Semiconductor device and manufacturing method thereof

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

Field-effect transistors (FETs) have long been the dominant semiconductor device used to manufacture ASIC chips, static random access memory (SRAM), and more. With the miniaturization of semiconductor devices, the short-channel effect of FET is becoming more and more serious. Affected by the short-channel effect, any slight impurity change in the channel will cause the threshold voltage (Vt) of the FET to shift, and impurities in the channel will appear. One of the reasons for the change is that after the source/drain region is formed by ion implantation, the dopant impurities in the source/drain region diffuse laterally to the channel region of the FET, which causes the shift of the threshold voltage of the FET, thereby affecting the performance of the FET.

In the existing FET manufacturing process, the source/drain region is generally formed after the gate spacer, and the gate and the offset spacer (offset spacer) on both sides and the gate spacer are used as shields to conduct ions on the semiconductor substrate. formed by injection. Based on this, in order to avoid the lateral diffusion of dopant impurities in the source/drain region to the channel region of the FET, in the prior art, the thickness of the sidewall of the gate is increased so that the gap between the source region and the drain region formed by ion implantation is distance increases. However, due to the increase of the thickness of the gate sidewall, the volume of the overall FET becomes larger, and because the distance between the source region and the drain region is extended, the series resistance between the source and drain will also increase, thereby affecting performance of the device.

Contents of the invention

In view of this, the present invention provides a semiconductor device and a manufacturing method thereof, so as to reduce the volume of the device and reduce the source-drain ratio while avoiding the lateral diffusion of doping impurities in the source/drain region to the channel region. series resistance between them.

The technical means adopted in the present invention are as follows: a method for manufacturing a semiconductor device, comprising:

A semiconductor structure to be formed with source/drain regions is provided, the semiconductor structure includes a semiconductor substrate with predefined positions of the source/drain regions, and a gate stack formed on the semiconductor substrate, and the semiconductor substrate an impurity having a first conductivity type;

Etching the semiconductor substrate at the position of the predefined source/drain region by dry etching to form a groove;

A liner layer having impurities of the first conductivity type is formed on the inner surface of the groove by selective chemical vapor deposition, and the concentration of the impurities of the first conductivity type in the liner layer is higher than that of the first conductivity type in the semiconductor substrate. concentration of impurities;

Dry etching the liner layer to remove the liner layer at the bottom of the groove to form a diffusion barrier layer on the sidewall of the groove;

A semiconductor layer doped with impurities of the second conductivity type is filled in the groove by chemical vapor deposition, and the semiconductor layer is used as a source/drain region.

Further, the semiconductor structure providing the source/drain region to be formed includes:

providing a semiconductor substrate with a first conductivity type impurity, the semiconductor substrate is predefined with a gate location and a source/drain region location;

sequentially forming an insulating layer, a polysilicon layer and a hard mask layer on the semiconductor substrate;

forming a patterned photoresist layer covering only the predefined gate positions on the hard mask layer, and etching and patterning the hard mask layer with the patterned photoresist layer;

Using the patterned hard mask layer as a shield, sequentially etching the polysilicon layer and insulating layer, forming a gate insulating layer and a gate on the semiconductor substrate;

depositing a first dielectric layer on the surface of the semiconductor substrate, and dry etching the first dielectric layer to form offset sidewalls on both sides of the gate insulating layer and the gate;

performing ion implantation on the semiconductor substrate by using the gate and the offset sidewall as a shield to form a lightly doped source/drain region;

Depositing a second dielectric layer on the surface of the semiconductor substrate, and dry etching the second dielectric layer to form gate sidewalls on the surface of the offset sidewalls.

Further, the first conductivity type is P-type conductivity, the second conductivity type is N-type conductivity, and the first conductivity type impurity is one or a combination of two or more of boron, indium or titanium; or ,

The first conductivity type is N-type conductivity, the second conductivity type is P-type conductivity, and the impurity of the first conductivity type is phosphorus or arsenic, or a combination of both.

The present invention also provides a semiconductor device, comprising: a semiconductor substrate containing impurities of the first conductivity type and a gate stack formed on the semiconductor substrate, characterized in that, in the semiconductor substrate on both sides of the gate stack A source/drain region with impurities of the second conductivity type is formed, and a diffusion barrier layer is formed on both sides of each source/drain region; the diffusion barrier layer has impurities of the first conductivity type and has a high impurity concentration Impurity concentration of the first conductivity type in the semiconductor substrate.

Further, the gate stack includes a gate dielectric layer formed on the semiconductor substrate, a gate located on the gate dielectric layer, offset sidewalls located on both sides of the gate dielectric layer and the gate, and offset sidewalls located on the offset sidewalls. Shift the gate sidewall of the sidewall surface;

The semiconductor substrate also includes a lightly doped source/drain region located in the semiconductor substrate on both sides of the gate, the offset sidewall and the bottom of the gate sidewall.

Further, the first conductivity type is P-type conductivity, the second conductivity type is N-type conductivity, and the first conductivity type impurity is one or a combination of two or more of boron, indium or titanium; or ,

The first conductivity type is N-type conductivity, the second conductivity type is P-type conductivity, and the impurity of the first conductivity type is phosphorus or arsenic, or a combination of both.

Using the semiconductor device and its manufacturing method provided by the present invention, after forming a groove by etching the semiconductor substrate in the source/drain region, a liner layer is formed by selective chemical vapor deposition and etched to form a The conductivity type is the same as that of the semiconductor substrate, and the impurity concentration is higher than that of the diffusion barrier layer of the semiconductor substrate, and the source/drain region of the conductivity type opposite to that of the diffusion barrier layer is continuously epitaxially formed in the groove. Therefore, because the source/drain A diffusion barrier layer opposite to the conductivity type of the source/drain region is set between the regions, which neutralizes the impurities laterally diffused from the source/drain region to the channel region, thereby eliminating the need to increase the thickness of the sidewall of the gate and reducing the The volume of the whole device is reduced, and the series resistance between source and drain is reduced.

Description of drawings

Fig. 1 is the flow chart of the manufacturing method of a kind of semiconductor device of the present invention;

2a to 2e are flow charts of a typical embodiment of a method for manufacturing a semiconductor device according to the present invention.

detailed description

The principles and features of the present invention are described below in conjunction with the accompanying drawings, and the examples given are only used to explain the present invention, and are not intended to limit the scope of the present invention.

As shown in Figure 1, the present invention provides a kind of manufacturing method of semiconductor device, comprises the following steps:

A semiconductor structure to be formed with source/drain regions is provided, the semiconductor structure includes a semiconductor substrate with predefined positions of the source/drain regions, and a gate stack formed on the semiconductor substrate, and the semiconductor substrate an impurity having a first conductivity type;

Etching the semiconductor substrate at the position of the predefined source/drain region by dry etching to form a groove;

A liner layer having impurities of the first conductivity type is formed on the inner surface of the groove by selective chemical vapor deposition, and the concentration of the impurities of the first conductivity type in the liner layer is higher than that of the first conductivity type in the semiconductor substrate. concentration of impurities;

Dry etching the liner layer to remove the liner layer at the bottom of the groove to form a diffusion barrier layer on the sidewall of the groove;

A semiconductor layer doped with impurities of the second conductivity type is filled in the groove by chemical vapor deposition, and the semiconductor layer is used as a source/drain region.

In order to further describe the features of the present invention in detail, as a typical embodiment of a method for manufacturing a semiconductor device of the present invention, it will be described in detail below in conjunction with accompanying drawings 2a-2e.

Referring to FIG. 2a, in this embodiment, firstly, the semiconductor structure to be formed with the source/drain region is manufactured using the prior art, and the steps include:

providing a semiconductor substrate 10 with impurities of the first conductivity type, where the semiconductor substrate 10 has predefined gate positions and source/drain region positions;

On the semiconductor substrate 10, an insulating layer 11, a polysilicon layer 12 and a hard mask layer 13 are sequentially formed, wherein the insulating layer 11 can be silicon oxide, silicon oxynitride, etc., and the hard mask layer 13 is preferably silicon nitride;

A patterned photoresist layer (not shown) covering only the predefined gate positions is formed on the hard mask layer 13, and the patterned hard mask layer 13 is etched with the patterned photoresist layer (in order to reflect the process The continuity of is still marked with the original mark, and other structures are the same);

Using the patterned hard mask layer 13 as a shield, sequentially etch the polysilicon layer 12 and the insulating layer 11 to form the gate insulating layer 11 and the gate 12 on the semiconductor substrate 10;

Deposit a first dielectric layer 14 on the surface of the semiconductor substrate 10, and dry etch the first dielectric layer 14 to form offset sidewalls 14 on both sides of the gate insulating layer 11 and the gate 12, wherein the material of the first dielectric layer 14 It can be silicon oxide, silicon oxynitride, etc.;

Ion implantation is performed on the semiconductor substrate 10 using the gate 12 and the offset sidewall 14 as a shield to form a lightly doped source/drain region 16;

Deposit a second dielectric layer 15 on the surface of the semiconductor substrate 10, and dry-etch the second dielectric layer 15 to form gate sidewalls 15 on the surface of the offset sidewalls 14, wherein the gate sidewalls 15 are preferably silicon nitride , a gate stack is formed by the gate dielectric layer 11, the gate 12, the offset sidewall 14 and the gate sidewall 15;

As shown in FIG. 2b, after the structure in FIG. 2a is obtained, using the gate stack as a shield, dry etching is used to etch the semiconductor substrate 10 at the predefined source/drain region to form a groove 17;

Referring to FIG. 2c, a liner layer 18 having a first conductivity type impurity is formed on the inner surface of the groove 17 by selective chemical vapor deposition, and the concentration of the first conductivity type impurity in the liner layer 18 is higher than that of the first conductivity type impurity in the semiconductor substrate 10. concentration of impurities;

As shown in Figure 2d, the liner layer 18 is dry etched to remove the liner layer at the bottom of the groove 17 to form a diffusion barrier layer 18' on the sidewall of the groove 17;

As shown in FIG. 2 e , the groove 17 is filled with a semiconductor layer 19 doped with impurities of the second conductivity type by chemical vapor deposition, and the semiconductor layer 19 is used as the source/drain region 19 .

Therefore, using the semiconductor device manufacturing method provided by the present invention, after forming the groove by etching the semiconductor substrate in the source/drain region, a liner layer is formed by selective chemical vapor deposition and etched to form a The conductivity type is the same as that of the semiconductor substrate, and the impurity concentration is higher than that of the diffusion barrier layer of the semiconductor substrate, and the source/drain region of the conductivity type opposite to that of the diffusion barrier layer is continuously epitaxially formed in the groove. Therefore, because the source/drain A diffusion barrier layer opposite to the conductivity type of the source/drain region is set between the regions, which neutralizes the impurities laterally diffused from the source/drain region to the channel region, thereby eliminating the need to increase the thickness of the sidewall of the gate and reducing the The volume of the whole device is reduced, and the series resistance between source and drain is reduced.

The present invention also provides a semiconductor device, as shown in FIG. 2e, including a semiconductor device, including: a semiconductor substrate 10 containing impurities of a first conductivity type and a gate stack formed on the semiconductor substrate 10;

Wherein, the gate stack includes a gate dielectric layer 11 formed on the semiconductor substrate 10, a gate 12 located on the gate dielectric layer 11, offset sidewalls 14 located on both sides of the gate dielectric layer 11 and the gate 12, and offset side walls 14 located on both sides of the gate dielectric layer 11 and the gate 12. The gate sidewall 15 on the surface of the sidewall 14;

Source/drain regions 19 having impurities of the second conductivity type are formed in the semiconductor substrate 10 on both sides of the gate stack, and a diffusion barrier layer 18' is formed on both sides of each source/drain region 19; the diffusion barrier The layer 18 ′ has impurities of the first conductivity type and the impurity concentration is higher than that of the semiconductor substrate 10 .

The semiconductor substrate 10 further includes a lightly doped source/drain region 16 located on both sides of the gate 12 , the offset sidewall 14 and the bottom of the gate sidewall 15 in the semiconductor substrate 10 .

It should be noted that, in the above-mentioned semiconductor device and its manufacturing method, when the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity, that is, when the semiconductor device is an NMOS transistor, the first conductivity type The impurity is one or a combination of two or more of boron, indium or titanium;

When the first conductivity type is N-type conductivity, the second conductivity type is P-type conductivity, that is, when the semiconductor device is a PMOS transistor, the impurity of the first conductivity type is phosphorus or arsenic, or a combination of both.

Further, for the selection of specific materials, numerical values, and process parameters such as etching, selective chemical vapor deposition, chemical vapor deposition, impurities, and impurity concentrations in the method, those skilled in the art can according to the specific semiconductor device type (such as NMOS or PMOS), size and other factors, select suitable materials and process parameters based on existing technologies and common knowledge, so no limitation is made here.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the present invention. within the scope of protection.

Claims (6)

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor structure to be formed with a source/drain region, wherein the semiconductor structure comprises a semiconductor substrate with a predefined position of the source/drain region and a gate stack formed on the semiconductor substrate, and the semiconductor substrate is provided with impurities of a first conduction type;

etching the semiconductor substrate at the predefined source/drain region position by using dry etching to form a groove;

forming a liner layer with first conductive type impurities on the inner surface of the groove by utilizing selective chemical vapor deposition, wherein the concentration of the first conductive type impurities in the liner layer is higher than that of the first conductive type impurities in the semiconductor substrate;

dry etching the liner layer, and removing the liner layer at the bottom and the top of the side face of the groove to form a diffusion barrier layer on the side wall of the groove;

and filling the groove with a semiconductor layer doped with second conductive type impurities by using chemical vapor deposition, and taking the semiconductor layer as a source/drain region.

2. The method of claim 1, wherein providing a semiconductor structure in which source/drain regions are to be formed comprises:

providing a semiconductor substrate with first conductive type impurities, wherein the semiconductor substrate is predefined with a grid electrode position and a source/drain electrode region position;

sequentially forming an insulating layer, a polycrystalline silicon layer and a hard mask layer on the semiconductor substrate;

forming a patterned photoresist layer only covering the predefined gate position on the hard mask layer, and etching and patterning the hard mask layer by using the patterned photoresist layer;

taking the patterned hard mask layer as a shield, sequentially etching the polycrystalline silicon layer and the insulating layer, and forming a gate insulating layer and a gate on the semiconductor substrate;

depositing a first dielectric layer on the surface of the semiconductor substrate, and etching the first dielectric layer by a dry method to form offset side walls on the two sides of the gate insulating layer and the grid;

carrying out ion implantation on the semiconductor substrate by taking the grid and the offset side wall as a shield to form a lightly doped source/drain region;

and depositing a second dielectric layer on the surface of the semiconductor substrate, and etching the second dielectric layer by a dry method to form a grid side wall on the surface of the offset side wall.

3. The method of claim 1 or 2, wherein the first conductivity type is P-type conductivity, the second conductivity type is N-type conductivity, and the first conductivity type impurity is a combination of one or more of boron, indium, or titanium; or,

the first conductivity type is N-type conductivity, the second conductivity type is P-type conductivity, and the first conductivity type impurity is phosphorus or arsenic, or a combination of the two.

4. A semiconductor device, comprising: the semiconductor device comprises a semiconductor substrate containing first conduction type impurities and a gate stack formed on the semiconductor substrate, and is characterized in that source/drain regions containing second conduction type impurities are formed in the semiconductor substrate on two sides of the gate stack, and diffusion barrier layers are formed on two sides of each source/drain region; the diffusion barrier layer has a first conductive type impurity and an impurity concentration higher than that of the semiconductor substrate;

the forming of the diffusion barrier layer is as follows:

etching the semiconductor substrate at the predefined source/drain region position by using dry etching to form a groove;

forming a liner layer with first conductive type impurities on the inner surface of the groove by utilizing selective chemical vapor deposition;

and dry etching the liner layer, and removing the liner layer at the bottom and the top of the side face of the groove to form a diffusion barrier layer on the side wall of the groove.

5. The semiconductor device according to claim 4, wherein the gate stack comprises a gate dielectric layer formed on a semiconductor substrate, a gate electrode located on the gate dielectric layer, offset sidewalls located on two sides of the gate dielectric layer and the gate electrode, and a gate sidewall located on a surface of the offset sidewall;

the semiconductor substrate further comprises lightly doped source/drain regions located on two sides of the gate, in the offset side wall and in the semiconductor substrate at the bottom of the gate side wall.

6. The semiconductor device according to claim 4 or 5, wherein the first conductivity type is a P-type conductivity, the second conductivity type is an N-type conductivity, and the first conductivity type impurity is one or a combination of boron, indium, or titanium; or,

the first conductivity type is N-type conductivity, the second conductivity type is P-type conductivity, and the first conductivity type impurity is phosphorus or arsenic, or a combination of the two.