CN107731890A - Fin formula field effect transistor and forming method thereof - Google Patents

Abstract

A fin field effect transistor and its forming method, the forming method comprising: providing a semiconductor substrate, on which a raised first fin and a second fin are formed, and a P is formed in the first fin type well region, an N-type well region is formed in the second fin, a first trench is formed between the first fin and the second fin, and the first trench exposes the sides of the first fin and the second fin The wall, the side of the first fin portion away from the first groove has a second groove, and the side of the second fin portion away from the first groove has a third groove; the first groove and the second groove are exposed The first doped region is formed on the sidewall surface of the first fin; the second doped region is formed on the sidewall surface of the second fin exposed by the first trench and the third trench; the first doped region is formed After the second doped region and the first trench, the second trench and the third trench are filled with isolation material to form a shallow trench isolation structure. The transistor formed by the method of the invention prevents the generation of leakage current and the generation of short channel effect.

Description

Fin field effect transistor and method of forming the same

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a fin field effect transistor and a forming method thereof.

Background technique

With the continuous development of semiconductor process technology, process nodes are gradually reduced, and gate-last (gate-last) process has been widely used to obtain an ideal threshold voltage and improve device performance. However, when the feature size (CD, Critical Dimension) of the device is further reduced, even if the gate-last process is adopted, the structure of the conventional MOS field effect transistor can no longer meet the requirements for device performance, and the fin field effect transistor (Fin FET) as a conventional Device substitution has received extensive attention.

A fin field effect transistor in the prior art includes: a semiconductor substrate on which protruding fins are formed, and the fins are generally obtained by etching the semiconductor substrate; an isolation layer, Covering the surface of the semiconductor substrate and a part of the sidewall of the fin; the gate structure straddles the fin and covers the top and sidewall of the fin, the gate structure includes a gate dielectric layer and A gate electrode on the gate dielectric layer; a source region and a drain region located on both sides of the gate structure.

In order to improve the performance of the fin field effect transistor, stress is usually introduced into the channel region of the fin field effect transistor to improve the mobility of carriers in the channel region of the fin field effect transistor, specifically, in the p-type fin field effect transistor The source region and drain region of the field effect transistor are formed of silicon germanium material, and the source region and drain region of the N-type fin field effect transistor are formed of carbon silicon material.

However, the performance of the fin field effect transistor formed by the prior art still needs to be improved.

Contents of the invention

The problem solved by the invention is how to improve the performance of the transistor.

In order to solve the above problems, the present invention provides a method for forming a fin field effect transistor, comprising:

A semiconductor substrate is provided, a raised first fin and a second fin are formed on the semiconductor substrate, a P-type well region is formed in the first fin, and an N-type well is formed in the second fin region, there is a first groove between the first fin and the second fin, the first groove exposes the sidewalls of the first fin and the second fin, and the first fin is far away from the first groove There is a second groove on one side of the second fin, and a third groove on the side of the second fin away from the first groove; a first groove is formed on the side wall surface of the first fin exposed in the first groove and the second groove. Doped region, the first doped region is used to prevent impurity ions in the P-type well region from diffusing into the subsequently formed shallow trench isolation structure; the second fin exposed in the first trench and the third trench The second doped region is formed on the sidewall surface of the fin, and the second doped region is used to prevent the impurity ions in the source and drain regions formed in the N-type well region from moving from the sidewall of the second fin to the channel region. Diffusion and diffusion into the subsequently formed shallow trench isolation structure; after the first doped region and the second doped region are formed, the isolation material is filled in the first trench, the second trench and the third trench to form shallow trench isolation structure.

Optionally, the first doped region is a carbon doped region, and the second doped region is a fluorine doped region.

Optionally, the carbon-doped region has a depth of 2nm-12nm, and the concentration of carbon ions in the carbon-doped region is 5e18-5e19atom/cm ³ .

Optionally, the formation process of the carbon-doped region is: using the first ion implantation process, doping carbon ions in the surface material of the sidewall of the first fin exposed in the first trench and the second trench, A carbon doped region is formed.

Optionally, the implantation angle of the first ion implantation process is 5-25 degrees, the implantation energy is 2-8KeV, and the implantation dose is 5e13-5e14atom/cm ² .

Optionally, the depth of the fluorine-doped region is 2nm-12nm, and the concentration of fluorine ions in the fluorine-doped region is 5e18-1e20atom/cm ³ .

Optionally, the formation process of the fluorine-doped region is: using the second ion implantation process, doping fluorine ions in the surface material of the sidewall of the second fin exposed in the first trench and the third trench, A fluorine-doped region is formed.

Optionally, the implantation angle of the second ion implantation process is 5-25 degrees, the implantation energy is 4-12 KeV, and the implantation dose is 1e14-1e15 atom/cm ² .

Optionally, the formation process of the carbon-doped region is: forming a first semiconductor epitaxial layer containing carbon ions on the sidewall surfaces of the first fin exposed in the first trench and the second trench, The first semiconductor epitaxial layer serves as a carbon doped region.

Optionally, the first semiconductor epitaxial layer is used as a part of the first fin, the material of the first semiconductor epitaxial layer is silicon or silicon carbide, and the shallow trench isolation structure covers the surface of the first semiconductor epitaxial layer.

Optionally, the formation process of the fluorine-doped region is: forming a second semiconductor epitaxial layer containing fluorine ions on the sidewall surfaces of the second fin exposed in the first trench and the third trench, The second semiconductor epitaxial layer serves as a fluorine-doped region.

Optionally, the second semiconductor epitaxial layer is used as a part of the second fin, the material of the second semiconductor epitaxial layer is silicon or silicon germanium, and the shallow trench isolation structure covers the surface of the second semiconductor epitaxial layer .

Optionally, the formation process of the carbon-doped region is: forming a first intermediate layer containing carbon ions on the sidewall surfaces of the first fin exposed in the first trench and the second trench, by The activation process makes the carbon ions in the first intermediate layer diffuse to the sidewall surface of the first fin, forming a carbon doped region on the sidewall surface of the first fin.

Optionally, the formation process of the fluorine-doped region is: forming a second intermediate layer containing fluorine ions on the sidewall surfaces of the second fin exposed in the first trench and the third trench, by The activation process makes the fluorine ions in the second intermediate layer diffuse to the sidewall surface of the second fin, forming a fluorine doped region on the sidewall surface of the second fin.

Optionally, further comprising: etching back to remove part of the shallow trench structure, exposing part of the sidewalls of the first fin and the second fin.

Optionally, a first gate structure is formed across part of the top and sidewall surfaces of the first fin; a second gate structure is formed across part of the top and sidewall surfaces of the second fin.

Optionally, a first source-drain region is formed in the first fins on both sides of the first gate structure; a second source-drain region is formed in the second fins on both sides of the second gate structure.

Optionally, the doping type of the first source and drain region is N type, and the doping type of the second source and drain region is P type.

The present invention also provides a fin field effect transistor, comprising:

A semiconductor substrate, a protruding first fin and a second fin are formed on the semiconductor substrate, a P-type well region is formed in the first fin, and an N-type well region is formed in the second fin , there is a first groove between the first fin and the second fin, the first groove exposes the sidewalls of the first fin and the second fin, the first fin is far away from the first groove One side has a second groove, and the side of the second fin away from the second groove has a third groove; the first groove on the side wall surface of the first fin exposed in the first groove and the second groove A doping region, the first doping region is used to prevent impurity ions in the P-type well region from diffusing into the shallow trench isolation structure; located on the side of the second fin exposed in the first trench and the third trench A second doped region on the wall surface, the second doped region is used to prevent impurity ions in the source and drain regions formed in the N-type well region from diffusing to the channel region along the sidewall of the second fin and to the channel region. Diffusion in the shallow trench isolation structure; the shallow trench isolation structure filling the first trench, the second trench and the third trench.

Optionally, the first doped region is a carbon doped region, and the second doped region is a fluorine doped region.

Optionally, the carbon-doped region has a depth of 2nm-12nm, and the concentration of carbon ions in the carbon-doped region is 5e18-5e19atom/cm ³ .

Optionally, the depth of the fluorine-doped region is 2nm-12nm, and the concentration of fluorine ions in the fluorine-doped region is 5e18-1e20atom/cm ³ .

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the method for forming a Fin Field Effect Transistor of the present invention, after forming the first fin with the P-type well region and the second fin with the N-type well region on the semiconductor substrate, the first trench and the second trench The exposed sidewall surface of the first fin forms a first doped region; the exposed sidewall surface of the second fin in the first trench and the third trench forms a second doped region; After the region and the second doped region, an isolation material is filled in the first trench, the second trench and the third trench to form a shallow trench isolation structure. The first doped region can prevent impurity ions (especially boron ions or boron fluoride ions) in the P-type well region of the first fin from separating from the shallow trench formed between the first fin and the second fin. Diffusion in the structure ensures the isolation performance of the shallow trench isolation structure, thereby preventing the generation of leakage current between the first fin and the second fin; the second doped region can prevent impurity ions in the P-type source and drain regions (such as boron ions) diffuse to the channel region along the sidewall of the second fin, thereby preventing the generation of the short channel effect, and preventing impurity ions in the subsequent P-type source and drain regions formed in the second fin (such as boron ions) diffuse into the shallow trench isolation structure formed between the second fin and the first fin to ensure the isolation performance of the shallow trench isolation structure, thereby preventing leakage between the first fin and the second fin current generation. And the method of the present invention realizes the integrated fabrication of N-type and P-type fin field effect transistors.

Further, the first doped region is a carbon doped region, and the carbon doped region can not only prevent impurity ions (especially boron ions or boron fluoride ions) in the P-type well region of the first fin from flowing into the first fin. Diffusion in the shallow trench isolation structure formed between the second fin and the second fin ensures the isolation performance of the shallow trench isolation structure, thereby preventing the generation of leakage current between the first fin and the second fin, and the carbon doped region is opposite to (N-type FinFET) The electrical performance of the first fin is less affected.

Further, the second doped region is a fluorine-doped region, and the fluorine-doped region can not only prevent impurity ions (such as boron ions) in the P-type source and drain regions from moving to the channel region along the sidewall of the second fin. Diffusion, thereby preventing the generation of the short channel effect, and preventing impurity ions (such as boron ions) in the P-type source and drain regions subsequently formed in the second fin from forming between the second fin and the first fin Diffusion in the shallow trench isolation structure ensures the isolation performance of the shallow trench isolation structure, thereby preventing the leakage current between the first fin and the second fin, and the fluorine-doped region is opposite to (P-type fin field effect Transistor) has less influence on the electrical performance of the second fin.

The Fin Field Effect Transistor of the present invention comprises a first doped region and a second doped region, the first doped region can prevent impurity ions (especially boron ions or fluorine) in the P-type well region of the first fin Boron oxide ions) diffuse into the shallow trench isolation structure formed between the first fin and the second fin to ensure the isolation performance of the shallow trench isolation structure, thereby preventing leakage current between the first fin and the second fin The generation of; The second doped region can prevent impurity ions (such as boron ions) in the P-type source and drain regions from diffusing to the channel region along the sidewall of the second fin, thereby preventing the generation of the short channel effect , and prevent impurity ions (such as boron ions) in the P-type source and drain regions subsequently formed in the second fin from diffusing into the shallow trench isolation structure formed between the second fin and the first fin, ensuring The shallow trench isolation structure isolates performance, thereby preventing the generation of leakage current between the first fin and the second fin.

Description of drawings

1 to 6 are structural schematic diagrams of a method for forming a fin field effect transistor according to an embodiment of the present invention;

7 to 9 are structural schematic diagrams of the process of a fin field effect transistor according to another embodiment of the present invention;

10-12 are schematic cross-sectional structure diagrams of the formation process of the fin field effect transistor in another embodiment of the present invention.

detailed description

As mentioned in the background art, the performance of the fin field effect transistor formed in the prior art still needs to be improved, for example, the fin field effect transistor formed in the prior art still has the problem of leakage current.

Research has found that in the prior art, when fin field effect transistors are manufactured, impurity ions are doped in the fins to form well regions or impurity ions are doped in fins to form source and drain regions, and the adjacent fins are separated by lightly doped isolation structures. Isolation, because the impurity ions doped in the fins will diffuse into the shallow trench isolation structure, so that the isolation performance of the shallow trench isolation structure is reduced, and leakage current is easily generated between adjacent fins.

Further studies have found that boron ions and boron fluoride ions are more likely to diffuse into the shallow trench structure between adjacent fins than other impurity ions, so the well region of the N-type fin field effect transistor and the P The boron ions and boron fluoride ions doped in the source and drain regions of the fin field effect transistor of the type contribute greatly to the leakage current caused by the degradation of the isolation performance of the shallow trench isolation structure.

To this end, the present invention provides a fin field effect transistor and its forming method. In the forming method of the present invention, a first fin having a P-type well region and a second fin having an N-type well region are formed on a semiconductor substrate. After finning, the first doped region is formed on the sidewall surface of the first fin exposed in the first trench and the second trench; the sidewall of the second fin exposed in the first trench and the third trench A second doped region is formed on the surface; after the first doped region and the second doped region are formed, isolation materials are filled in the first trench, the second trench and the third trench to form a shallow trench isolation structure. The first doped region can prevent impurity ions (especially boron ions or boron fluoride ions) in the P-type well region of the first fin from separating from the shallow trench formed between the first fin and the second fin. Diffusion in the structure ensures the isolation performance of the shallow trench isolation structure, thereby preventing the generation of leakage current between the first fin and the second fin; the second doped region can prevent impurity ions in the P-type source and drain regions (such as boron ions) diffuse to the channel region along the sidewall of the second fin, thereby preventing the generation of the short channel effect, and preventing impurity ions in the subsequent P-type source and drain regions formed in the second fin (such as boron ions) diffuse into the shallow trench isolation structure formed between the second fin and the first fin to ensure the isolation performance of the shallow trench isolation structure, thereby preventing leakage between the first fin and the second fin current generation.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present invention in detail, for convenience of explanation, the schematic diagrams will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which shall not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

1 to 6 are structural schematic diagrams of a method for forming a fin field effect transistor according to an embodiment of the present invention.

1 and 2, a semiconductor substrate 200 is provided, on which a raised first fin 202 and a second fin 203 are formed, and a P-type fin 202 is formed in the first fin 202. Well region, an N-type well region is formed in the second fin portion 203, a first trench 211 is formed between the first fin portion 202 and the second fin portion 203, and the first trench 211 exposes the first fin portion 202 and the sidewall of the second fin portion 203, the side of the first fin portion 202 away from the first groove 211 has a second groove 212, and the side of the second fin portion 203 away from the first groove 211 has a third groove Slot 213.

The semiconductor substrate 200 may be silicon or silicon-on-insulator (SOI), and the semiconductor substrate 200 may also be germanium, silicon-germanium, gallium arsenide, or germanium-on-insulator. The material of the semiconductor substrate 200 in this implementation for silicon.

In this embodiment, the formation process of the first fin portion 202 and the second fin portion 203 is: forming a patterned hard mask layer 201 on the semiconductor substrate 200, and the patterned hard mask layer 201 is formed with Several openings exposing the surface of the semiconductor substrate; the semiconductor substrate 200 is etched along the openings to form first fins 202 and second fins 203 . In this embodiment, one first fin 202 and one adjacent second fin 203 are taken as an example for illustration. In other embodiments, several (≥2) first fins 200 are formed on the semiconductor substrate 200. The fin 202 and several (≥2) second fins 203 , at least one first fin 202 is adjacent to the second fin 203 .

The material of the mask layer 201 is silicon oxide, silicon nitride or other suitable mask materials, and the mask layer 201 may be a single-layer or multi-layer (≥2 layers) stacked structure.

The first fin portion 202 is doped with P-type impurity ions to form a P-type well region, and the second fin portion 203 is doped with N-type impurity ions to form an N-type well region. In an embodiment, after the formation of the first fin 202 and the second fin 203 , ion implantation processes are performed on the first fin 202 and the second fin 203 respectively, and a P-type fin is formed in the first fin 202 . Well region, an N-type well region is formed in the second fin portion 203 . In other embodiments, before the first fin 202 and the second fin 203 are formed, P-type impurity ions can be doped in the semiconductor substrate corresponding to the position of the first fin to be subsequently formed, and corresponding to the position of the second fin to be subsequently formed. N-type impurity ions are doped at the position of the portion; after doping, the semiconductor substrate is etched to form the first fin portion 202 and the second fin portion 203 at corresponding positions.

The P-type impurity ions are one or more of boron ions, boron fluoride ions, gallium ions or indium ions; the N-type impurity ions are one or more of phosphorus ions, arsenic ions or antimony ions .

In this embodiment, the impurity ions doped in the P-type well region of the first fin 202 are boron ions or boron fluoride ions, and the impurity ions doped in the N-type well region of the second fin 203 are phosphorus ion.

In other embodiments, the first fin 202 and the second fin 203 may be formed by an epitaxial process, and the first fin and the second fin are doped by a self-doping process during the epitaxial process.

Referring to FIG. 3, a first doped region 205 is formed on the sidewall surface of the first fin 202 exposed by the first trench 211 and the second trench 212, and the first doped region 205 is used to prevent the P-type well region from The impurity ions in the diffusion diffuse into the subsequently formed shallow trench isolation structure.

In this embodiment, the first doped region 205 is a carbon doped region (205).

The formed carbon-doped region 205 is located near the sidewall surface of the first fin, and the carbon-doped region 205 is doped with carbon ions, and the carbon-doped region is used to prevent impurities in the P-type well region of the first fin 202 Ions (especially boron ions or boron fluoride ions) diffuse into the subsequent shallow trench isolation structure formed between the first fin 202 and the second fin 203 to ensure the isolation performance of the shallow trench isolation structure and prevent the first fin generation of leakage current between the first fin portion 202 and the second fin portion 203, and the carbon doped region 205 has little influence on the electrical performance of the first fin portion 202 (N-type fin field effect transistor).

In one embodiment, the carbon-doped region 205 has a depth of 2nm-12nm, and the concentration of carbon ions in the carbon-doped region 205 is 5e18-5e19atom/cm ³ , so as to minimize the impact on the first fin 201 While affecting the electrical performance, effectively prevent impurity ions (especially boron ions or boron fluoride ions) in the P-type well region of the first fin 202 from forming between the subsequent first fin 202 and second fin 203 Diffusion in the shallow trench isolation structure.

The formation process of the carbon doped region 205 is: using the first ion implantation process 21, doping carbon ions in the surface material of the sidewall of the first fin 202 exposed by the first trench 211 and the second trench 212 , forming a carbon doped region 205 .

In one embodiment, the implantation angle of the first ion implantation process 21 is 5-25 degrees, the implantation energy is 2-8KeV, and the implantation dose is 5e13-5e14atom/cm ² , so that the formed carbon-doped region 205 is close to the surface of the first fin, and the carbon ions in the formed carbon doped region 205 can be more uniformly distributed and the concentration of carbon ions can meet the requirements, so that the formed carbon doped region 205 prevents the first fin from The effect of impurity ions (especially boron ions or boron fluoride ions) in the P-type well region of 202 diffusing into the subsequent shallow trench isolation structure formed between the first fin 202 and the second fin 203 is better.

It should be noted that before the first ion implantation process 21 is performed, a mask layer is formed on the surface of the second fin 203 and other surfaces of the semiconductor substrate that do not need to be implanted with impurity ions.

Referring to FIG. 4, a second doped region 206 is formed on the sidewall surface of the second fin 203 exposed by the first trench 211 and the third trench 213, and the second doped region 206 is used to prevent subsequent N-type The impurity ions in the source-drain region (second source-drain region) formed in the well region diffuse to the channel region along the sidewall of the second fin and diffuse into the subsequently formed shallow trench isolation structure.

In this embodiment, the second doped region 206 is a fluorine doped region (206).

The fluorine-doped region 206 is doped with fluorine ions, and the fluorine-doped region 206 is located near the sidewall surface of the second fin portion 203. The function of the fluorine-doped region 206 is to prevent P-type source and drain regions Impurity ions (such as boron ions) diffuse to the channel region along the sidewall of the second fin to prevent the short channel effect from occurring, and prevent the P-type source and drain regions subsequently formed in the second fin 203 Impurity ions (such as boron ions) diffuse into the shallow trench isolation structure formed between the second fin and the first fin to ensure the isolation performance of the shallow trench isolation structure and prevent the first fin 202 and the second fin 203 from generation of leakage current, and the fluorine-doped region 206 has little influence on the electrical properties of the second fin portion 203 (P-type fin field effect transistor).

In one embodiment, the depth of the fluorine-doped region 206 is 2nm-12nm, and the concentration of fluorine ions in the fluorine-doped region 206 is 5e18-1e20atom/cm ³ . Field Effect Transistor) While the impact on the electrical properties of the second fin portion 203 is small, it can effectively prevent the impurity ions (such as boron ions) in the P-type source and drain regions from moving to the channel region along the sidewall of the second fin portion. Diffusion, prevent the short channel effect, and effectively prevent impurity ions (such as boron ions) in the P-type source and drain regions formed in the second fin 203 from moving between the second fin and the first fin Diffusion in the shallow trench isolation structure formed between them.

The formation process of the fluorine-doped region 206 is: using the second ion implantation process 22, doping fluorine ions in the surface material of the sidewall of the second fin 203 exposed by the first trench 211 and the third trench 213 , forming a fluorine-doped region 206 .

In one embodiment, the implantation angle of the second ion implantation process 22 is 5-25 degrees, the implantation energy is 4-12 KeV, and the implantation dose is 1e14-1e15 atom/cm ² , so that the formed fluorine-doped region 206 is close to the surface of the second fin, and the fluorine ions in the formed fluorine-doped region 206 can be more uniformly distributed and the concentration of fluorine ions can meet the requirements, so that the formed fluorine-doped region 206 prevents the P-type source The impurity ions (such as boron ions) in the drain region diffuse to the channel region along the sidewall of the second fin, preventing the generation of the short channel effect, and effectively preventing the subsequent P-type formation in the second fin 203. The effect of impurity ions (such as boron ions) in the source and drain regions of the diffusion into the shallow trench isolation structure formed between the second fin and the first fin is better.

It should be noted that before the second ion implantation process 22 is performed, a mask layer is formed on the surface of the first fin 202 and other surfaces of the semiconductor substrate that do not need to be implanted with impurity ions.

In this embodiment, the step of forming the fluorine-doped region 206 is performed after the step of forming the carbon-doped region 205. In other embodiments, the step of forming the fluorine-doped region 206 can also be performed in the carbon-doped region 205 is performed before the forming step.

Referring to FIG. 5 , an isolation material is filled in the first trench 211 (see FIG. 4 ), the second trench 212 (see FIG. 4 ) and the third trench 213 (see FIG. 4 ), forming a shallow trench isolation structure 207 .

The formation process of the shallow trench isolation structure 207 is: forming a surface covering the first fin portion 202, the second fin portion 203, and the hard mask layer 201 (refer to FIG. 4 ) and filling the surface of the first trench 211 ( 4), the isolation material layer of the second trench 212 (refer to FIG. 4) and the third trench 213 (refer to FIG. 4); planarize the isolation material layer to form the first fin 202 and the second fin The top surface of portion 203 is a stop layer, and shallow trench isolation structures 207 are formed in first trench 211 (refer to FIG. 4 ), second trench 212 (refer to FIG. 4 ), and third trench 213 (refer to FIG. 4 ). .

The material of the shallow trench isolation structure 207 is silicon oxide, silicon nitride, silicon oxynitride. In this embodiment, the material of the shallow trench isolation structure 207 is silicon oxide.

The shallow trench isolation structure 207 can be a single-layer or multi-layer (≥2 layers) stacked structure. In one embodiment, the shallow trench isolation structure is a double-layer stack structure, including a liner layer and The filling layer on the surface of the liner layer fills the first trench 211 (the second trench 212 and the third trench 213 ). The materials of the pad layer and the filling layer can be the same or the same.

Referring to FIG. 6 , etch back to remove part of the thickness of the shallow trench structure 207 , exposing part of the sidewalls of the first fin 202 and the second fin 203 .

Etching back to remove part of the thickness of the shallow trench structure 207 adopts a wet etching process. After etching back, the surface of the remaining shallow trench isolation structure 207 is lower than the top surfaces of the first fin 202 and the second fin 203 .

After performing the etch-back step, it also includes: forming a first gate structure (not shown in the figure) across the top and sidewall surfaces of the first fin portion 202; forming a top portion across the second fin portion 203 and a second gate structure (not shown in the figure) on the sidewall surface; a first source and drain region (not shown in the figure) is formed in the first fin portion 202 on both sides of the first gate structure; Second source and drain regions (not shown in the figure) are formed in the second fins 203 on both sides of the gate structure.

The first gate structure includes a first gate dielectric layer and a first gate electrode on the first gate dielectric layer, and the second gate structure includes a second gate dielectric layer and a second gate electrode on the second gate dielectric layer.

In an embodiment, the material of the first gate dielectric layer and the second gate dielectric layer is silicon oxide, and the material of the first gate electrode layer and the second gate electrode layer is polysilicon. In another embodiment, the material of the first gate dielectric layer and the second gate dielectric layer is a high-K dielectric constant material, and the material of the high-K gate dielectric layer can be HfO ₂ , TiO ₂ , HfZrO, HfSiNO , Ta ₂ O ₅ , ZrO ₂ , ZrSiO ₂ , Al ₂ O ₃ , SrTiO ₃ or BaSrTiO, the material of the corresponding first gate electrode layer and the second gate electrode layer is metal, and the metal can be W, Al , Cu, Ti, Ag, Au, Pt, Ni or one or more.

The doping type of the first source and drain region is N type, and the doping type of the second source and drain region is P type. The first source and drain regions and the second source and drain regions are formed by an ion implantation process. The P-type impurity ions doped in the second source-drain region are one or more of boron ions, boron fluoride ions, gallium ions, or indium ions; the N-type impurity ions doped in the first source-drain region It is one or more of phosphorus ions, arsenic ions or antimony ions.

The embodiment of the present invention also provides a fin field effect transistor, please refer to FIG. 5 , including:

A semiconductor substrate 200, on which a raised first fin 202 and a second fin 203 are formed, a P-type well region is formed in the first fin 202, and a p-type well region is formed in the second fin 201 An N-type well region is formed, and there is a first trench between the first fin 202 and the second fin 203, and the first trench exposes the sidewalls of the first fin 202 and the second fin 203, the second A side of a fin 202 away from the first groove has a second groove, and a side of the second fin 203 away from the second groove has a third groove;

The first doped region 205 located on the sidewall surface of the first fin 202 exposed in the first trench and the second trench, the first doped region 205 is used to prevent impurity ions in the P-type well region from Diffusion in shallow trench isolation structures;

The second doped region 206 located on the sidewall surface of the second fin 203 exposed in the first trench and the third trench, the second doped region 206 is used to prevent the source formed in the N-type well region The impurity ions in the drain region diffuse to the channel region along the sidewall of the second fin and diffuse into the shallow trench isolation structure;

The shallow trench isolation structure 207 filling the first trench, the second trench and the third trench.

The first doped region 205 is a carbon doped region (205), and the second doped region 206 is a fluorine doped region (206).

In one embodiment, the depth of the carbon-doped region 205 is 2nm-12nm, the concentration of carbon ions in the carbon-doped region is 5e18-5e19atom/cm ³ ; the depth of the fluorine-doped region 206 is 2nm-12nm, The concentration of fluorine ions in the fluorine-doped region is 5e18˜1e20atom/cm ³ .

It should be noted that, for other definitions and descriptions of the FinFET in this embodiment, please refer to the relevant definitions and descriptions in the forming process of the FinFET in the foregoing embodiments.

7 to 9 are structural schematic diagrams of the process of the fin field effect transistor according to another embodiment of the present invention.

The difference between this embodiment and the previous embodiments is that the formation process of the first doped region (carbon doped region) and the second doped region (fluorine doped region) are different. region (carbon doped region) and the second doped region (fluorine doped region) before the process and the formation of the first doped region (carbon doped region) and the second doped region (fluorine doped region) after For the specific definition and description of the process, please refer to the specific definition and description of relevant parts in the foregoing embodiments, and details will not be repeated in this embodiment. FIG. 7 is carried out on the basis of the aforementioned FIG. 2 .

Referring to FIG. 7, a first doped region (carbon doped region) 301 is formed on the sidewall surface of the first fin portion 202. The formation process of the first doped region (carbon doped region) 301 is as follows: A first semiconductor epitaxial layer 301 containing carbon ions is formed on the sidewall surface of the first fin exposed by the first trench 211 and the second trench 212, and the first semiconductor epitaxial layer 301 serves as a carbon doped region or a second a doped region.

The formation process of the first semiconductor epitaxial layer 301 is a (self-doping) selective epitaxial process, and the material of the first semiconductor epitaxial layer 301 is silicon or silicon carbide. Due to the special structure of the first fin portion 202 and the second fin portion 203, it is difficult to control the process when the ion implantation process forms the first doped region (carbon doped region), and it is easier to adopt (self-doping) selective epitaxy The first semiconductor epitaxial layer 301 is formed, and the first semiconductor epitaxial layer 301 formed by this method can maintain better thickness uniformity and distribution uniformity of impurity ion concentration, so that the first semiconductor epitaxial layer 301 (first doped impurity region or carbon doped region) to prevent impurity ions (especially boron ions or boron fluoride ions) in the P-type well region of the first fin 202 from forming between the subsequent first fin 202 and second fin 203 Diffusion works better in shallow trench isolation structures.

Before forming the first semiconductor epitaxial layer 301, other regions (the second fin 203 and part of the semiconductor substrate 200) other than the sidewall of the first fin 202 are covered with a mask layer, and the mask layer only exposes the first fin 202. On the sidewall of the first fin 202, the first semiconductor epitaxial layer 301 is formed on the sidewall of the first fin 202 by a selective epitaxial process. During the selective epitaxial process, carbon ions are self-doped in the first semiconductor epitaxial layer.

In this embodiment, the material of the first semiconductor epitaxial layer 301 is silicon or silicon carbide, and the first semiconductor epitaxial layer 301 may serve as a part of the first fin.

In a specific embodiment, when the material of the first semiconductor epitaxial layer 301 is silicon, the (self-doping) selective epitaxy process is as follows: the temperature is 650-800 degrees Celsius, the pressure is 6-10torr, and the silicon source gas is SiH ₄ Or SiCl ₂ H ₄ , the flow rate of silicon source gas is 40-150 sccm, the selective gas is HCl, the flow rate of selective gas is 50-200 sccm, the impurity source gas is CH ₄ , the flow rate of CH ₄ is 50-200 sccm, the deposition chamber The low-frequency radio frequency power of the chamber is 1 watt to 100 watts, and the high-frequency radio frequency power of the deposition chamber is 500 watts to 2000 watts, so that the formed first semiconductor epitaxial layer 301 can maintain good thickness uniformity and distribution of impurity ion concentration Uniformity.

Referring to FIG. 8, a second doped region (fluorine doped region) 302 is formed on the sidewall surface of the second fin portion 203, and the formation process of the second doped region (fluorine doped region) 302 is as follows: A second semiconductor epitaxial layer 302 containing fluorine ions is formed on the sidewall surface of the second fin 202 exposed by the first trench 211 and the third trench 213, and the second semiconductor epitaxial layer 302 serves as a fluorine-doped region or the second doped region.

The formation process of the second semiconductor epitaxial layer 302 is a (self-doping) selective epitaxial process, and the material of the second semiconductor epitaxial layer 302 is silicon or silicon germanium. Due to the special structure of the first fin portion 202 and the second fin portion 203, it is difficult to control the process when the ion implantation process forms the second doped region (fluorine doped region), and the (self-doping) selective epitaxy process can be easily The second semiconductor epitaxial layer 302 is formed, and the second semiconductor epitaxial layer 302 formed by this method can maintain better thickness uniformity and distribution uniformity of impurity ion concentration, so that the second semiconductor epitaxial layer 302 (second doped impurity region or fluorine-doped region) to prevent impurity ions (such as boron ions) in the P-type source and drain region from diffusing to the channel region along the sidewall of the second fin, preventing the generation of short channel effect, and effective The effect of preventing impurity ions (such as boron ions) in the P-type source and drain regions subsequently formed in the second fin portion 203 from diffusing into the shallow trench isolation structure formed between the second fin portion and the first fin portion is even greater. good.

Before forming the second semiconductor epitaxial layer 302, other regions (the first fin portion 202, the first semiconductor epitaxial layer 301 and part of the semiconductor substrate 200) other than the sidewall of the second fin portion 203 are covered with the mask layer, the The mask layer only exposes the sidewalls of the second fins 203, and then the second semiconductor epitaxial layer 302 is formed on the sidewalls of the second fins 203 by a selective epitaxial process. During the selective epitaxial process, the second semiconductor epitaxial layer 302 Self-doping fluoride ions.

In this embodiment, the material of the second semiconductor epitaxial layer 302 is silicon or silicon germanium, and the second semiconductor epitaxial layer 302 may serve as a part of the second fin.

In a specific embodiment, when the material of the second semiconductor epitaxial layer 302 is silicon, the (self-doping) selective epitaxy process is as follows: the temperature is 650-800 degrees Celsius, the pressure is 6-10torr, and the silicon source gas is SiH ₄ Or SiCl ₂ H ₄ , the flow rate of silicon source gas is 40-150 sccm, the selective gas is HCl, the flow rate of selective gas is 50-200 sccm, the impurity source gas is HF, the flow rate of HF is 50-150 sccm, the deposition chamber is low frequency The radio frequency power is 1 watt to 100 watts, and the high frequency radio frequency power of the deposition chamber is 500 watts to 2000 watts, so that the formed second semiconductor epitaxial layer 302 can maintain good thickness uniformity and distribution uniformity of impurity ion concentration .

Referring to FIG. 9 , forming a layer covering the first semiconductor epitaxial layer (first doped region or carbon doped region) 301, a second semiconductor epitaxial layer (second doped region or fluorine doped region) 302 and filling the first trench The shallow trench isolation structure 207 of the trench, the second trench and the third trench.

10-12 are schematic cross-sectional structure diagrams of the formation process of the fin field effect transistor in another embodiment of the present invention.

The difference between this embodiment and the previous embodiments is that the formation process of the first doped region (carbon doped region) and the second doped region (fluorine doped region) are different. region (carbon doped region) and the second doped region (fluorine doped region) before the process and the first doped region (carbon doped region) and the second doped region (fluorine doped region) after the For the specific definition and description of the process, please refer to the specific definition and description of relevant parts in the foregoing embodiments, and details are not repeated in this embodiment. Figure 10 is carried out on the basis of the aforementioned Figure 2 .

Referring to FIG. 10 and FIG. 11 , a first doped region (carbon doped region) 403 is formed on the sidewall surface of the first fin portion 202, and the formation process of the first doped region (carbon doped region) 403 is as follows: A first intermediate layer 401 containing carbon ions is formed on the sidewall surfaces of the first fin 202 exposed in the first trench 211 and the second trench 212, and the carbon in the first intermediate layer 401 is activated through an activation process. The ions are diffused to the sidewall surface of the first fin portion 202, forming a first doped region (carbon doped region) 403 on the sidewall surface of the first fin portion 202; Doped region (fluorine doped region) 404, the formation process of the second doped region (fluorine doped region) 404 is: in the second fin exposed in the first trench 211 and the third trench 213 The second intermediate layer 402 containing fluorine ions is formed on the side wall surface of the second fin portion 203, and the fluorine ions in the second intermediate layer 402 are diffused to the side wall surface of the second fin portion 203 through an activation process. A second doped region (fluorine doped region) 404 is formed on the sidewall surface.

The material of the first intermediate layer 401 is silicon oxide or silicon nitride doped with carbon ions, and the material of the second intermediate layer 402 is silicon oxide or silicon nitride doped with fluorine ions. The formation process of the first intermediate layer 401 and the second intermediate layer 402 is a self-doping deposition process, and before the formation of the first intermediate layer 401, the mask layer is covered on other areas outside the sidewalls of the first fin portion 202, The mask layer only exposes the sidewall surface of the first fin portion 202; then a first intermediate layer 401 containing carbon ions is formed on the sidewall surface of the first fin portion 202; the mask is removed after the first intermediate layer 401 is formed layer; similarly, before forming the second intermediate layer 402, other areas outside the side walls of the second fin 203 are covered with a mask layer, and the mask layer only exposes the side wall surface of the second fin 203; then A second intermediate layer 402 containing carbon ions is formed on the sidewall surface of the second fin portion 203 ; the mask layer is removed after forming the second intermediate layer 402 .

The activation process for diffusing carbon ions in the first intermediate layer 401 to the sidewall surfaces of the first fins 202 and the activation process for diffusing fluorine ions in the second intermediate layer 402 to the sidewall surfaces of the second fins 203 may be At the same time, in one embodiment, the activation process is an annealing process.

After performing the activation process, the first intermediate layer 401 and the second intermediate layer 402 may be removed, so that the first intermediate layer 401 and the second intermediate layer 402 may not be removed, and the first intermediate layer 401 and the second intermediate layer 402 as a part of the subsequently formed shallow trench isolation structure.

Referring to FIG. 12 , after the activation process is performed, a shallow trench isolation structure 207 covering the surfaces of the first intermediate layer 401 and the second intermediate layer 402 and filling the first trench, the second trench, and the third trench is formed. .

In this embodiment, the first intermediate layer 401 and the second intermediate layer 402 are not removed, and the first intermediate layer 401 and the second intermediate layer 402 are part of the shallow trench isolation structure 207 .

In other embodiments, after removing the first intermediate layer 401 and the second intermediate layer 402, the formed shallow trench isolation structure covers the first doped region (carbon doped region) 403 and the second doped region (fluorine doped region) region) 404 and fills the first trench, the second trench and the third trench.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (22)

1. A kind of 1. forming method of fin formula field effect transistor, it is characterised in that including：

   Semiconductor substrate is provided, the first fin and the second fin formed with projection in the Semiconductor substrate, first fin Formed with P type trap zone in portion, formed with N-type well region in the second fin, there is first groove between the first fin and the second fin, The first groove exposes the side wall of the first fin and the second fin, and the side of the remote first groove of the first fin has the Two grooves, side of second fin away from first groove have the 3rd groove；

   The first doped region, first doped region are formed in the sidewall surfaces for the first fin that first groove and second groove expose For preventing the foreign ion in P type trap zone from being spread into the fleet plough groove isolation structure being subsequently formed；

   The second doped region, second doped region are formed in the sidewall surfaces for the second fin that first groove and the 3rd groove expose Spread for side wall of the foreign ion in the source-drain area that prevents from subsequently being formed in N-type well region along the second fin to channel region And spread into the fleet plough groove isolation structure being subsequently formed；

   After the first doped region and the second doped region is formed, the filling isolation material in first groove, second groove and the 3rd groove Material, form fleet plough groove isolation structure.
2. 2. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that first doped region is Carbon doping area, second doped region are Fluorin doped area.
3. 3. the forming method of fin formula field effect transistor as claimed in claim 2, it is characterised in that the depth in the carbon doping area Spend for 2nm~12nm, the concentration of carbon ion is 5e18~5e19atom/cm in carbon doping area³。
4. 4. the forming method of fin formula field effect transistor as claimed in claim 3, it is characterised in that the shape in the carbon doping area It is into process：Using the first ion implantation technology, on the surface of the side wall for the first fin that first groove and second groove expose Carbon ion is adulterated in material, forms carbon doping area.
5. 5. the forming method of fin formula field effect transistor as claimed in claim 4, it is characterised in that first ion implanting The implant angle of technique is 5~25 degree, and the energy of injection is 2~8KeV, and the dosage of injection is 5e13~5e14atom/cm²。
6. 6. the forming method of fin formula field effect transistor as claimed in claim 2, it is characterised in that the depth in the Fluorin doped area Spend for 2nm~12nm, the concentration of fluorine ion is 5e18~1e20atom/cm in Fluorin doped area³。
7. 7. the forming method of fin formula field effect transistor as claimed in claim 6, it is characterised in that the shape in the Fluorin doped area It is into process：Using the second ion implantation technology, on the surface of the side wall for the second fin that first groove and the 3rd groove expose Fluorine ion is adulterated in material, forms Fluorin doped area.
8. 8. the forming method of fin formula field effect transistor as claimed in claim 7, it is characterised in that second ion implanting The implant angle of technique is 5~25 degree, and the energy of injection is 4~12KeV, and the dosage of injection is 1e14~1e15atom/cm²。
9. 9. the forming method of fin formula field effect transistor as claimed in claim 2, it is characterised in that the shape in the carbon doping area It is into process：Formed in the sidewall surfaces of first fin exposed in first groove and second groove and contain carbon ion First semiconductor epitaxial layers, first semiconductor epitaxial layers are as carbon doping area.
10. 10. the forming method of fin formula field effect transistor as claimed in claim 9, it is characterised in that first semiconductor The material of epitaxial layer is silicon or carborundum, a part of first semiconductor epitaxial layers as the first fin, the shallow trench Isolation structure covers the surface of the first semiconductor epitaxial layers.
11. 11. the forming method of fin formula field effect transistor as claimed in claim 2, it is characterised in that the Fluorin doped area Forming process is：Formed in the sidewall surfaces of second fin exposed in first groove and the 3rd groove and contain fluorine ion The second semiconductor epitaxial layers, second semiconductor epitaxial layers are as Fluorin doped area.
12. 12. the forming method of fin formula field effect transistor as claimed in claim 11, it is characterised in that second semiconductor A part of the epitaxial layer as the second fin, the materials of second semiconductor epitaxial layers are silicon or SiGe, the shallow trench Isolation structure covers the surface of the second semiconductor epitaxial layers.
13. 13. the forming method of fin formula field effect transistor as claimed in claim 2, it is characterised in that the carbon doping area Forming process is：Formed in the sidewall surfaces of first fin exposed in first groove and second groove and contain carbon ion The first intermediate layer, the sidewall surfaces of the first fin are diffused into by the carbon ion in the intermediate layer of activation technology first, The sidewall surfaces of first fin form carbon doping area.
14. 14. the forming method of fin formula field effect transistor as claimed in claim 2, it is characterised in that the Fluorin doped area Forming process is：Formed in the sidewall surfaces of second fin exposed in first groove and the 3rd groove and contain fluorine ion The second intermediate layer, the sidewall surfaces of the second fin are diffused into by the fluorine ion in the intermediate layer of activation technology second, The sidewall surfaces of second fin form Fluorin doped area.
15. 15. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that also include：It is etched back to Except the shallow ditch groove structure of segment thickness, the part side wall of the first fin and the second fin is exposed.
16. 16. the forming method of fin formula field effect transistor as claimed in claim 15, it is characterised in that be developed across part The top of one fin and the first grid structure of sidewall surfaces；Be developed across the fin of part second top and sidewall surfaces Two grid structures.
17. 17. the forming method of fin formula field effect transistor as claimed in claim 16, it is characterised in that also include：First The first source-drain area is formed in first fin of grid structure both sides；Second is formed in the second fin of second grid structure both sides Source-drain area.
18. 18. the forming method of fin formula field effect transistor as claimed in claim 17, it is characterised in that first source-drain area Doping type be N-type, the doping type of second source-drain area is p-type.
19. A kind of 19. fin formula field effect transistor, it is characterised in that including：

    Semiconductor substrate, the first fin and the second fin formed with projection in the Semiconductor substrate, in first fin Formed with P type trap zone, formed with N-type well region in the second fin, there is first groove between the first fin and the second fin, it is described First groove exposes the side wall of the first fin and the second fin, and the side of the remote first groove of the first fin has the second ditch Groove, side of second fin away from second groove have the 3rd groove；

    Positioned at the first doped region in first groove and the sidewall surfaces of the first fin of second groove exposure, first doping Area is used to prevent the foreign ion in P type trap zone from spreading into fleet plough groove isolation structure；

    Positioned at the second doped region in first groove and the sidewall surfaces of the second fin of the 3rd groove exposure, second doping Side wall of the foreign ion that area is used in the source-drain area that prevents from being formed in N-type well region along the second fin to channel region spread with And spread into fleet plough groove isolation structure；

    Fill the fleet plough groove isolation structure of first groove, second groove and the 3rd groove.
20. 20. fin formula field effect transistor as claimed in claim 19, it is characterised in that first doped region is carbon doping Area, second doped region are Fluorin doped area.
21. 21. fin formula field effect transistor as claimed in claim 20, it is characterised in that the depth in the carbon doping area is 2nm ~12nm, the concentration of carbon ion is 5e18~5e19atom/cm in carbon doping area³。
22. 22. fin formula field effect transistor as claimed in claim 20, it is characterised in that the depth in the Fluorin doped area is 2nm ~12nm, the concentration of fluorine ion is 5e18~1e20atom/cm in Fluorin doped area³。