CN118249747A - A broadband injection-locked doubler and tripler with high harmonic suppression ratio - Google Patents

Abstract

The invention discloses a high harmonic suppression ratio broadband injection-locked double and triple frequency multiplier, which adopts a multi-harmonic extraction transformer to perform secondary and tertiary amplification on the signal of the injector, and the multi-harmonic extraction transformer comprises two groups of output inductance groups and one group of input inductance groups, the two groups of output inductance groups are coupled with the input inductance group, the input end of the input inductance group is connected to the output end of the two groups of injectors, and the output ends of the two groups of injectors are respectively connected to one output end of a load pair, and the application uses a multi-harmonic extraction transformer composed of two groups of output inductance groups and one group of input inductance groups to amplify the second and third harmonics of the signals injected by the two groups of injectors, so as to achieve double and triple frequency, and the bandwidths of the double and triple frequencies overlap with each other, which equivalently expands the bandwidth, and the coupling between the inductors in the load pair increases the resonator impedance, thereby improving the harmonic suppression ratio, and compared with the traditional frequency multiplier structure, the structure proposed by the invention has a larger bandwidth and a higher harmonic suppression ratio.

Description

A broadband injection-locked doubler and tripler with high harmonic suppression ratio

Technical Field

The invention relates to the field of radio frequency technology, and in particular to a high harmonic suppression ratio broadband injection locked doubler and tripler.

Background technique

The injection-locked frequency multiplier is a commonly used device in electronic communication systems. Its function is to lock the frequency of the input signal at a specific frequency multiplication output, so that the frequency of the input signal can be amplified to a higher frequency multiplication output and effectively block interference signals from other frequencies. The injection-locked frequency multiplier plays an extremely important role in the phase-locked loop and is also a key circuit in wireless communication systems. Traditional injection-locked frequency multipliers are limited in practical application due to their poor harmonic suppression ratio, narrow bandwidth, and unchangeable frequency multiplication ratio.

The existing method to improve the harmonic suppression ratio is mainly to suppress the harmonic signals of a specific frequency by adding isolators or traps, but this method will increase power consumption, area and other overheads; the existing method to improve the bandwidth is mainly to increase the size of the injector transistor, but the increase in transistor size will make the parasitic capacitance too large and reduce the operating frequency; the existing method to achieve the multiplier ratio is mainly to introduce a harmonic mixer, but this will introduce nonlinear distortion and reduce the stability of the system.

As in the prior art, a patent application with application number 201911029869.8 discloses a broadband injection locked frequency multiplier, which uses multiple harmonic generators to generate second/third injected harmonics to achieve multiple frequency multiplication ratios. The use of multiple harmonic generators increases the complexity of the structure and increases the power consumption of the system.

Summary of the invention

The object of the present invention is to provide a high harmonic suppression ratio broadband injection locked doubler and tripler frequency multiplier to overcome the problems of complex structure and high system power consumption of the existing frequency multiplier.

A high harmonic suppression ratio broadband injection locked doubler and tripler frequency generator, comprising an injector, a load pair and a multi-harmonic extraction transformer, wherein the multi-harmonic extraction transformer comprises two groups of output inductance groups and one group of input inductance groups, the two groups of output inductance groups are coupled with the input inductance group, the output ends of the two groups of injectors are connected to the input ends of the input inductance groups, and the output ends of the two groups of injectors are respectively connected to one output end of the load pair;

One of the output inductor groups includes a first inductor L1 and a second inductor L2, one end of the first inductor L1 is connected to one end of the second inductor L2, the other end of the first inductor L1 and the other end of the second inductor L2 are connected to two capacitors in series, and the connection ends of the two capacitors are both grounded; the other end of the first inductor L1 and the other end of the second inductor L2 are output ends of one of the output inductor groups;

The input inductor group includes a third inductor L3 and a fourth inductor L4, one end of the third inductor L3 is connected to one end of the fourth inductor L4, the other end of the third inductor L3 is connected to the output end of one injector, and the other end of the fourth inductor L4 is connected to the output end of another injector;

Another output inductor group includes a fifth inductor L5 and a sixth inductor L6, one end of the fifth inductor L5 is connected to one end of the sixth inductor L6, the other end of the fifth inductor L5 and the other end of the sixth inductor L6 are the output end of the other output inductor group; the connection point between the fifth inductor L5 and the sixth inductor L6 is the bias voltage Vb3 connection point.

Preferably, the injector includes a MOS tube, a capacitor and a resistor, the gate of the MOS tube is connected to one end of the capacitor and one end of the resistor, the source of the MOS tube is grounded, the drain of the MOS tube is connected to the input end of the input inductor group, the other end of the capacitor is connected to the input signal; the other end of the resistor is a bias voltage connection point.

Preferably, the load pair includes a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5 and a sixth MOS tube M6, the drain of the third MOS tube M3 is connected to the gate of the fourth MOS tube M4, and the connection between the drain of the third MOS tube M3 and the gate of the fourth MOS tube M4 serves as an output end of the load pair;

The drain of the fourth MOS tube M4 is connected to the gate of the third MOS tube M3, and the connection point between the drain of the fourth MOS tube M4 and the gate of the third MOS tube M3 serves as another output end of the load pair;

The source of the fifth MOS tube M5 is grounded, and the drain of the fifth MOS tube M5 is connected to the source of the third MOS tube M3 and the source of the fourth MOS tube M4 respectively;

The drain of the sixth MOS tube M6 is connected to the gate of the sixth MOS tube M6 and the gate of the fifth MOS tube M5 respectively, and the drain of the sixth MOS tube M6 is connected to the power supply VDD, and the source of the sixth MOS tube M6 is grounded.

Preferably, the first inductor L1 is coupled with the third inductor L3, and the coupling coefficient between the first inductor L1 and the third inductor L3 is k1; the second inductor L2 is coupled with the fourth inductor L4, and the coupling coefficient between the second inductor L2 and the fourth inductor L4 is k1.

Preferably, for even harmonics in the current injected by the injector, the value of k1 is 0.3-0.5; for odd harmonics in the current injected by the injector, the value of k1 is 0.001.

Preferably, the third inductor L3 is coupled with the fifth inductor L5, and the coupling coefficient between the third inductor L3 and the fifth inductor L5 is k2; the fourth inductor L4 is coupled with the sixth inductor L6, and the coupling coefficient between the fourth inductor L4 and the sixth inductor L6 is k2.

Preferably, for even harmonics in the current injected by the injector, the value of k2 is 0.001; for odd harmonics in the current injected by the injector, the value of k2 is 0.2-0.4.

Preferably, the first inductor L1 is coupled with the fifth inductor L5, and the coupling coefficient between the first inductor L1 and the fifth inductor L5 is k3; the second inductor L2 is coupled with the sixth inductor L6, and the coupling coefficient between the second inductor L2 and the sixth inductor L6 is k3.

Preferably, the value of k3 is 0.4-0.6.

Compared with the prior art, the present invention has the following beneficial technical effects:

The present invention provides a high harmonic suppression ratio broadband injection-locked double and triple frequency multiplier, which adopts a multi-harmonic extraction transformer to perform secondary and tertiary amplification on the signal of the injector, and the multi-harmonic extraction transformer comprises two groups of output inductance groups and one group of input inductance groups, the two groups of output inductance groups are coupled with the input inductance group, the input end of the input inductance group is connected to the output end of the two groups of injectors, and the output ends of the two groups of injectors are respectively connected to one output end of a load pair. The present application uses a multi-harmonic extraction transformer composed of two groups of output inductance groups and one group of input inductance groups to amplify the second and third harmonics of the signals injected by the two groups of injectors, so as to achieve double and triple frequency, and the bandwidths of the double and triple frequencies overlap with each other, which equivalently expands the bandwidth.

Preferably, the coupling between the inductors in the load pair increases the resonator impedance, thereby improving the harmonic suppression ratio. Compared with the traditional frequency multiplier structure, the structure proposed in the present invention has a larger bandwidth and a higher harmonic suppression ratio.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a high harmonic suppression ratio broadband injection locked doubler or tripler circuit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of the interior of the resonant cavity when even harmonics in the current injected by the injector enter the resonant cavity in an embodiment of the present invention.

FIG3 is a schematic diagram of the interior of the resonant cavity when odd harmonics in the current injected by the injector enter the resonant cavity in an embodiment of the present invention.

FIG. 4 is a simulation diagram of the operating frequency range in an embodiment of the present invention.

FIG. 5 is a simulation diagram of harmonic suppression ratio in an embodiment of the present invention.

Detailed ways

In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

It should be noted that the terms "one of the groups", "another of the groups" and the like in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein.

As shown in Figure 1, the present invention provides a high harmonic suppression ratio broadband injection locked double and triple frequency generator, including an injector, a load pair and a multi-harmonic extraction transformer, the multi-harmonic extraction transformer includes two groups of output inductance groups and one group of input inductance groups, the two groups of output inductance groups are coupled with the input inductance group, the output ends of the two groups of injectors are connected to the input ends of the input inductance groups, and the output ends of the two groups of injectors are respectively connected to one output end of the load pair; the present application uses a multi-harmonic extraction transformer composed of two groups of output inductance groups and one group of input inductance groups to amplify the second and third harmonics of the signals injected by the two groups of injectors, which can achieve double and triple frequency, and the bandwidths of the double and triple frequencies overlap with each other, which equivalently expands the bandwidth.

In a specific embodiment of the present application, as shown in FIG1 , one of the output inductor groups includes a first inductor L1 and a second inductor L2, one end of the first inductor L1 is connected to one end of the second inductor L2, the other end of the first inductor L1 and the other end of the second inductor L2 are connected to two capacitors in series, and the connection ends of the two capacitors are grounded; the other end of the first inductor L1 and the other end of the second inductor L2 are the output ends of one of the output inductor groups.

The input inductor group includes a third inductor L3 and a fourth inductor L4, one end of the third inductor L3 is connected to one end of the fourth inductor L4, the other end of the third inductor L3 is connected to the output end of one injector, and the other end of the fourth inductor L4 is connected to the output end of another injector. The first inductor L1 is coupled to the third inductor L3, the second inductor L2 is coupled to the fourth inductor L4; the third inductor L3 and the fourth inductor L4 are connected to a power supply VDD.

Another output inductor group includes a fifth inductor L5 and a sixth inductor L6, one end of the fifth inductor L5 is connected to one end of the sixth inductor L6, and the other end of the fifth inductor L5 and the other end of the sixth inductor L6 are output ends of another output inductor group; the fifth inductor L5 is coupled to the third inductor L3, and the sixth inductor L6 is coupled to the fourth inductor L4; and the connection point between the fifth inductor L5 and the sixth inductor L6 is a connection point of the bias voltage Vb3.

In a specific embodiment of the present application, the injector includes a MOS tube M, a capacitor C and a resistor R, the gate of the MOS tube M is connected to one end of the capacitor C and one end of the resistor R, the source of the MOS tube M is grounded, the drain of the MOS tube M is connected to the input end of the input inductor group, that is, the drain of the MOS tube M is connected to the other end of the third inductor L3, the other end of the capacitor is connected to the input signal; the other end of the resistor is a bias voltage connection point.

In a specific embodiment of the present application, as shown in FIG1 , one of the injectors includes a first MOS transistor M1 , a first capacitor C1 and a first resistor R1 ;

The gate of the first MOS tube M1 is respectively connected to one end of the first capacitor C1 and one end of the first resistor R1, the source of the first MOS tube M1 is grounded, and the drain of the first MOS tube M1 is respectively connected to the drain of the third MOS tube M3 and the other end of the third inductor L3; the other end of the first capacitor C1 is the input signal Vinj+ connection point; the other end of the first resistor R1 is the bias voltage Vb1 connection point.

As shown in FIG1 , another injector includes a second MOS transistor M2, a second capacitor C2 and a second resistor R2, wherein the gate of the second MOS transistor M2 is respectively connected to one end of the second capacitor C2 and one end of the second resistor R2, the source of the second MOS transistor M2 is grounded, and the drain of the second MOS transistor M2 is respectively connected to the drain of the fourth MOS transistor M4 and the other end of the fourth inductor L4; the other end of the second capacitor C2 is the input signal Vinj-connection point; and the other end of the second resistor R2 is the bias voltage Vb2 connection point.

As shown in FIG1 , the load pair includes a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5 and a sixth MOS tube M6, the drain of the third MOS tube M3 is connected to the gate of the fourth MOS tube M4, and the connection between the drain of the third MOS tube M3 and the gate of the fourth MOS tube M4 serves as an output end of the load pair;

The drain of the fourth MOS tube M4 is connected to the gate of the third MOS tube M3, and the connection point between the drain of the fourth MOS tube M4 and the gate of the third MOS tube M3 serves as another output end of the load pair;

The source of the fifth MOS tube M5 is grounded, and the drain of the fifth MOS tube M5 is connected to the source of the third MOS tube M3 and the source of the fourth MOS tube M4 respectively;

The drain of the sixth MOS tube M6 is connected to the gate of the sixth MOS tube M6 and the gate of the fifth MOS tube M5 respectively, and the drain of the sixth MOS tube M6 is connected to the power supply VDD, and the source of the sixth MOS tube M6 is grounded.

When the high harmonic suppression ratio broadband injection locked doubler/tripler frequency multiplier of the present application is used, a differential signal Vinj+ and a differential signal Vinj- are output from two injectors respectively, the differential signal Vinj+ is injected from the gate of the first MOS tube M1 of one of the injectors, and the differential signal Vinj- is injected from the gate of the second MOS tube M2 of the other injector. The drain currents of the first MOS tube M1 and the second MOS tube M2 are expressed in the following form using the Fourier series formula:

In the above formula, For/> The drain current of the first MOS tube M1 and the second MOS tube M2 at the moment; /> is the frequency of the injected signal; /> are the Fourier coefficients of each order harmonic of drain current,/> Representatives Harmonics of order.

After passing through the multi-harmonic extraction transformer, the second harmonic is:

After passing through the multi-harmonic extraction transformer, the third harmonic is:

when ≥1, the Fourier coefficients of each harmonic of the drain current/> Expressed as:

in, is the period of the injected signal, /> is the conduction time of the first MOS transistor M1 and the second MOS transistor M2 within one cycle of the injected signal, /> It is the maximum peak-to-peak current output from the transistor drain.

The coupling coefficient between the first inductor L1 and the third inductor L3 is k1;

The coupling coefficient between the second inductor L2 and the fourth inductor L4 is k1;

The coupling coefficient between the third inductor L3 and the fifth inductor L5 is k2;

The coupling coefficient between the fourth inductor L4 and the sixth inductor L6 is k2;

The coupling coefficient between the first inductor L1 and the fifth inductor L5 is k3;

The coupling coefficient between the second inductor L2 and the sixth inductor L6 is k3;

In the above, for the even harmonics in the current injected by the injector, k1 is 0.3-0.5, k2 is 0.001, and k3 is 0.4-0.6; for the odd harmonics in the current injected by the injector, k1 is 0.001, k2 is 0.2-0.4, and k3 is 0.4-0.6.

In one embodiment of the present invention, as shown in FIG2 , for the even harmonics in the current injected by the injector, induced currents with opposite polarities are generated on the fifth inductor L5 and the sixth inductor L6, which cancel each other out; the even harmonics in the current injected by the injector generate induced currents with the same polarity on the first inductor L1 and the second inductor L2, which reinforce each other; at this time, the coupling coefficient K1 between the third inductor L3 and the first inductor L1 is relatively large, and the coupling coefficient K1 between the fourth inductor L4 and the second inductor L2 is relatively large; the coupling coefficient k2 between the third inductor L3 and the fifth inductor L5 is close to 0, and the coupling coefficient k2 between the fourth inductor L4 and the sixth inductor L6 is close to 0.

In another embodiment of the present invention, as shown in FIG3 , for odd harmonics in the current injected by the injector, induced currents with the same polarity are generated on the fifth inductor L5 and the sixth inductor L6, which reinforce each other; induced currents with opposite polarities are generated on the first inductor L1 and the second inductor L2, which cancel each other out. At this time, the coupling coefficient k1 between the third inductor L3 and the first inductor L1 is close to 0, and the coupling coefficient k1 between the fourth inductor L4 and the second inductor L2 is close to 0; the coupling coefficient k2 between the third inductor L3 and the fifth inductor L5 is relatively large, and the coupling coefficient k2 between the fourth inductor L4 and the sixth inductor L6 is relatively large.

Specifically, the MOS tubes used in the present application are all N-type MOS tubes, which have the characteristics of low voltage and low power consumption while increasing the output voltage swing. In the load pair of the present application, the drain of the fifth MOS tube M5 is respectively connected to the source of the third MOS tube M3 and the source of the fourth MOS tube M4, and the third MOS tube M3 and the fourth MOS tube M4 are connected by cross-coupling, which can form a negative resistance to supplement the energy consumed by the resonant cavity. The fifth MOS tube M5 is set as a tail current tube to ensure the oscillation of the oscillator and output a stable waveform. By adjusting the sizes of the third MOS tube M3, the fourth MOS tube M4 and the fifth MOS tube M5, the oscillator meets the oscillation conditions and has a stable voltage swing.

In yet another embodiment of the present invention, the present application conducts simulation experiments on the above-mentioned high harmonic suppression ratio broadband injection locked doubler and tripler:

The simulation experiment components of this application adopt SMIC 55nm RF CMOS process, and the simulation circuit of this application is built based on the Cadence IC618 simulation experiment platform.

The present invention simulates and verifies the high harmonic suppression ratio broadband injection locked double and triple frequency multiplier of the present application using the Spectre RF simulation tool. The specific circuit diagram is shown in FIG1 . The resistance of the first resistor R1 and the second resistor R2 is 4 kΩ, the capacitance of the first capacitor C1 and the second capacitor C2 is 2 pF, the capacitance of the third capacitor C3 and the fourth capacitor C4 is 250 fF, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 are RF NMOS transistors (n12ll_ckt_rf) in the SMIC 55nm RF CMOS process, the fifth MOS tube M5 and the sixth MOS tube M6 are RF NMOS transistors (n12ll_ckt_rf) in the SMIC 55nm RF CMOS process, the given power supply voltage VDD is 1.2 V, the operating temperature is 27 degrees Celsius, and the bias voltages Vb1 and Vb2 are both 0.35 V. As shown in Figure 4, it is a simulation diagram of the operating frequency range, in which the horizontal axis represents the output frequency (GHz), the vertical axis represents the input power (dBm), the square curve represents the double frequency, and the circular curve represents the triple frequency. From the simulation results of the operating frequency, it can be seen that the bandwidth of the double frequency is 22.2GHz to 32.4GHz, the bandwidth of the triple frequency is 25.2 GHz to 41.4GHz, and the total bandwidth is 22.2GHz to 41.4GHz; the frequency bands corresponding to different frequency multiplication modes in the present invention overlap with each other, which is equivalent to expanding the bandwidth; the harmonic suppression ratio simulation is performed for the circuit in the above specific embodiment, and the result is shown in Figure 5. Within the operating frequency range, the harmonic suppression ratio of the frequency doubler of the present invention is lower than -50dBc.

The device embodiments described above are merely illustrative. For example, the division of the modules is merely a logical function division. There may be other divisions in actual implementation, such as multiple units or plug-ins may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed may be through some interface, indirect coupling or communication connection of the device or unit, which may be electrical, mechanical or other forms.

Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. In the description of this specification, the description of the reference terms "one embodiment", "another embodiment", "another embodiment", etc. means that the specific features, structures or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this specification. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the present invention.

Claims (9)

1. A high harmonic suppression ratio broadband injection locked doubler and tripler, characterized in that it comprises an injector, a load pair and a multi-harmonic extraction transformer, wherein the multi-harmonic extraction transformer comprises two groups of output inductance groups and one group of input inductance groups, the two groups of output inductance groups are coupled with the input inductance group, the output ends of the two groups of injectors are connected to the input end of the input inductance group, and the output ends of the two groups of injectors are respectively connected to one output end of the load pair; One of the output inductor groups includes a first inductor L1 and a second inductor L2, one end of the first inductor L1 is connected to one end of the second inductor L2, the other end of the first inductor L1 and the other end of the second inductor L2 are connected to two capacitors in series, and the connection ends of the two capacitors are both grounded; the other end of the first inductor L1 and the other end of the second inductor L2 are output ends of one of the output inductor groups; The input inductor group includes a third inductor L3 and a fourth inductor L4, one end of the third inductor L3 is connected to one end of the fourth inductor L4, the other end of the third inductor L3 is connected to the output end of one injector, and the other end of the fourth inductor L4 is connected to the output end of another injector; Another output inductor group includes a fifth inductor L5 and a sixth inductor L6, one end of the fifth inductor L5 is connected to one end of the sixth inductor L6, the other end of the fifth inductor L5 and the other end of the sixth inductor L6 are the output end of the other output inductor group; the connection point between the fifth inductor L5 and the sixth inductor L6 is the bias voltage Vb3 connection point. 2. According to claim 1, a high harmonic suppression ratio broadband injection locked double or triple frequency generator, characterized in that the injector includes a MOS tube, a capacitor and a resistor, the gate of the MOS tube is connected to one end of the capacitor and one end of the resistor, the source of the MOS tube is grounded, the drain of the MOS tube is connected to the input end of the input inductor group, the other end of the capacitor is connected to the input signal; the other end of the resistor is a bias voltage connection point. 3. According to claim 1, a high harmonic suppression ratio broadband injection locked doubler and tripler, characterized in that the load pair comprises a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5 and a sixth MOS tube M6, the drain of the third MOS tube M3 is connected to the gate of the fourth MOS tube M4, and the connection between the drain of the third MOS tube M3 and the gate of the fourth MOS tube M4 serves as an output end of the load pair; The drain of the fourth MOS tube M4 is connected to the gate of the third MOS tube M3, and the connection point between the drain of the fourth MOS tube M4 and the gate of the third MOS tube M3 serves as another output end of the load pair; The source of the fifth MOS tube M5 is grounded, and the drain of the fifth MOS tube M5 is connected to the source of the third MOS tube M3 and the source of the fourth MOS tube M4 respectively; The drain of the sixth MOS tube M6 is connected to the gate of the sixth MOS tube M6 and the gate of the fifth MOS tube M5 respectively, and the drain of the sixth MOS tube M6 is connected to the power supply VDD, and the source of the sixth MOS tube M6 is grounded. 4. According to claim 1, a high harmonic suppression ratio broadband injection locked doubler and tripler frequency generator, characterized in that the first inductor L1 is coupled with the third inductor L3, and the coupling coefficient between the first inductor L1 and the third inductor L3 is k1; the second inductor L2 is coupled with the fourth inductor L4, and the coupling coefficient between the second inductor L2 and the fourth inductor L4 is k1. 5. A high harmonic suppression ratio broadband injection locked doubler or tripler according to claim 4, characterized in that for even harmonics in the current injected by the injector, the value of k1 is 0.3-0.5; for odd harmonics in the current injected by the injector, the value of k1 is 0.001. 6. According to claim 1, a high harmonic suppression ratio broadband injection locked double or tripler frequency generator, characterized in that the third inductor L3 is coupled with the fifth inductor L5, and the coupling coefficient between the third inductor L3 and the fifth inductor L5 is k2; the fourth inductor L4 is coupled with the sixth inductor L6, and the coupling coefficient between the fourth inductor L4 and the sixth inductor L6 is k2. 7. A high harmonic suppression ratio broadband injection locked doubler or tripler according to claim 6, characterized in that for even harmonics in the current injected by the injector, the value of k2 is 0.001; for odd harmonics in the current injected by the injector, the value of k2 is 0.2-0.4. 8. According to claim 1, a high harmonic suppression ratio broadband injection locked doubler and tripler, characterized in that the first inductor L1 is coupled with the fifth inductor L5, and the coupling coefficient between the first inductor L1 and the fifth inductor L5 is k3; the second inductor L2 is coupled with the sixth inductor L6, and the coupling coefficient between the second inductor L2 and the sixth inductor L6 is k3. 9. A high harmonic suppression ratio broadband injection locked doubler and tripler according to claim 8, characterized in that k3 is 0.4-0.6.