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CN118206070A - Manufacturing and wet sharpening method for high-aspect-ratio silicon nano cone array - Google Patents

Manufacturing and wet sharpening method for high-aspect-ratio silicon nano cone array Download PDF

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Publication number
CN118206070A
CN118206070A CN202410108759.5A CN202410108759A CN118206070A CN 118206070 A CN118206070 A CN 118206070A CN 202410108759 A CN202410108759 A CN 202410108759A CN 118206070 A CN118206070 A CN 118206070A
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Prior art keywords
silicon
etching
sharpening
cone
wet
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CN202410108759.5A
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Chinese (zh)
Inventor
崔波
康仁强
潘艾希
朱效立
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Kunshan Zhuozhi Micro Technology Co ltd
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Kunshan Zhuozhi Micro Technology Co ltd
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Priority to CN202410108759.5A priority Critical patent/CN118206070A/en
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00031Regular or irregular arrays of nanoscale structures, e.g. etch mask layer
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00388Etch mask forming
    • B81C1/00404Mask characterised by its size, orientation or shape
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00523Etching material
    • B81C1/00531Dry etching
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00523Etching material
    • B81C1/00539Wet etching

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

The invention belongs to the technical field of nano material preparation and application, and particularly relates to a manufacturing and wet sharpening method of a large-aspect-ratio silicon nano cone array, wherein in a dry etching stage, a silicon column with the height of 5 microns is etched by plasma deep silicon etching, on the basis of the silicon column, a continuous mode etching and an oxygen plasma etching mode are innovatively fused, samples are periodically further etched, the silicon substrate is etched by the continuous mode etching, the diameter and the height of a glue mask are gradually reduced due to the oxygen plasma etching, so that the nano silicon cone is etched, then the etched silicon cone array is subjected to preliminary sharpening by two different wet processes, and finally the balance between the high efficiency and the shape controllability in cone array manufacturing is realized by applying the etching and various sharpening methods.

Description

Manufacturing and wet sharpening method for high-aspect-ratio silicon nano cone array
Technical Field
The invention belongs to the technical field of nano material preparation and application, and particularly relates to a method for manufacturing and wet sharpening a silicon nano cone array with a large aspect ratio.
Background
With the rapid development of the semiconductor industry, silicon nano-structures have become one of the most widely studied directions in the scientific, medical and engineering fields, and in these structures, silicon nano-cone arrays have become the focus of various research applications, the application range covers field emission X-rays, solar cells, optical sensors, nanoneedles and various characterization tools, such as atomic force microscope probes, and the research and application of these silicon nano-cone arrays play a key role in the continuous progress of technology.
Existing silicon nanotaper array fabrication methods include bottom-up (bottom-up) or top-down (top-down) techniques, where the vapor-droplet-solid (VLS) method is the main bottom-up self-assembly method in which silicon is integrated into liquid Au-Si nanodroplets and then condensed into a solid phase, which are relatively low cost, but the resulting silicon nanotaper array is not uniform and has low reproducibility; wet etching is a main top-down manufacturing method, and is mainly used for anisotropic etching of a silicon substrate by using a tetramethyl ammonium hydroxide (TMAH) or potassium hydroxide (KOH) solution, so that a silicon nano cone array is obtained, and the wet etching method is low in manufacturing cost and high in yield benefit, but the etched silicon nano cone has a fixed side wall cone angle determined by a silicon crystal structure;
Other wet processes such as Metal Assisted Chemical Etching (MACE) which require metal nanostructures to catalyze silicon etching, may introduce metal impurities and form porous structures, and in addition, wet etching often results in non-uniformity and significant critical dimension loss due to excessive etching.
In view of the above, the dry etching from top to bottom etches a topography-controllable anisotropic structure better than the wet etching, wherein the plasma deep silicon etching consists of alternating etching and passivation steps, which is easy to form a rough groove profile on the sidewall;
Therefore, it can be summarized that the main problem of the prior art is that the balance between the high efficiency and the shape controllability cannot be achieved;
in view of the above, the technical scheme provides a method for manufacturing and wet sharpening a silicon nano cone array with a large aspect ratio.
Disclosure of Invention
The embodiment of the invention aims to provide a method for manufacturing and wet sharpening a silicon nano cone array with a large aspect ratio, which aims to solve the problem.
The invention is realized in such a way that the method for manufacturing and wet sharpening the silicon nano cone array with large aspect ratio comprises the following steps:
s1, selecting a clean silicon substrate 1 as a starting sample;
S2, spin-coating a layer of ultraviolet photoresist on the clean silicon substrate 1;
S3, placing the silicon substrate with the ultraviolet photoresist spin-coated on a hot plate, baking for 1-2 minutes at 110 ℃, performing laser direct writing by using a maskless photoetching machine to form a designed pattern sample, performing ultraviolet exposure, and developing the ultraviolet photoresist at room temperature for 1-5 minutes after finishing;
s4, transferring the pattern on the resist to a silicon substrate by using a Bosch process to form a silicon column 4, and improving the aspect ratio of the structure;
S5, using a mode of reducing the diameter of the resist mask, namely using an etching mode combining continuous mode etching and oxygen plasma etching, and periodically further etching the sample to form a silicon cone 5 pattern;
s6, sharpening the silicon cone 5 in the S5 by using a sharpening solution under the normal temperature or normal temperature ultrasonic condition,
The sharpening solution uses 35% KOH solution 6, so that the silicon cone 5 is sharpened for 5-20 minutes under the condition of normal-temperature ultrasonic; or using an aqueous solution 7 (the ratio is 50:1-300:1) of 69% nitric acid and 49% hydrofluoric acid, and standing the silicon cone 5 for 3 minutes for sharpening under normal temperature conditions;
S7, carrying out high-temperature thermal oxidation on the sharpened silicon cone 5 array, removing silicon oxide by using 49% hydrofluoric acid, and further sharpening the silicon cone 5 array;
Wherein the temperature of the high-temperature thermal oxidation is set at 700-950 DEG, and the time of the thermal oxidation is 2-8h, preferably 5h.
According to the manufacturing and wet sharpening method of the large-aspect-ratio silicon nano cone array, in a dry etching stage, a silicon column with the height of 5 microns is etched by plasma deep silicon etching (DRIE, bosch process), the diameter of the silicon column is 3.5 microns, on the basis of the silicon column, the etching modes of continuous mode etching and oxygen plasma etching are innovatively fused, samples are periodically further etched, the silicon substrate is etched by the continuous mode etching, the diameter and the height of a glue mask are gradually reduced by the oxygen plasma etching, and thus the nano silicon cone is etched;
After the dry etching is finished, the top end of the silicon nano cone is close to a plane, the diameter of the plane is about 400 nm, and the top end at the moment is a plane instead of the tip end, so that the top end of the silicon nano cone cannot be further sharpened in an oxidation sharpening mode;
Firstly, under the conditions of normal temperature and ultrasonic treatment, placing a sample in a 35% KOH solution, reducing the diameter of the top end of the sample to about 70 nm, and reducing the tip end to below 20 nm after further oxidation sharpening;
secondly, under the condition of normal temperature, placing the sample in an aqueous solution of 69% nitric acid and 49% hydrofluoric acid, reducing the diameter of the top end of the sample to about 80 nm, and reducing the tip end to below 20 nm after further oxidation sharpening;
summarizing the above, the technical scheme can realize the manufacture of the silicon nanometer cone needle tip smaller than 20nm by applying etching and various sharpening methods.
Drawings
FIG. 1 is a process flow diagram of one embodiment of a method for manufacturing and wet sharpening a high aspect ratio silicon nanotaper array;
fig. 2 is a process flow diagram of a second embodiment of a method for manufacturing and wet sharpening a high aspect ratio silicon nanotaper array.
In the accompanying drawings: 1-silicon substrate, 2-nLof 2035 photoresist mask, 3-laser light source, 4-silicon column, 5-silicon cone, 6-35% potassium hydroxide solution, 7-49% hydrofluoric acid and 69% nitric acid mixed water solution.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Specific implementations of the invention are described in detail below in connection with specific embodiments.
The method for manufacturing and wet sharpening the silicon nano cone array with the large aspect ratio comprises the following steps of:
S1, selecting a clean silicon substrate 1 as a starting sample;
S2, spin-coating a layer of ultraviolet photoresist on the clean silicon substrate 1;
the thickness of the ultraviolet photoresist is set to be 2-10 microns, preferably 6 microns;
S3, placing the silicon substrate with the ultraviolet photoresist spin-coated on a hot plate, baking for 1 minute at 110 ℃, performing laser direct writing by using a maskless photoetching machine to form a design pattern, performing ultraviolet exposure, and developing the ultraviolet photoresist at room temperature for 1-5 minutes after finishing the ultraviolet exposure;
Preferably, the exposure dose for the design pattern area in S3 is 200-1000 mJ/cm, and the development time for the ultraviolet resist is preferably 3 minutes;
s4, transferring the pattern on the resist to a silicon substrate by using a Bosch process to form a silicon column 4, and improving the aspect ratio of the structure;
The Bosch process is to deposit one layer of etched film on the side wall to prevent or weaken side etching in the manufacture of integrated circuit, and has fluoro-base active radical to etch silicon, side wall passivation and protecting alternately.
S5, using a mode of reducing the diameter of the resist mask, namely using an etching mode combining continuous mode etching and oxygen plasma etching, and periodically further etching the sample to form a silicon cone 5 pattern;
The continuous mode etching etches the silicon substrate, wherein RF (radio frequency current) power is 5-30W, ICP power is 800-1200W ICP, gas flow of C 4F8 (octafluorocyclobutane) is 20-50 sccm, and gas flow of SF 6 (sulfur hexafluoride) is 10-30 sccm; the size of the nLof 2035 photoresist mask 2 is reduced by oxygen plasma etching, the diameter of a silicon column 4 to be etched later is synchronously reduced, the RF (radio frequency current) power is 5-20W, the ICP power is 800-1200W ICP, and the gas flow of oxygen is 10-60 sccm. After the two kinds of etching are finished, integrally forming a silicon cone 5 pattern;
Specifically, in the continuous mode etching, the RF (radio frequency current) power is preferably 10 to 20 w, the icp power is preferably 1000w icp, the gas flow rate of c 4F8 (octafluorocyclobutane) is preferably 35 sccm, and the gas flow rate of SF 6 (sulfur hexafluoride) is 20 sccm;
in oxygen plasma etching, RF (radio frequency current) power is 8-15W, ICP power is 1000W ICP, and the gas flow of oxygen is 35sccm.
S6, sharpening the silicon cone 5 in the S5 by using a sharpening solution under the normal temperature or normal temperature ultrasonic condition,
The sharpening solution uses 35% KOH solution 6, so that the silicon cone 5 is sharpened for 5-20 minutes under the condition of normal-temperature ultrasonic; or using an aqueous solution 7 (the ratio is 50:1-300:1) of 69% nitric acid and 49% hydrofluoric acid, and standing the silicon cone 5 for 3 minutes for sharpening under normal temperature conditions;
S7, carrying out high-temperature thermal oxidation on the sharpened silicon cone 5 array, removing silicon oxide by using 49% hydrofluoric acid, and further sharpening the silicon cone 5 array;
Wherein the temperature of the high-temperature thermal oxidation is set at 700-950 DEG, and the time of the thermal oxidation is 2-8h, preferably 5h.
As a preferred embodiment of the invention, as shown in FIG. 1, when sharpening is performed by using 35% KOH solution as the sharpening solution, a specific process flow of the silicon nano-cone array with large aspect ratio comprises the following steps:
S101, selecting a single-sided polished silicon wafer as a substrate, and cleaning the substrate by using an RCA standard cleaning flow (shown in FIG. 1 a);
S102, spin-coating a 3.2 micrometer nLof 2035 photoresist film 2 on a substrate;
S103, placing the substrate with the photoresist film 2 spin-coated with nLof2035 on a hot plate, baking at 110 ℃ for 1 minute, and performing laser direct writing by using a maskless photoetching machine, wherein the nLof2035 photoresist film 2 is used as negative resist and is subjected to laser direct writing to form a design pattern, the formed pattern is a circle with the diameter of 3.5 microns, and the array period is 10 microns (as shown in figure 1 b); then placing the sample on a hot plate and baking at 110 ℃ for 1 minute, cooling the sample, immersing the sample in MICROPOSIT MF-319 developing solution at room temperature for developing the photoresist nLof2035 for 1 minute, and washing and drying the sample by deionized water (shown in fig. 1 c);
s104, carrying out dry etching on the silicon substrate by taking the developed nLof 2035 pattern layer as a mask to form a silicon column 4, wherein the used reactive ion etching is a standard Bosch process, and the etching and passivation processes are alternately carried out to weaken the transverse etching, and the target etching depth is 5 micrometers under the following etching conditions (as shown in figure 1 d);
Etching: 20 W RF, 1000W ICP, SF 6 flow 160 sccm, 25 mTorr, 7s;
Passivation: 5W RF, 1000W ICP, C 4F8 flow 160 sccm, 20 mTorr, 5s;
S105, based on the silicon column 4, merging the etching modes of continuous mode etching and oxygen plasma etching, and periodically further etching the sample, wherein the continuous mode etching etches the silicon substrate, and the oxygen plasma etching reduces the size of the nLof 2035 photoresist mask, so as to finish the etching of the nanometer silicon cone 5; the target etch depth was 5 microns (as shown in fig. 1 e) under the following etch conditions:
Etching 10W RF, 1200W ICP, C 4F8:SF6 = 38:22, 10 mTorr, 32s;
Oxygen 5W RF, 1000W ICP, 40 sccm O 2, 10 mTorr, 12s;
s106, removing the residual resist mask (shown in FIG. 1 f);
s107, placing the sample in 35% KOH solution 6 at normal temperature, carrying out ultrasonic treatment for 8 minutes, and reducing the diameter of the top end of the sample to about 70 nm (shown in figure 1 g);
S108, after the sample is subjected to oxidative sharpening at 950 ℃ for 2 hours, the silicon oxide is removed by using 49% hydrofluoric acid, and the tip is reduced to below 20 nm (shown in FIG. 1 h).
As a second preferred embodiment of the present invention, as shown in fig. 2, when the aqueous solution 7 of 69% nitric acid and 49% hydrofluoric acid is used as the sharpening solution for sharpening, a specific process flow of the silicon nano cone array with a large aspect ratio comprises the following steps:
s201, selecting a single-sided polished silicon wafer as a substrate, and cleaning the substrate by using an RCA standard cleaning flow (shown in FIG. 2 a);
S202, spin-coating a 3.2 micrometer nLof 2035 photoresist film 2 on a substrate;
S203, placing the substrate with the photoresist film 2 spin-coated with nLof2035 on a hot plate, baking at 110 ℃ for 1 minute, and performing laser direct writing by using a maskless photoetching machine, wherein the nLof2035 photoresist film 2 is used as negative resist and is subjected to laser direct writing to form a design pattern, the formed pattern is a circle with the diameter of 3.5 microns, and the array period is 10 microns (as shown in figure 2 b); then placing the sample on a hot plate and baking at 110 ℃ for 1 minute, cooling the sample, immersing the sample in MICROPOSIT MF-319 developing solution at room temperature for developing the photoresist nLof2035 for 1 minute, and washing and drying the sample by deionized water (shown in fig. 2 c);
S204, dry etching is carried out on the silicon substrate by taking the developed nLof 2035 pattern layer as a mask to form a silicon column 4, the used reactive ion etching is a standard Bosch process, the etching and passivation processes are alternately carried out to weaken the transverse etching, and the target etching depth is 5 microns under the following etching conditions (as shown in figure 1 d);
Etching: 20 W RF, 1000W ICP, SF 6 flow 160 sccm, 25 mTorr, 7s;
Passivation: 5W RF, 1000W ICP, C 4F8 flow 160 sccm, 20 mTorr, 5s;
S205, based on the silicon column 4, merging the etching modes of continuous mode etching and oxygen plasma etching, and periodically further etching the sample, wherein the continuous mode etching etches the silicon substrate, and the oxygen plasma etching reduces the size of nLof 2035 photoresist mask, so as to finish the etching of the nano silicon 5; the target etch depth was 5 microns (as shown in fig. 2 e) under the following etch conditions:
Etching 10W RF, 1200W ICP, C 4F8:SF6 = 38:22, 10 mTorr, 32s;
Oxygen 5W RF, 1000W ICP, 40 sccm O 2, 10 mTorr, 12s;
S206, removing the residual resist mask (shown in FIG. 2 f);
s207, placing the sample in a 100:1 aqueous solution of 69% nitric acid and 49% hydrofluoric acid at normal temperature, performing ultrasonic treatment for 8 minutes, and reducing the diameter of the top end of the sample to about 80 nm (shown in fig. 2 g);
s208, after the sample is subjected to oxidative sharpening at 950 ℃ for 2 hours, the silicon oxide is removed by using 49% hydrofluoric acid, and the tip is reduced to below 20 nm (shown in FIG. 2 h);
For the first embodiment and the second embodiment, it should be noted that nLof 2035 photoresist film 2 is a film material whose solubility can be changed under illumination or radiation such as ultraviolet light, and belongs to one type of ultraviolet photoresist;
wherein the laser light source 3 of the maskless lithography machine is set as a group of diode lasers, and the exposure wavelength and the dose are 375 nm and 220 mJ/cm.
Specifically, RCA standard cleaning is typically used when there is a thin oxide layer on the wafer die and silicon, and for this solution, it mainly removes the heavy alkali ions and cations on the silicon wafer, and it uses a kind of defect cleaning, which is a chemical method for cleaning the defects on the surface or inside of the product during the manufacturing process, and uses specific cleaning agents and process parameters to remove dirt, residues, oxide layers or other defects on the surface of the product.
In the RCA standard cleaning process, the defect cleaning mainly comprises the following steps of-I
Pre-treating, namely primarily cleaning the silicon wafer to remove dirt and impurities on the surface;
Selecting a cleaning agent, namely selecting an HPM solution cleaning agent formed by mixing hydrochloric acid, hydrogen peroxide and water according to a certain proportion according to the material and defect type of a product;
Soaking and cleaning, namely soaking the product in a cleaning agent, and decomposing, swelling or stripping defects by utilizing chemical reaction;
4. rinsing, namely rinsing the silicon wafer by using clear water to remove residual cleaning agent and impurities;
5. Drying, namely airing the silicon wafer or drying the silicon wafer by using drying equipment to keep the surface of the silicon wafer dry.
It should be noted that, according to the implementation of the above embodiment, batch preparation of the silicon nano cone array with a large aspect ratio can be truly realized, but due to non-uniformity of dry etching on the four-inch and eight-inch wafers, the etching rates of the embodiments in the technical scheme are different at the center and the edge of the large-size silicon wafer. Thus, one skilled in the art should be aware of the correlation and regulation of etch rate with sample size.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims (9)

1. The manufacturing and wet sharpening method of the silicon nano cone array with the large aspect ratio is characterized by comprising the following steps of:
s1, selecting a clean silicon substrate (1) as a starting sample;
s2, spin-coating a layer of ultraviolet photoresist on the clean silicon substrate (1);
S3, placing the silicon substrate with the ultraviolet photoresist spin-coated on a hot plate, baking for 1-2 minutes at 110 ℃, performing laser direct writing by using a maskless photoetching machine to form a designed pattern sample, performing ultraviolet exposure, and then developing the ultraviolet photoresist at room temperature for 1-5 minutes;
s4, transferring the pattern on the resist to a silicon substrate by using a Bosch process to form a silicon column (4), and improving the aspect ratio of the structure;
S5, using a mode of reducing the diameter of the resist mask, namely using an etching mode combining continuous mode etching and oxygen plasma etching, and periodically further etching the sample to form a silicon cone (5) pattern;
S6, sharpening the silicon cone (5) in the S5 by using a sharpening solution formed by a 35% KOH solution (6) or a water solution (7) formed by mixing 69% nitric acid and 49% hydrofluoric acid, and sharpening for 5-20 minutes under corresponding normal-temperature ultrasonic or standing and sharpening for 3 minutes under normal-temperature conditions;
s7, performing high-temperature thermal oxidation on the sharpened silicon cone (5) array, removing silicon oxide by using 49% hydrofluoric acid, and further sharpening the silicon cone (5) array.
2. The method for manufacturing and wet sharpening a high aspect ratio silicon nanotaper array according to claim 1, wherein the silicon substrate (1) is a single-sided polished silicon wafer.
3. The method of claim 1, wherein the uv resist thickness in step S2 is set to 2-10 μm.
4. A method for manufacturing and wet sharpening a high aspect ratio silicon nanotaper array according to claim 3, wherein the ultraviolet photoresist is nLof 2035 photoresist film (2), and nLof 2035 photoresist film (2) is a film material with solubility changed under illumination or radiation such as ultraviolet light, belonging to ultraviolet photoresist.
5. The method of claim 1, wherein in step S3, the exposure dose for the designed pattern area is 200-1000 mJ/cm.
6. A method of manufacturing and wet sharpening high aspect ratio silicon nanotaper arrays according to claim 1, wherein the laser light source (3) of the maskless lithography machine is configured as a set of diode lasers with exposure wavelength and dose of 375 nm and 220 mJ/cm.
7. The method for manufacturing and wet sharpening a silicon nano cone array with high aspect ratio according to claim 1, wherein the exposed sample in S3 is immersed in MICROPOSIT MF-319 developing solution to develop photoresist nLof 2035, the developing time is set to 3 minutes, and the sample is rinsed with deionized water and dried.
8. The method of claim 1, wherein in step S5, the silicon substrate is etched by continuous mode etching, the RF (radio frequency current) power is 5-30W, the ICP power is 800-1200W ICP, the gas flow rate of C 4F8 (octafluorocyclobutane) is 20-50 sccm, and the gas flow rate of SF 6 (sulfur hexafluoride) is 10-30 sccm;
the size of nLof 2035 photoresist mask 2 is reduced by oxygen plasma etching, the diameter of a silicon column (4) to be etched later is synchronously reduced, RF (radio frequency current) power is 5-20W, ICP power is 800-1200W ICP, and the gas flow of oxygen is 10-60 sccm, and a silicon cone (5) pattern is integrally formed after the two etching ends.
9. The method of manufacturing and wet sharpening a high aspect ratio silicon nanotaper array according to claim 1, wherein in step S7, the temperature of the thermal oxidation is set to 700-950 °, and the time of the thermal oxidation is set to 2-8h.
CN202410108759.5A 2024-01-26 2024-01-26 Manufacturing and wet sharpening method for high-aspect-ratio silicon nano cone array Pending CN118206070A (en)

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