CN118157659B - Odd-number frequency dividing circuit - Google Patents
Odd-number frequency dividing circuit Download PDFInfo
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- CN118157659B CN118157659B CN202410564922.9A CN202410564922A CN118157659B CN 118157659 B CN118157659 B CN 118157659B CN 202410564922 A CN202410564922 A CN 202410564922A CN 118157659 B CN118157659 B CN 118157659B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/02—Input circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/08—Output circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
- H03K23/502—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits with a base or a radix other than a power of two
- H03K23/505—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits with a base or a radix other than a power of two with a base which is an odd number
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Abstract
The invention discloses an odd-number frequency dividing circuit. The clock signals of the first rising edge D trigger to the N-2 rising edge D trigger and the N rising edge D trigger are inputted into CLKP, the clock signals of the N-1 rising edge D trigger are inputted into CLKN, the input end of the first rising edge D trigger is connected with the output end of the NAND gate, the output ends of the N-1 rising edge D trigger and the N rising edge D trigger are respectively connected with the input end of the NAND gate, the output end of the first inverter is respectively connected with the input end of the second inverter and the clock ports of the N-1 rising edge D trigger, the output end of the second inverter is respectively connected with the clock ports of the first rising edge D trigger to the N-2 rising edge D trigger and the N rising edge D trigger, and the output end of the NAND gate is connected with the input end of the third inverter. The odd-number frequency dividing circuit of the invention has an output duty ratio of 50% and low power consumption.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and in particular, to an odd-number frequency dividing circuit.
Background
In multiband or multistandard applications, frequency dividers are widely used for expanding the frequency range. When using an even divider we can easily get a signal with a 50% duty cycle. But the duty cycle of a conventional odd divider is not equal to 50%. For example, conventional divide-by-five dividers can achieve a duty cycle of 60% or 40%. Such imperfect signals may cause even harmonics, degrading circuit performance. To avoid this, many odd-numbered frequency dividing circuits outputting 50% duty ratio have been proposed, but most of them are complex in structure, and some even require the use of a calibration circuit, resulting in increased power consumption.
Disclosure of Invention
The invention provides an odd-number frequency division circuit, which can improve the problem that the duty ratio of an output signal is not 50%.
In order to achieve the above object, the present invention provides the following solutions:
An odd-numbered frequency dividing circuit includes: the number of the rising edge D triggers is N, the number of the inverters is 3, the number of the NAND gates is 1, the first rising edge D trigger to the nth rising edge D trigger are sequentially connected, clock signals of the first rising edge D trigger to the N-2 rising edge D trigger and the nth rising edge D trigger are input into CLKP, inverse relation exists between the clock signals of the N-1 rising edge D trigger and CLKP, the input end of the first rising edge D trigger is connected with the output end of the NAND gate, the output end of the N-1 rising edge D trigger is connected with the input end of the NAND gate, the output end of the first inverter is connected with the input end of the second inverter and the clock ports of the N-1 rising edge D trigger, the output end of the second inverter is connected with the output end of the first rising edge D trigger to the output end of the second inverter, the output end of the second inverter is connected with the rising edge D trigger and the output end of the N-1 rising edge D trigger is connected with the output end of the rising edge D trigger.
Optionally, the reset state of each rising edge D flip-flop is a low level trigger.
Optionally, when the reset signal is at a low level, that is, the circuit is in a reset state, each of the flip-flop outputs is at a low level, and the nand gate outputs are at a high level; when the reset signal goes from low to high, the circuit begins to operate.
Optionally, when the odd-numbered frequency dividing circuit is a divide-by-five circuit, the divide-by-five circuit includes four rising edge D flip-flops, three inverters, and one nand gate.
Optionally, the four rising edge D flip-flops output Data at the time of coming the rising edge of the CLK clock signal respectively, and the output at the rest time remains unchanged, and the output frequency of the four rising edge D flip-flops is one fifth of the CLK signal, and the signal duty ratio is 60%.
Optionally, the clock signals of the first rising edge D flip-flop, the second rising edge D flip-flop and the fourth rising edge D flip-flop are input as CLKP, and the output ends of the first rising edge D flip-flop, the second rising edge D flip-flop and the fourth rising edge D flip-flop have a phase difference of one CLK clock period in sequence.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
The invention provides an odd-number frequency dividing circuit, which comprises: the device comprises rising edge D triggers, inverters and NAND gates, wherein the number of the rising edge D triggers is N, the number of the inverters is 3, the number of the NAND gates is 1, the first rising edge D trigger to the nth rising edge D trigger are sequentially connected, clock signals of the first rising edge D trigger to the (N-2) th rising edge D trigger and the nth rising edge D trigger are input into CLKP, the clock signals of the (N-1) th rising edge D trigger are input into CLKP, inverse relation exists between the CLKP and the CLKN, the input end of the first rising edge D trigger is connected with the output end of the NAND gate, the output end of the (N-1) th rising edge D trigger and the output end of the (N-1) th rising edge D trigger are respectively connected with the input end of the second rising edge D trigger and the clock ports of the (N-1) th rising edge D trigger, the output end of the second rising edge D trigger is respectively connected with the clock ports of the first rising edge D trigger to the (N-2) th rising edge D trigger and the output end of the same, and the output end of the third rising edge D trigger is connected with the output end of the third rising edge D trigger. The odd-number frequency dividing circuit has the advantages of simple structure, 50% output duty ratio, low power consumption and the like, and is very suitable for application requirements of the odd-number frequency dividing circuit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a divide-by-five circuit;
FIG. 2 is a timing diagram of the divide-by-five circuit operation;
FIG. 3 is a block diagram of a divide-by-N circuit;
fig. 4 is a block diagram of a divide-by-seven circuit configuration.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides an odd-number frequency division circuit, which can improve the problem that the duty ratio of an output signal is not 50%.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Example 1:
An odd-numbered frequency dividing circuit includes: the number of the rising edge D triggers is N, the number of the inverters is 3, the number of the NAND gates is 1, the first rising edge D trigger to the nth rising edge D trigger are sequentially connected, clock signals of the first rising edge D trigger to the N-2 rising edge D trigger and the nth rising edge D trigger are input into CLKP, inverse relation exists between the clock signals of the N-1 rising edge D trigger and CLKP, the input end of the first rising edge D trigger is connected with the output end of the NAND gate, the output end of the N-1 rising edge D trigger is connected with the input end of the NAND gate, the output end of the first inverter is connected with the input end of the second inverter and the clock ports of the N-1 rising edge D trigger, the output end of the second inverter is connected with the output end of the first rising edge D trigger to the output end of the second inverter, the output end of the second inverter is connected with the rising edge D trigger and the output end of the N-1 rising edge D trigger is connected with the output end of the rising edge D trigger.
The reset state of each rising edge D trigger is low level trigger. When the reset signal is low level, namely the circuit is in a reset state, the output of each trigger is low level, and the output of the NAND gate is high level; when the reset signal goes from low to high, the circuit begins to operate.
Example 2:
when the odd-number frequency dividing circuit is a divide-by-five frequency dividing circuit, the divide-by-five frequency dividing circuit comprises four rising edge D flip-flops, three inverters and a NAND gate. Wherein the CLK inputs of the rising edge D flip-flops DFF1, DFF2, and DFF4 are CLKP and the CLK input of DFF3 is CLKN. A block diagram of the divide-by-five circuit is shown in figure 1,
The working sequence of the divide-by-five circuit is shown in fig. 2, the four rising edge D flip-flops output Data end Data in the rising edge of the CLK clock signal at time respectively, the output of the four rising edge D flip-flops is kept unchanged at other time, the output frequency of the four rising edge D flip-flops is one fifth of the CLK signal, and the signal duty ratio is 60%.
The clock signals of the first rising edge D flip-flop, the second rising edge D flip-flop and the fourth rising edge D flip-flop are inputted as CLKP, and the output terminals of the first rising edge D flip-flop, the second rising edge D flip-flop and the fourth rising edge D flip-flop have a phase difference of one CLK clock period in sequence, that is, the output terminals Q1, Q2 and Q4 have a phase difference of one CLK clock period in sequence. The clock signal CLKN of the flip-flop DFF3 has an inverse relationship with the clock signal CLKP of the flip-flop DFF4, and the output signals Q3 and Q4 of the two flip-flops have a phase difference of one half CLK period. Therefore, only Q3 and Q4 need be logically nand-operated to obtain a clock signal having a frequency of one fifth of the CLK signal and a duty cycle of 50%.
The odd-number frequency dividing circuit provided by the invention has the advantages of simple structure, 50% of output duty ratio, low power consumption and the like, and is very suitable for application requirements of the odd-number frequency dividing circuit. As shown in fig. 3, this structure can also satisfy any odd-numbered division scenario by cascading D flip-flops between flip-flops DFF2 and DFF 3. For example, if 1D flip-flop is cascaded between DFF2 and DFF3 on the basis of divide-by-five circuit, then the structure becomes a divide-by-seven circuit as shown in fig. 4.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.
Claims (3)
1. An odd-numbered dividing circuit, characterized by comprising: the device comprises rising edge D flip-flops, inverters and NAND gates, wherein the number of the rising edge D flip-flops is N, the number of the inverters is 3, the number of the NAND gates is 1, the first rising edge D flip-flop is connected with the N rising edge D flip-flop in sequence, the clock signal input of the first rising edge D flip-flop to the N-2 rising edge D flip-flop and the clock signal input of the N rising edge D flip-flop are CLKP, inverse relation exists between the clock signal input of the N-1 rising edge D flip-flop and the clock signal input of the CLKN, the input end of the first rising edge D flip-flop is connected with the output end of the NAND gate, the output end of the N-1 rising edge D flip-flop is connected with the input end of the NAND gate respectively, the output end of the first rising edge D flip-flop is connected with the input end of the second rising edge D flip-flop and the clock port of the N-1 rising edge D flip-flop respectively, and the output end of the second rising edge D flip-flop is connected with the output end of the rising edge D flip-flop respectively;
when the odd-number frequency dividing circuit is a divide-by-five frequency dividing circuit, the divide-by-five frequency dividing circuit comprises four rising edge D flip-flops, three inverters and a NAND gate;
the four rising edge D triggers output Data end Data temporarily at rising edges of the CLK clock signals respectively, the output of the remaining moments is kept unchanged, the output frequency of the four rising edge D triggers is one fifth of the CLK signals, and the signal duty ratio is 60%;
The clock signals of the first rising edge D trigger, the second rising edge D trigger and the fourth rising edge D trigger are input as CLKP, and the output ends of the first rising edge D trigger, the second rising edge D trigger and the fourth rising edge D trigger can have a phase difference of one CLK clock period in sequence.
2. The odd-numbered divider circuit of claim 1, wherein the reset state of each rising edge D flip-flop is a low level trigger.
3. The odd-numbered frequency dividing circuit according to claim 1, wherein when the reset signal is low, i.e., the circuit is in a reset state, each of the flip-flop outputs is low, and the nand gate output is high; when the reset signal goes from low to high, the circuit begins to operate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410564922.9A CN118157659B (en) | 2024-05-09 | 2024-05-09 | Odd-number frequency dividing circuit |
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| CN202410564922.9A CN118157659B (en) | 2024-05-09 | 2024-05-09 | Odd-number frequency dividing circuit |
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| CN118157659A CN118157659A (en) | 2024-06-07 |
| CN118157659B true CN118157659B (en) | 2024-07-30 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5365119A (en) * | 1991-08-15 | 1994-11-15 | Nokia Mobile Phones Ltd. | Circuit arrangement |
| CN103633995A (en) * | 2012-08-24 | 2014-03-12 | 比亚迪股份有限公司 | Frequency divider circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002344308A (en) * | 2001-05-18 | 2002-11-29 | Matsushita Electric Ind Co Ltd | Odd number divider and 90 degree phase shifter using it |
| US6566918B1 (en) * | 2001-08-28 | 2003-05-20 | Xilinx, Inc. | Divide-by-N clock divider circuit with minimal additional delay |
| US8081018B2 (en) * | 2008-08-21 | 2011-12-20 | Qualcomm Incorporated | Low power radio frequency divider |
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- 2024-05-09 CN CN202410564922.9A patent/CN118157659B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5365119A (en) * | 1991-08-15 | 1994-11-15 | Nokia Mobile Phones Ltd. | Circuit arrangement |
| CN103633995A (en) * | 2012-08-24 | 2014-03-12 | 比亚迪股份有限公司 | Frequency divider circuit |
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| CN118157659A (en) | 2024-06-07 |
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