CN118099300A - Method for adjusting etching type appearance of compound semiconductor multilayer structure - Google Patents
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- CN118099300A CN118099300A CN202410510691.3A CN202410510691A CN118099300A CN 118099300 A CN118099300 A CN 118099300A CN 202410510691 A CN202410510691 A CN 202410510691A CN 118099300 A CN118099300 A CN 118099300A
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- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
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- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/3065—Plasma etching; Reactive-ion etching
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Abstract
Description
技术领域Technical Field
本发明涉及半导体技术领域，具体为一种化合物半导体多层结构刻蚀型貌调节方法。The invention relates to the field of semiconductor technology, in particular to a method for adjusting etching morphology of a compound semiconductor multilayer structure.
背景技术Background technique
掩埋异质结构发光器件是由限定的电流限制区域，其将电流引导到结构内的光学有源层，在使用InGaAsP/InP/InGaAs材料的器件中，这种结构提供高可靠性、低阈值电流，良好的光场特性及光纤耦合效率，并且广泛用于一定范围的工作频率上的光纤通信系统中。Buried heterostructure light-emitting devices are composed of defined current confinement regions that guide current to the optically active layer within the structure. In devices using InGaAsP/InP/InGaAs materials, this structure provides high reliability, low threshold current, good light field characteristics and fiber coupling efficiency, and is widely used in fiber-optic communication systems over a certain range of operating frequencies.
实际在制作器件中，关于刻蚀型貌的控制是二次金属有机物气相沉积前一个关键的一环，很多文献报道掩埋异质结构发光器件多是选用全湿法腐蚀的方式，湿法刻蚀操作简易材料损伤小，能制作出相对平滑的台面，但是，全湿法刻蚀的均匀性差，宽度控制不易，而干法刻蚀工艺重复性高，均匀性好，但易产生材料损伤，所以应用于掩埋异质结构发光器件的台面制作，可以干法蚀刻后再进行湿法蚀刻以达到台面尺寸和型貌的控制；为此本发明提出一种化合物半导体多层结构刻蚀型貌调节方法，以解决上述提到的问题。In the actual device manufacturing, the control of etching morphology is a key link before secondary metal organic vapor deposition. Many literatures report that buried heterostructure light-emitting devices mostly use full wet etching. Wet etching is simple to operate and causes little material damage, and can produce relatively smooth mesas. However, full wet etching has poor uniformity and is difficult to control the width. The dry etching process has high repeatability and good uniformity, but is prone to material damage. Therefore, it is used in the production of mesas for buried heterostructure light-emitting devices. Dry etching can be followed by wet etching to achieve control of mesa size and morphology. To this end, the present invention proposes a compound semiconductor multilayer structure etching morphology adjustment method to solve the above-mentioned problems.
发明内容Summary of the invention
针对现有技术的不足，本发明提供了一种化合物半导体多层结构刻蚀型貌调节方法，解决了现有技术中使用全湿法刻蚀的均匀性差，宽度控制不易，而干法刻蚀工艺重复性高，均匀性好，但易产生材料损伤的问题。In view of the shortcomings of the prior art, the present invention provides a method for adjusting the etching morphology of a compound semiconductor multilayer structure, which solves the problem that the full wet etching used in the prior art has poor uniformity and difficult width control, while the dry etching process has high repeatability and good uniformity, but is prone to material damage.
为实现以上目的，本发明通过以下技术方案予以实现：一种化合物半导体多层结构刻蚀型貌调节方法，该方法具体包括以下步骤：To achieve the above objectives, the present invention is implemented through the following technical solutions: a method for adjusting the etching morphology of a compound semiconductor multilayer structure, the method specifically comprising the following steps:
S1、图形化掩膜在化合物半导体多层结构的表面；S1, patterning the mask on the surface of the compound semiconductor multilayer structure;
S2、无掩罩的多层结构在HBr和N2和其他少量的混合反应气体所产生的化学等离子体，在表面的垂直方向各向异性蚀刻该多层结构；S2, the multilayer structure without mask is subjected to chemical plasma generated by a mixed reaction gas of HBr and N2 and other small amounts, and the multilayer structure is anisotropically etched in a vertical direction on the surface;
其中，化合物半导体多层结构为：包括InP-p层、量子阱core层、InP-n层、衬底。The compound semiconductor multilayer structure includes an InP-p layer, a quantum well core layer, an InP-n layer, and a substrate.
优选的，所述图形化掩膜是PECVD设备沉积的 SiO2，用光刻技术在掩膜上制作光刻胶图形 ,掩膜的刻蚀采用反应离子刻蚀(RIE)，在有机化学去除光刻胶后，即得二氧化硅的图形掩膜在化合物半导体多层结构上。Preferably, the patterned mask is SiO 2 deposited by PECVD equipment, a photoresist pattern is made on the mask by photolithography, and the mask is etched by reactive ion etching (RIE). After the photoresist is removed by organic chemistry, a silicon dioxide pattern mask is obtained on the compound semiconductor multilayer structure.
优选的，还包括电感耦合等离子体两个独立的13.56MHz射频功率源射频电源RF1和RF2；Preferably, it also includes two independent 13.56 MHz radio frequency power sources RF1 and RF2 for inductively coupled plasma;
所述RF1 在反应室控制等离子体的产生，调节其密度；The RF1 controls the generation of plasma in the reaction chamber and adjusts its density;
所述RF2连接到反应室外的电感线圈上，提供了一个偏置电压给等离子体提供一定的能量控制等离子体轰击刻蚀表面的能量；The RF2 is connected to the inductor coil outside the reaction chamber, providing a bias voltage to provide a certain amount of energy to the plasma to control the energy of the plasma bombarding the etching surface;
溴基气体分子和产生的离子、自由基，进行物理式撞击溅蚀和化学刻蚀无掩膜的化合物半导体多层结构。Bromine-based gas molecules and the generated ions and free radicals perform physical impact sputtering and chemical etching of maskless compound semiconductor multilayer structures.
优选的，采用HBr:H2O2:H2O湿法刻蚀ICP后具有含铟多层InP层、InGaAsP层结构，获得梯型的、无刻痕光滑和干净的表面。Preferably, after wet etching of ICP using HBr:H 2 O 2 :H 2 O, a multilayer InP layer and an InGaAsP layer structure containing indium is obtained, and a trapezoidal, scratch-free, smooth and clean surface is obtained.
优选的，所述衬底包括InP、InGaAs和InGaAsP中的任意一种。Preferably, the substrate includes any one of InP, InGaAs and InGaAsP.
有益效果Beneficial Effects
本发明提供了一种化合物半导体多层结构刻蚀型貌调节方法。与现有技术相比具备以下有益效果：The present invention provides a method for adjusting the etching morphology of a compound semiconductor multilayer structure. Compared with the prior art, it has the following beneficial effects:
本发明采用 HBr:H2O2:H2O 作为化学刻蚀得到合理参数对含铟化合物半导体多层结构湿蚀刻型貌控制方法，得到了表面粗糙度小且可有效控制台面宽度，是合适半导体光电子器件的蚀刻工艺。The invention adopts HBr : H2O2 : H2O as chemical etching to obtain reasonable parameters for wet etching morphology control of indium compound semiconductor multilayer structure, obtains small surface roughness and can effectively control the table width, and is an etching process suitable for semiconductor optoelectronic devices.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1为本发明化合物半导体多层结构示意图；FIG1 is a schematic diagram of a compound semiconductor multilayer structure of the present invention;
图2为本发明二氧化硅的图形掩膜在化合物半导体多层结构示意图；FIG2 is a schematic diagram of a multilayer structure of a silicon dioxide pattern mask in a compound semiconductor according to the present invention;
图3为本发明中电感耦合等离子体的射频功率源射频电源示意图；FIG3 is a schematic diagram of a radio frequency power source of an inductively coupled plasma in the present invention;
图4为本发明具有含铟多层InP层、InGaAsP层结构的多层结构示意图。FIG. 4 is a schematic diagram of a multilayer structure of the present invention having a multilayer InP layer and an InGaAsP layer structure containing indium.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
请参阅图1-4，本申请提供了一种化合物半导体多层结构刻蚀型貌调节方法，该方法具体包括以下步骤：Referring to FIGS. 1-4 , the present application provides a method for adjusting etching morphology of a compound semiconductor multilayer structure, the method specifically comprising the following steps:
S1、图形化掩膜在化合物半导体多层结构的表面；S1, patterning the mask on the surface of the compound semiconductor multilayer structure;
其中，化合物半导体多层结构为：包括InP-p层、量子阱core层、InP-n层、衬底，如图1所示。The compound semiconductor multilayer structure includes an InP-p layer, a quantum well core layer, an InP-n layer, and a substrate, as shown in FIG1 .
所述衬底包括InP、InGaAs和InGaAsP中的任意一种。The substrate includes any one of InP, InGaAs and InGaAsP.
所述图形化掩膜是PECVD设备沉积的 SiO2，用光刻技术在掩膜上制作光刻胶图形,掩膜的刻蚀采用反应离子刻蚀(RIE)，在有机化学去除光刻胶后，即得二氧化硅的图形掩膜在化合物半导体多层结构上(晶圆)，如图2所示。The patterned mask is SiO 2 deposited by PECVD equipment. A photoresist pattern is made on the mask using photolithography technology. The mask is etched using reactive ion etching (RIE). After the photoresist is removed by organic chemistry, a silicon dioxide pattern mask is obtained on the compound semiconductor multilayer structure (wafer), as shown in FIG2 .
S2、无掩罩的多层结构在HBr和N2和其他少量的混合反应气体所产生的化学等离子体，在表面的垂直方向各向异性蚀刻该多层结构；S2, the multilayer structure without mask is subjected to chemical plasma generated by a mixed reaction gas of HBr and N2 and other small amounts, and the multilayer structure is anisotropically etched in a vertical direction on the surface;
采用HBr:H2O2:H2O湿法刻蚀ICP后具有含铟多层InP层、InGaAsP层结构，获得梯型的、无刻痕光滑和干净的表面，如图4所示。After the ICP is wet-etched with HBr:H 2 O 2 :H 2 O, a multi-layer InP layer and an InGaAsP layer structure containing indium is obtained, and a trapezoidal, scratch-free, smooth and clean surface is obtained, as shown in FIG4 .
还包括电感耦合等离子体两个独立的13.56MHz射频功率源射频电源RF1 和RF2；如图3所示；It also includes two independent 13.56MHz radio frequency power sources RF1 and RF2 for inductively coupled plasma, as shown in FIG3 ;
所述RF1 在反应室控制等离子体的产生，调节其密度；The RF1 controls the generation of plasma in the reaction chamber and adjusts its density;
所述RF2连接到反应室外的电感线圈上，提供了一个偏置电压给等离子体提供一定的能量控制等离子体轰击刻蚀表面的能量；The RF2 is connected to the inductor coil outside the reaction chamber, providing a bias voltage to provide a certain amount of energy to the plasma to control the energy of the plasma bombarding the etching surface;
溴基气体分子和产生的离子、自由基，进行物理式撞击溅蚀和化学刻蚀无掩膜的化合物半导体多层结构。Bromine-based gas molecules and the generated ions and free radicals perform physical impact sputtering and chemical etching of maskless compound semiconductor multilayer structures.
上述公式中的部分数据均是去其纲量进行数值计算，同时本说明书中未作详细描述的内容均属于本领域技术人员公知的现有技术。Some of the data in the above formulas are dimensionless and numerically calculated. Meanwhile, the contents not described in detail in this specification belong to the prior art known to those skilled in the art.
以上实施例仅用以说明本发明的技术方法而非限制，尽管参照较佳实施例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方法进行修改或等同替换，而不脱离本发明技术方法的精神和范围。The above embodiments are only used to illustrate the technical method of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical method of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical method of the present invention.
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| JPH1012970A (en) * | 1996-06-20 | 1998-01-16 | Nec Corp | Semiconductor device and its manufacture |
| US5968845A (en) * | 1996-02-13 | 1999-10-19 | Matsushita Electric Industrial Co., Ltd. | Method for etching a compound semiconductor, a semi-conductor laser device and method for producing the same |
| CN1669128A (en) * | 2002-07-19 | 2005-09-14 | 优利讯美国有限公司 | High temperature anisotropic etching of multi-layer structures |
| US20200058773A1 (en) * | 2018-08-14 | 2020-02-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of fabricating trimmed fin and fin structure |
| CN112582262A (en) * | 2020-11-27 | 2021-03-30 | 中国电子科技集团公司第十三研究所 | Non-selective wet etching method for multilayer material and application thereof |
| US20240006159A1 (en) * | 2022-06-30 | 2024-01-04 | Spts Technologies Limited | Post-processing of Indium-containing Compound Semiconductors |
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- 2024-04-26 CN CN202410510691.3A patent/CN118099300A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5968845A (en) * | 1996-02-13 | 1999-10-19 | Matsushita Electric Industrial Co., Ltd. | Method for etching a compound semiconductor, a semi-conductor laser device and method for producing the same |
| JPH1012970A (en) * | 1996-06-20 | 1998-01-16 | Nec Corp | Semiconductor device and its manufacture |
| CN1669128A (en) * | 2002-07-19 | 2005-09-14 | 优利讯美国有限公司 | High temperature anisotropic etching of multi-layer structures |
| US20200058773A1 (en) * | 2018-08-14 | 2020-02-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of fabricating trimmed fin and fin structure |
| CN112582262A (en) * | 2020-11-27 | 2021-03-30 | 中国电子科技集团公司第十三研究所 | Non-selective wet etching method for multilayer material and application thereof |
| US20240006159A1 (en) * | 2022-06-30 | 2024-01-04 | Spts Technologies Limited | Post-processing of Indium-containing Compound Semiconductors |
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Application publication date: 20240528 |