CN117894850B - LDMOS devices with HCI resistance - Google Patents

Abstract

The present application relates to the field of semiconductor technology, and discloses an LDMOS device resistant to HCI effect, comprising: a substrate, wherein a buried region is provided in the substrate or an epitaxial layer of the substrate; a drift region, wherein the drift region is provided in the substrate and above the buried region, and a body region is provided on the drift region; a gate structure, wherein the gate structure is provided on the substrate and spans the drift region and the body region; a field oxygen, wherein the field oxygen is provided on the substrate and connected to the gate structure, and a Si-F bond region for passivating interface dangling bonds is provided between the field oxygen and the substrate, wherein the Si-F bond region is formed by ion implantation of F element at the interface between the field oxygen and the substrate; and a self-aligned isolation layer, wherein the self-aligned isolation layer is provided on the substrate and used to cover the active region of the LDMOS device, and partially covers the polysilicon surface of the gate structure. The present application improves the ability of the LDMOS device to resist HCI, thereby improving the reliability of the LDMOS device.

Description

LDMOS devices with HCI resistance

Technical Field

The present application relates to the field of semiconductor technology, and in particular to an LDMOS device that is resistant to HCI effects.

Background technique

In the semiconductor manufacturing process, LDMOS devices are a type of MOSFET devices commonly used for power amplification. In LDMOS devices, due to high voltage application, the electric field will form a strong gradient on the surface. When the electric field strength is high enough, carriers (such as electrons or holes) will obtain enough energy to overcome the energy band barrier of the insulating layer or oxide layer and merge into it. This phenomenon is called hot carrier injection (HCI). The HCI effect will lead to device performance degradation and reliability problems. When carriers are injected into the insulating layer or oxide layer, they may cause charge accumulation or voltage shift, thereby changing the threshold voltage and other electrical parameters of the device, which may lead to increased leakage current of the device, threshold voltage drift and other irreversible effects, ultimately affecting the performance and life of the device. Since the drift region of the LDMOS device has a higher electric field strength distribution, a larger saturation current and a higher impact ionization rate, the HCI effect becomes more severe. Therefore, how to design an LDMOS device with better resistance to the HCI effect has become a technical problem that needs to be solved urgently.

Summary of the invention

In view of this, the present application provides an LDMOS device resistant to HCI effect, so as to improve the ability of the LDMOS device to resist HCI and improve the reliability of the LDMOS device.

To achieve the above objectives, the technical solutions adopted are:

An LDMOS device resistant to HCI effect, comprising:

A substrate, wherein a buried region is provided in the substrate or an epitaxial layer of the substrate;

A drift region, wherein the drift region is disposed in the substrate and above the buried layer region, and a body region is disposed on the drift region;

a gate structure, the gate structure being disposed on the substrate and spanning the drift region and the body region;

A field oxygen, the field oxygen is disposed on the substrate and connected to the gate structure, a Si-F bond region for passivating interface dangling bonds is disposed between the field oxygen and the substrate, and the Si-F bond region is formed by ion implantation of an F element at an interface between the field oxygen and the substrate;

A self-aligned isolation layer is disposed on the substrate and is used to cover the active area of the LDMOS device and partially cover the polysilicon surface of the gate structure.

The present application is further configured as follows: it also includes a first well region and a second well region provided in the substrate, the first well region and the second well region are arranged at intervals, the first well region is close to the drift region, and maintains a distance from the drift region.

The present application is further configured as follows: an STI isolation structure is provided on the substrate, and the STI isolation structure is arranged between the first well region and the drift region, and between the first well region and the second well region.

The present application is further configured as follows: the upper surface of the body region has a first doped region, the upper surface of the drift region and near the STI isolation structure has a second doped region, the upper surface of the first well region has a third doped region, and the upper surface of the second well region has a fourth doped region.

The present application is further configured as follows: the gate structure includes a gate oxide layer and a polysilicon layer sequentially stacked on the substrate, and sidewall structures are provided on the sides of the gate oxide layer and the polysilicon layer.

The present application is further configured as follows: the self-aligned isolation layer covers upper surfaces of the first doping region, the second doping region, the third doping region, and the fourth doping region, respectively.

The present application is further configured as follows: the forming material of the self-aligned isolation layer includes SiO2, and the SiO2 covers the active area of the LDMOS device and partially covers the polysilicon surface of the gate structure through a PECVD deposition process.

The present application is further configured as follows: the first well region and the second well region are symmetrically arranged on both sides of the drift region, an isolation region is also provided in the substrate, the isolation region is located between the drift region and the buried layer region, and both ends of the isolation region extend to the first well region respectively.

The present application is further configured as follows: the substrate, the body region and the first well region are of a first conductivity type, and the buried layer region, the drift region and the second well region are of a second conductivity type.

The present application is further configured as follows: when the LDMOS device is an N-type LDMOS device, the first conductivity type is P-type and the second conductivity type is N-type; when the LDMOS device is a P-type LDMOS device, the first conductivity type is N-type and the second conductivity type is P-type.

In summary, compared with the prior art, the present application discloses an LDMOS device resistant to HCI effect, wherein a buried region is provided in a substrate or an epitaxial layer of the substrate, a drift region is located above the buried region in the substrate, and a body region is provided on the drift region, and a gate structure is provided on the substrate and spans the drift region and the body region, wherein a field oxygen is provided on the substrate and connected to the gate structure, and a Si-F bond region for passivating interface dangling bonds is provided between the field oxygen and the substrate, and the Si-F bond region is formed by ion implantation of the F element at the interface between the field oxygen and the substrate, and a self-aligned isolation layer is provided on the substrate and is used to cover the active region of the LDMOS device and partially cover the polysilicon surface of the gate structure, that is, through the above-mentioned arrangement, the ability of the LDMOS device to resist HCI is improved, thereby improving the reliability of the LDMOS device.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

FIG1 is a schematic structural diagram of a first LDMOS device resistant to HCI effect according to the present embodiment;

FIG2 is a schematic structural diagram of a second LDMOS device for resisting HCI effect according to the present embodiment;

FIG. 3 is a hot carrier injection-static drain current degradation relationship table of this embodiment.

Description of the drawings: 1. Substrate; 2. Epitaxial layer; 21. First well region; 22. Second well region; 23. STI isolation structure; 24. Isolation region; 3. Buried layer region; 4. Drift region; 5. Body region; 6. Gate structure; 61. Gate oxide layer; 62. Polysilicon layer; 63. Sidewall structure; 7. Field oxygen; 8. Si-F bond region; 9. Self-aligned isolation layer; 101. First doped region; 102. Second doped region; 103. Third doped region; 104. Fourth doped region.

Detailed ways

Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.

It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context in the specific embodiment.

It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application, and have no specific meanings. Therefore, "module", "component" or "unit" can be used in a mixed manner.

In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the description order of the following embodiments is not intended to limit the priority order of the embodiments.

As described in the background technology, in the related art, the HCI effect can lead to degradation of device performance and reliability problems. When carriers are injected into the insulating layer or the oxide layer, charge accumulation or voltage shift may be caused, thereby changing the threshold voltage and other electrical parameters of the device, which may lead to increased leakage current of the device, threshold voltage drift and other irreversible effects, ultimately affecting the performance and life of the device. Since the drift region of the LDMOS device has a higher electric field strength distribution, a larger saturation current and a higher collision ionization rate, the HCI effect becomes more severe. Based on this, the present embodiment discloses an LDMOS device that is resistant to the HCI effect.

1 and 2 , the LDMOS device resistant to HCI effect of the present embodiment includes a substrate 1 , a drift region 4 , a gate structure 6 , a field oxide 7 , a self-aligned isolation layer 9 , and the like.

Specifically, the material of the substrate 1 of the present embodiment can be single crystal silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium and the like. The substrate 1 can also be a silicon germanium substrate, a III-V group element compound substrate, a silicon carbide substrate or its stacked structure, or a silicon-on-insulator structure, or a diamond substrate or other semiconductor material substrates known to those skilled in the art.

In the specific implementation process, a buried region 3 is provided in the substrate 1, a drift region 4 is provided in the substrate 1 and is located above the buried region 3, and a body region 5 is provided on the drift region 4, that is, the introduction of the buried region 3 can help control the electric field distribution in the drift region 4. For example, by adjusting the doping concentration and position of the buried region 3, the electric field gradient can be changed to make it more evenly distributed and reduce the electric field concentration phenomenon, which helps to reduce the electric field strength in the high electric field area and reduce the electric field induced carrier injection effect and breakdown risk. At the same time, the existence of the buried region 3 can increase the resistance of the drift region 4 and reduce the leakage current in the drift region 4. The resistance of the buried region 3 limits the current distribution in the drift region 4, which helps to improve the switching characteristics of the device and reduce power consumption. The buried region 3 can provide electrical isolation for the drift region 4 to prevent lateral diffusion of current.

Among them, the body region 5 on the drift region 4 is the main current channel of the LDMOS device. By controlling the voltage and doping concentration of the body region 5, the current flow of the device can be effectively controlled, and the device's tolerance to high-power operations can be enhanced, thereby improving the device's power handling capability and reliability.

The gate structure 6 of this embodiment is arranged on the substrate 1 and spans the drift region 4 and the body region 5. Specifically, the gate structure 6 may include a gate oxide layer 61 and a polysilicon layer 62 stacked in sequence on the substrate 1, and sidewall structures 63 are provided on the sides of the gate oxide layer 61 and the polysilicon layer 62 to perform the gate function.

It should be noted that the field oxygen 7 of this embodiment is arranged on the substrate 1 and connected to the gate structure 6, wherein a Si-F bond region 8 for passivating interface dangling bonds is provided between the field oxygen 7 and the substrate 1, and the Si-F bond region 8 is formed by ion implantation of the F element at the interface between the field oxygen 7 and the substrate 1.

In some embodiments, an epitaxial layer 2 can be formed on the substrate 1, and the epitaxial layer 2 and the buried layer 3 are stacked in sequence on the substrate 1. At this time, the above-mentioned functional layers of the semiconductor device can all be formed on the epitaxial layer 2. Specifically, the formation of the epitaxial layer 2 on the substrate 1 can be achieved through chemical vapor deposition or molecular beam epitaxy process to achieve large-area and uniform-thickness epitaxial layer growth.

It can be understood that the ability of the device to resist the HCI effect is highly correlated with the interface state of the device. The more interface states (referring to the energy level or charge state at the interface between two different materials or different regions. When two materials contact to form an interface, some additional energy levels or charge distributions will be formed due to lattice mismatch, chemical reaction or defects) there are, the worse the ability to resist the HCI effect. For the interface between the field oxygen 7 and the substrate 1, this embodiment performs ion implantation of F (fluorine) element to form a Si-F bond region 8, that is, the existence of the Si-F bond region 8 is intended to passivate the interface between the field oxygen 7 and the substrate 1, which helps to reduce the interface state density and improve the interface quality of the material to reduce charge capture and leakage current, thereby improving the ability of the device to resist the HCI effect.

Among them, dangling bonds usually appear on the surface or interface, especially in the passivation process of the material surface. When the material surface is treated or a passivator is applied, atoms or molecules form chemical bonds with the surface. In this process, some atoms may lose their bonding partners with neighboring atoms, resulting in the formation of dangling bonds. The existence of dangling bonds may cause instability of the surface or interface because the atoms on the dangling bonds tend to form new chemical bonds with other atoms. In this embodiment, during the process of passivating the interface, ion implantation of F elements is performed to bond with the atoms on the dangling bonds to stabilize the surface or interface and reduce the influence of dangling bonds, thereby improving the interface stability of the field oxygen 7 and the substrate 1 and improving the performance of the material, thereby improving the ability of the device to resist the HCI effect.

Referring to FIG. 3 , FIG. 3 is a hot carrier injection-static drain current degradation relationship table of the present embodiment, wherein the ordinate is Idlin Shift /%, i.e., the percentage change of the static drain current, and the abscissa is Stress Time /s, i.e., the duration of the hot carrier injection. #20 is the LDMOS device of the present embodiment that uses F element ion implantation to form the Si-F bond region 8, and #5 is a conventional LDMOS device in the related art. It can be clearly understood that the present embodiment greatly improves the ability of the LDMOS device to resist HCI.

After the Si—F bond region 8 is formed, the present embodiment is designed to have a self-aligned isolation layer 9 disposed on the substrate 1 and used to cover the active region of the LDMOS device.

Furthermore, the self-aligned isolation layer 9 also partially covers the polysilicon surface of the gate structure 6 .

It should be noted that the self-aligned barrier layer (SAB) isolates the active area of the LDMOS device that does not need to form metal silicide from the surrounding area, which helps to reduce mutual interference between devices and improve the performance and reliability of the device. It can also provide electrical isolation between the gate and other electrodes (such as the source and drain), thereby preventing leakage current and crosstalk between circuits, and improving the working stability and reliability of the device. At the same time, the self-aligned isolation layer 9 of this embodiment can also modulate the electric field distribution inside the device. According to its distribution position, the electric field peak between the drift region 4 and the active region can be reduced, thereby improving the voltage resistance and reliability of the device.

In the specific implementation process, the LDMOS device with resistance to HCI effect also includes a first well region 21 and a second well region 22 arranged in the substrate 1, and the first well region 21 and the second well region 22 are arranged at intervals, wherein the first well region 21 is close to the drift region 4 and maintains a distance from the drift region 4.

Through the design of the first well region 21 and the second well region 22, the charge storage and control of the LDMOS device can be used, and the operating voltage range of the device can also be adjusted, and the threshold voltage and turn-on voltage of the device can be changed. At the same time, the first well region 21 and the second well region 22 also affect the electric field distribution in the drift region 4, that is, by adjusting the potential and shape of the well region, the intensity and distribution of the electric field can be controlled, thereby affecting the charge distribution and current flow in the drift region 4.

Furthermore, an STI isolation structure 23 is provided on the substrate 1, and the STI isolation structure 23 is arranged between the first well region 21 and the drift region 4, and between the first well region 21 and the second well region 22. That is, the STI isolation structure 23 provides physical isolation between the first well region 21 and the drift region 4, and between the first well region 21 and the second well region 22, thereby preventing lateral diffusion of charge and current, thereby reducing current crosstalk and interference, and improving the noise characteristics, working stability and anti-interference ability of the device.

Regarding the formation of the STI isolation structure 23, it may specifically include: photolithography and etching the substrate 1 to define the position and shape of the STI isolation structure 23 on the substrate 1, that is, etching a series of shallow and wide grooves on the substrate 1, which will be used to isolate different devices and can be used to isolate the active area of the substrate 1; cleaning the STI isolation structure 23, oxidizing it in the STI isolation structure 23 to form a sacrificial oxide layer, and flattening it through a CMP chemical mechanical polishing process, so that the STI isolation structure 23 is flush with the surface around the substrate 1, wherein the STI isolation structure 23 is cleaned to remove surface particles, metal ions, etc., and optional cleaning methods include acid cleaning, solvent cleaning, and gas purging, etc. The cleaning agent may include a combination of one or more of sulfuric acid, hydrochloric acid, nitric acid, and hydrofluoric acid. That is, the acidic solution may include any one of the above solutions, or may also include a combination of any two or more of the above solutions, which is not limited in this embodiment.

In the specific implementation process, the upper surface of the body region 5 has a first doped region 101, the upper surface of the drift region 4 and near the STI isolation structure 23 has a second doped region 102, the upper surface of the first well region 21 has a third doped region 103, and the upper surface of the second well region 22 has a fourth doped region 104. During the normal operation of the LDMOS device, the first doped region 101 and the second doped region 102 can be regarded as source and drain electrodes of the LDMOS device. For example, the first doped region 101 can be a source, and the second doped region 102 can be a drain, so as to cooperate with the gate structure 6 to exert the function of the LDMOS device.

Furthermore, the aforementioned self-aligned isolation layer 9 is arranged on the substrate 1 and is used to cover the active area of the LDMOS device. The specific distribution can be: the self-aligned isolation layer 9 covers the upper surfaces of the first doping region 101, the second doping region 102, the third doping region 103 and the fourth doping region 104 respectively.

Among them, the forming material of the self-aligned isolation layer 9 includes SiO2, and SiO2 can be covered on the active area of the LDMOS device and partially covers the polysilicon surface of the gate structure 6 through a PECVD (Plasma-Enhanced Chemical Vapor Deposition) thin film deposition process, and PECVD has the characteristics of low temperature deposition, good uniformity, suitability for large-area deposition, and good coverage on complex structures.

It should be noted that the LDMOS device of this embodiment can be symmetrically arranged with respect to some features in structural design. For example, with the body region 5 as the center, the drift region 4, the STI isolation structure 23, the first well region 21 and the second well region 22 can be symmetrically arranged on both sides of the body region 5 in the substrate 1, and the gate structure 6, the field oxide 7 and the self-aligned isolation layer 9 can be symmetrically arranged on the substrate 1.

That is, the first well region 21 and the second well region 22 may be symmetrically arranged on both sides of the drift region 4 .

Among them, an isolation region 24 is also provided in the substrate 1, and the isolation region 24 is located between the drift region 4 and the buried region 3, and the two ends of the isolation region 24 extend to the first well region 21 respectively, which is used to form a physical isolation between the drift region 4 and the buried region 3, and prevent the lateral diffusion of charges and currents between different regions, thereby reducing the crosstalk and interference of the current.

In this embodiment, the substrate 1, body region 5 and first well region 21 may be of the first conductivity type, and the buried region 3, drift region 4 and second well region 22 may be of the second conductivity type. Specifically, when the LDMOS device is an N-type LDMOS device, the first conductivity type is P-type and the second conductivity type is N-type. When the LDMOS device is a P-type LDMOS device, the first conductivity type is N-type and the second conductivity type is P-type.

In summary, the present embodiment discloses an LDMOS device resistant to HCI effect, wherein a buried region 3 is provided in a substrate 1, a drift region 4 is located above the buried region 3 in the substrate 1, a body region 5 is provided on the drift region 4, a gate structure 6 is provided on the substrate 1 and spans the drift region 4 and the body region 5, wherein a field oxide 7 is provided on the substrate 1 and connected to the gate structure 6, a Si-F bond region 8 for passivating interface dangling bonds is provided between the field oxide 7 and the substrate 1, the Si-F bond region 8 is formed by ion implantation of F element at the interface between the field oxide 7 and the substrate 1, a self-aligned isolation layer 9 is provided on the substrate 1 and is used to cover the active region of the LDMOS device and partially cover the polysilicon surface of the gate structure, thereby, the interface dangling bonds between the field oxide 7 and the substrate 1 are passivated by the Si-F bond region 8, thereby optimizing the interface state between the field oxide 7 and the substrate 1, improving the ability of the LDMOS device to resist HCI, and thus improving the reliability and life of the LDMOS device.

The above is a detailed introduction to the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the core idea of the present application. At the same time, for technical personnel in this field, according to the idea of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims (10)

1. An LDMOS device resistant to HCI effects, comprising:

A substrate, wherein a buried layer region is arranged in the substrate, and the substrate is made of monocrystalline silicon, silicon carbide or silicon germanium;

the drift region is arranged in the substrate and above the buried layer region, and a body region is arranged on the drift region;

A gate structure disposed on the substrate and crossing the drift region and the body region;

The field oxide is arranged on the substrate and connected with the grid structure, a Si-F bond area for passivating an interface suspension bond is arranged between the field oxide and the substrate, and the Si-F bond area is formed by carrying out ion implantation of F element at the interface of the field oxide and the substrate;

and the self-aligned isolation layer is arranged on the substrate and used for covering the active area of the LDMOS device and partially covering the polysilicon surface of the grid structure.

2. The HCI effect-resistant LDMOS device of claim 1, further comprising a first well region and a second well region disposed within the substrate, the first well region and the second well region being spaced apart, the first well region being adjacent to and spaced apart from the drift region.

3. The HCI effect-resistant LDMOS device of claim 2, wherein an STI isolation structure is disposed on the substrate, the STI isolation structure being disposed between the first well region and the drift region, and between the first well region and the second well region.

4. The LDMOS device of claim 3, wherein the upper surface of the body region has a first doped region, the upper surface of the drift region has a second doped region adjacent to the STI isolation structure, the upper surface of the first well region has a third doped region, and the upper surface of the second well region has a fourth doped region.

5. The LDMOS device as recited in claim 4, wherein said gate structure comprises a gate oxide layer and a polysilicon layer sequentially stacked on said substrate, wherein side walls are provided on sides of said gate oxide layer and said polysilicon layer.

6. The LDMOS device of claim 5, wherein said self-aligned spacer layer covers upper surfaces of said first doped region, said second doped region, said third doped region and said fourth doped region, respectively.

7. The LDMOS device of claim 1, wherein the self-aligned spacer layer comprises a material comprising SiO2, wherein the SiO2 is deposited by a PECVD deposition process over the active area of the LDMOS device and partially over the polysilicon surface of the gate structure.

8. The LDMOS device of claim 3, wherein the first well region and the second well region are symmetrically arranged at two sides of the drift region, wherein an isolation region is further arranged in the substrate, the isolation region is located between the drift region and the buried layer region, and two ends of the isolation region extend to the first well region respectively.

9. The HCI effect-resistant LDMOS device of claim 2, wherein the substrate, the body region, and the first well region are of a first conductivity type, and the buried layer region, the drift region, and the second well region are of a second conductivity type.

10. The HCI effect-resistant LDMOS device of claim 9, wherein the first conductivity type is P-type when the LDMOS device is an N-type LDMOS device, the second conductivity type is N-type, and wherein the first conductivity type is N-type and the second conductivity type is P-type when the LDMOS device is a P-type LDMOS device.