CN118431290B - Groove type power device, manufacturing method, power module, conversion circuit and vehicle - Google Patents
Groove type power device, manufacturing method, power module, conversion circuit and vehicle Download PDFInfo
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- CN118431290B CN118431290B CN202410514565.5A CN202410514565A CN118431290B CN 118431290 B CN118431290 B CN 118431290B CN 202410514565 A CN202410514565 A CN 202410514565A CN 118431290 B CN118431290 B CN 118431290B
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/01—Manufacture or treatment
- H10D12/031—Manufacture or treatment of IGBTs
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- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
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- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
- H10D62/8325—Silicon carbide
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- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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- H—ELECTRICITY
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- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
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Abstract
The invention discloses a groove type power device, a preparation method, a power module, a conversion circuit and a vehicle, wherein the groove type power device comprises a substrate; the semiconductor epitaxial layer is positioned on one side of the substrate, the grid electrode groove is formed in the semiconductor epitaxial layer in a transmission mode from the surface of one side, far away from the substrate, of the semiconductor epitaxial layer, the groove grid structure is positioned in the grid electrode groove and comprises a polycrystalline silicon grid electrode, a first grid electrode insulating layer positioned at the bottom of the polycrystalline silicon grid electrode and a second grid electrode insulating layer positioned on the side wall of the polycrystalline silicon grid electrode, the dielectric constant of the material of the first grid electrode insulating layer is larger than or equal to that of the material of the second grid electrode insulating layer, and the dielectric constant of the material of the first grid electrode insulating layer is larger than that of silicon oxide. The technical scheme provided by the embodiment of the invention improves the problem of breakdown of the gate insulation layer in the trench type power device and ensures the control capability of the gate to the device.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductor devices, in particular to a trench type power device, a manufacturing method, a power module, a conversion circuit and a vehicle.
Background
Silicon carbide (SiC) has excellent physical and electrical characteristics as a representative of third generation semiconductor materials. Compared with silicon materials, the SiC material has the advantages of large forbidden bandwidth, high breakdown electric field, high heat conductivity, high electron saturation rate, strong radiation resistance and the like, so that a semiconductor device prepared from the SiC material can stably operate at a higher temperature and is also suitable for high-voltage and high-frequency scenes.
SiC MOSFETs undergo a planar-to-trench process, by modifying the gate structure, the flow of current on the gate changes from planar to vertical. In the related art, by adding a source trench etching, ion implantation is performed on the bottom and the side wall of the source trench to obtain a P-well region with a sufficient depth, and the structure is named as a double trench structure (DT-MOS). Compared with a non-shielding structure, the double-groove structure can reduce the grid oxygen electric field, improve the voltage resistance and reduce the specific on-resistance. The dual trench structure achieves a superior balance of both from a structural simplicity and process complexity perspective, as well as from a device characteristic perspective. The proposal of the structure also makes the commercialization development of the SiC trench gate MOSFET device take the first step.
However, the conventional trench type power device has the problem of unstable threshold voltage. Particularly, in the double-groove structure, under the blocking state, the electric field concentration effect at the bottom of the gate groove is very easy to cause the electric field in the gate oxide layer (gate insulating layer) to be intensified, so that the gate oxide layer at the bottom of the gate groove breaks down in advance. In order to avoid the advanced breakdown of the gate oxide layer at the bottom of the gate trench, the thickness of the gate oxide layer at the bottom of the gate trench needs to be increased, but the method is limited in the current process, the oxidation rate has an important relation with the crystal plane orientation of SiC, and the thickness of the sidewall oxide layer is higher than that of the bottom oxide layer in the self-oxidation process of the trench wall of the gate trench, so that the electric field effect at the trench is weakened, and the control capability of the gate to the device is reduced. Therefore, how to improve the breakdown problem of the gate insulation layer in the trench type power device and ensure the control capability of the gate to the device is a technical problem to be solved by the person in the field.
Disclosure of Invention
The embodiment of the invention provides a groove type power device, a preparation method, a power module, a conversion circuit and a vehicle, so that the problem of breakdown of a gate insulating layer in the groove type power device is solved, and the control capability of the gate to the device is ensured.
According to an aspect of the present invention, there is provided a trench type power device including:
a substrate;
A semiconductor epitaxial layer located on one side of the substrate;
the grid electrode groove is positioned on the surface of one side of the semiconductor epitaxial layer away from the substrate;
the gate structure comprises a polysilicon gate, a first gate insulating layer positioned at the bottom of the polysilicon gate and a second gate insulating layer positioned on the side wall of the polysilicon gate;
the dielectric constant of the material of the first gate insulating layer is greater than or equal to that of the material of the second gate insulating layer, and the dielectric constant of the material of the first gate insulating layer is greater than that of silicon oxide.
Optionally, the dielectric constant of the material of the second gate insulating layer is greater than the dielectric constant of silicon oxide;
the thickness of the first gate insulating layer is larger than that of the second gate insulating layer positioned on the side wall of the polysilicon gate.
Optionally, the trench power device further includes:
a third gate insulating layer located between the first gate insulating layer and the polysilicon gate;
The third gate insulating layer and the second gate insulating layer are made of the same material, and the third gate insulating layer and the second gate insulating layer are integrally arranged.
Optionally, the material of the second gate insulating layer includes silicon oxide.
Optionally, along the direction of the semiconductor epitaxial layer away from the substrate, the semiconductor outer layer sequentially comprises a first conductive type first doping region, a second conductive type first doping region and a first conductive type second doping region;
n-type doped ions are doped in the first conductive type first doped region and the first conductive type second doped region;
Or the first conductive type first doped region and the first conductive type second doped region are doped with P-type doped ions, and the second conductive type first doped region is doped with N-type doped ions.
Optionally, the trench power device further includes:
the source electrode grooves are positioned on two opposite sides of the grid electrode groove and are arranged at intervals with the grid electrode groove;
The source structure comprises a polysilicon source, a first source insulating layer positioned at the bottom of the polysilicon source and a second source insulating layer positioned on the side wall of the polysilicon source, wherein the first source insulating layer is made of the same material as the first gate insulating layer;
the semiconductor epitaxial layer further comprises a second conductive type second doping region, and the second conductive type second doping region is located at the bottom and the side wall of the groove source structure.
Optionally, the trench power device further includes:
An interlayer insulating layer which is positioned on one side of the semiconductor epitaxial layer far away from the substrate and covers the trench gate structure;
a source electrode located on one side of the interlayer insulating layer away from the substrate, and on the surface of the semiconductor epitaxial layer uncovered by the interlayer insulating layer;
And the drain electrode is positioned on the surface of the substrate far away from the semiconductor epitaxial layer.
According to another aspect of the present invention, there is provided a method for manufacturing a trench type power device, including:
Providing a substrate;
forming a semiconductor epitaxial layer on one side of the substrate;
Forming a grid groove on the surface of one side of the semiconductor epitaxial layer far away from the substrate;
and forming a trench gate structure in the gate trench, wherein the trench gate structure comprises a polysilicon gate, a first gate insulating layer positioned at the bottom of the polysilicon gate and a second gate insulating layer positioned on the side wall of the polysilicon gate, the dielectric constant of the material of the first gate insulating layer is greater than or equal to that of the material of the second gate insulating layer, and the dielectric constant of the material of the first gate insulating layer is greater than that of silicon oxide.
Optionally, forming a trench gate structure in the gate trench includes:
Forming a mask layer on the surface of the semiconductor epitaxial layer far away from the substrate and the groove wall of the gate groove;
Etching the mask layer at the bottom of the gate trench to expose the bottom of the gate trench;
forming a first grid initial insulating layer on the surface of one side of the mask layer far away from the substrate, the surface of the mask layer in the grid groove far away from the side wall of the grid groove and the bottom of the grid groove;
coating photoresist so that the photoresist covers the surface of the first grid initial insulating layer, which is far away from the side of the substrate, and filling the grid groove;
patterning the photoresist to form a plurality of openings exposing the first gate initial insulating layer away from the surface of one side of the substrate;
Etching the first gate initial insulating layer and at least part of the mask layer based on the opening in the photoresist;
Removing the photoresist, and removing the mask layer and the first grid initial insulating layer positioned on the surface of the mask layer through corrosive liquid based on an ultrasonic oscillation mode so as to form a first grid insulating layer at the bottom of the grid groove;
forming a second grid initial insulating layer on the surface of one side of the semiconductor epitaxial layer far away from the substrate, the side wall of the grid groove and the surface of the first grid insulating layer, wherein the dielectric constant of the material of the second grid initial insulating layer is larger than that of silicon oxide;
Removing the second grid initial insulating layer positioned on the surface of one side of the semiconductor epitaxial layer far away from the substrate through dry etching, and removing the second grid initial insulating layer of the first grid insulating layer far away from the surface of one side of the substrate so as to form a second grid insulating layer on the side wall of the grid groove;
and filling a polysilicon material in the gate trench to form a polysilicon gate.
Optionally, forming a trench gate structure in the gate trench includes:
Forming a mask layer on the surface of the semiconductor epitaxial layer far away from the substrate and the groove wall of the gate groove;
Etching the mask layer at the bottom of the gate trench to expose the bottom of the gate trench;
forming a first grid initial insulating layer on the surface of one side of the mask layer far away from the substrate, the surface of the mask layer in the grid groove far away from the side wall of the grid groove and the bottom of the grid groove;
coating photoresist so that the photoresist covers the surface of the first grid initial insulating layer, which is far away from the side of the substrate, and filling the grid groove;
patterning the photoresist to form a plurality of openings exposing the first gate initial insulating layer away from the surface of one side of the substrate;
Etching the first gate initial insulating layer and at least part of the mask layer based on the opening in the photoresist;
removing the photoresist, and removing the mask layer and the first grid initial insulating layer positioned on the surface of the mask layer through corrosive liquid based on an ultrasonic oscillation mode so as to form a first grid insulating layer at the bottom of the polysilicon grid;
forming a second grid initial insulating layer on the surface of one side of the semiconductor epitaxial layer far away from the substrate, the side wall of the grid groove and the surface of the first grid insulating layer, wherein the dielectric constant of the material of the second grid initial insulating layer is larger than that of silicon oxide;
filling photoresist in the gate trench to cover a second gate initial insulating layer positioned in the gate trench;
Removing the second gate initial insulating layer on the surface of the semiconductor epitaxial layer, which is far away from the substrate, through dry etching so as to form a second gate insulating layer on the side wall of the gate trench, and forming a third gate insulating layer on the surface of the first gate insulating layer, which is far away from the substrate;
and filling a polysilicon material in the gate trench to form a polysilicon gate.
Optionally, forming a trench gate structure in the gate trench includes:
Forming a mask layer on the surface of the semiconductor epitaxial layer far away from the substrate and the groove wall of the gate groove;
Etching the mask layer at the bottom of the gate trench to expose the bottom of the gate trench;
forming a first grid initial insulating layer on the surface of one side of the mask layer far away from the substrate, the surface of the mask layer in the grid groove far away from the side wall of the grid groove and the bottom of the grid groove;
coating photoresist so that the photoresist covers the surface of the first grid initial insulating layer, which is far away from the side of the substrate, and filling the grid groove;
patterning the photoresist to form a plurality of openings exposing the first gate initial insulating layer away from the surface of one side of the substrate;
Etching the first gate initial insulating layer and at least part of the mask layer based on the opening in the photoresist;
removing the photoresist, and removing the mask layer and the first grid initial insulating layer positioned on the surface of the mask layer through corrosive liquid based on an ultrasonic oscillation mode so as to form a first grid insulating layer at the bottom of the polysilicon grid;
oxidizing the side wall of the gate trench by thermal oxidation to form a second gate insulating layer on the side wall of the gate trench, wherein the material of the second gate insulating layer comprises silicon oxide;
and filling a polysilicon material in the gate trench to form a polysilicon gate.
Optionally, etching the semiconductor epitaxial layer, and forming a gate trench in the semiconductor epitaxial layer, simultaneously, further includes:
Forming source trenches on two opposite sides of the gate trench, wherein the source trenches are arranged at intervals with the gate trench;
Before forming the trench gate structure in the gate trench, the method further comprises:
implanting doping ions of a second doping type into the side wall and the bottom of the source electrode groove to form a second doping region of a second conductivity type;
Forming a trench gate structure in the gate trench, and simultaneously, further comprising:
the method comprises the steps of forming a groove source structure in a source groove, wherein the groove source structure comprises a polycrystalline silicon source electrode, a first source electrode insulating layer positioned at the bottom of the polycrystalline silicon source electrode and a second source electrode insulating layer positioned on the side wall of the polycrystalline silicon source electrode, the first source electrode insulating layer and the first gate electrode insulating layer are synchronously formed in the same process, the material of the second source electrode insulating layer and the second gate electrode insulating layer are synchronously formed in the same process, and the polycrystalline silicon source electrode and the polycrystalline silicon gate electrode are synchronously formed in the same process.
According to another aspect of the present invention, there is provided a power module, including a substrate and at least one trench power device according to any of the embodiments of the present invention, where the substrate is used to carry the trench power device.
According to another aspect of the present invention, there is provided a power conversion circuit for one or more of current conversion, voltage conversion, power factor correction;
the power conversion circuit comprises a circuit board and at least one groove-type power device according to any embodiment of the invention, wherein the groove-type power device is electrically connected with the circuit board.
According to another aspect of the present invention, there is provided a vehicle including a load and the power conversion circuit according to any one of the embodiments of the present invention, the power conversion circuit being configured to convert alternating current into direct current, alternating current into alternating current, direct current into direct current, or direct current into alternating current, and then input the alternating current into the load.
The embodiment of the invention provides a groove type power device, a preparation method, a power module, a conversion circuit and a vehicle, wherein the groove type power device comprises a substrate, a semiconductor epitaxial layer, a grid groove, a groove grid structure and a first grid insulating layer and a second grid insulating layer, wherein the semiconductor epitaxial layer is positioned on one side of the substrate, the grid groove is arranged in the semiconductor epitaxial layer from the surface of one side of the semiconductor epitaxial layer, which is far away from the substrate, the groove grid structure is positioned in the grid groove, the groove grid structure comprises a polysilicon grid, the first grid insulating layer is positioned at the bottom of the polysilicon grid, the second grid insulating layer is positioned on the side wall of the polysilicon grid, the dielectric constant of the material of the first grid insulating layer is larger than or equal to that of the second grid insulating layer, and the dielectric constant of the material of the first grid insulating layer is larger than that of silicon oxide. According to the technical scheme provided by the embodiment of the invention, the gate insulating layer at the bottom of the polysilicon gate is set as the dielectric layer of high-k material, so that the problem that the gate insulating layer at the bottom of the polysilicon gate is easy to break down in the trench type power device can be solved, the gate insulating layers at the bottom of the polysilicon gate and the gate insulating layer at the side wall of the polysilicon gate are formed step by step, the thicknesses of the gate bottom and the gate insulating layer at the side wall can be respectively accurately controlled, the shapes of the bottom gate insulating layer thickness and the thin side wall gate insulating layer can be easily obtained, and the control capability of the gate on the device is ensured.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural cross-sectional view of a trench power device according to an embodiment of the present invention;
Fig. 2 is a schematic structural cross-sectional view of another trench power device according to an embodiment of the present invention;
fig. 3 is a schematic structural cross-sectional view of another trench power device according to an embodiment of the present invention;
fig. 4 is a flowchart of a method for manufacturing a trench power device according to an embodiment of the present invention;
fig. 5 is a schematic structural cross-section corresponding to step S120 in the method for manufacturing a trench power device according to an embodiment of the present invention;
fig. 6 is a schematic structural cross-section corresponding to step S130 in the method for manufacturing a trench power device according to an embodiment of the present invention;
Fig. 7 is a schematic structural cross-section corresponding to step S1401 in a method for manufacturing a trench power device according to an embodiment of the present invention;
Fig. 8 to fig. 13 are schematic structural cross-sectional views corresponding to steps S411 to S416, steps S421 to S426, or steps S431 to S436 in step S140 in a method for manufacturing a trench type power device according to an embodiment of the present invention;
fig. 14 is a schematic structural cross-sectional view corresponding to step S417 or step S427 in step S140 in the method for manufacturing a trench type power device according to the embodiment of the present invention;
fig. 15 is a schematic structural cross-sectional view corresponding to step S418 in step S140 in a method for manufacturing a trench type power device according to an embodiment of the present invention;
Fig. 16 is a schematic structural cross-sectional diagram corresponding to step S419 in step S140 in a method for manufacturing a trench power device according to an embodiment of the present invention;
Fig. 17 to 19 are schematic structural cross-sectional views corresponding to steps S428 to S4210 in step S140 in a method for manufacturing a trench type power device according to an embodiment of the present invention;
Fig. 20 to 23 are schematic structural cross-sectional views corresponding to steps S437 to S4310 in step S140 in the method for manufacturing a trench type power device according to the embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The embodiment of the invention provides a groove type power device, which is characterized by comprising the following components:
a substrate;
the semiconductor epitaxial layer is positioned on one side of the substrate;
the grid electrode groove is positioned on the surface of one side of the semiconductor epitaxial layer away from the substrate;
The gate structure comprises a polysilicon gate, a first gate insulating layer positioned at the bottom of the polysilicon gate and a second gate insulating layer positioned on the side wall of the polysilicon gate;
The dielectric constant of the material of the first gate insulating layer is greater than or equal to that of the material of the second gate insulating layer, and the dielectric constant of the material of the first gate insulating layer is greater than that of silicon oxide.
Specifically, the material of the substrate and the material of the semiconductor epitaxial layer may be the same or different. In the embodiment of the present invention, the material of the substrate is the same as that of the semiconductor epitaxial layer, and may be SiC. That is, the trench type power device in the embodiment of the present invention may be a trench type SiC power device. SiC has excellent physical and electrical properties. Compared with silicon materials, the SiC material has the advantages of large forbidden bandwidth, high breakdown electric field, high heat conductivity, high electron saturation rate, strong radiation resistance and the like, so that a semiconductor device prepared from the SiC material can stably operate at a higher temperature and is also suitable for high-voltage and high-frequency scenes. In some embodiments of the invention, the substrate and the semiconductor epitaxial layer may be integrally provided. The integration of the substrate and the semiconductor epitaxial layer is understood to mean that the substrate and the semiconductor epitaxial layer are a monolithic SiC film layer structure formed in the same fabrication process. And after the front process is carried out on the whole SiC film layer structure, thinning the back surface of the SiC film layer structure, and carrying out heavy doping of the first conductive type doping ions on the back surface of the SiC film layer structure to form the substrate.
The semiconductor epitaxial layer includes a first conductivity type first doped region, a first conductivity type doped region, and a first conductivity type second doped region. The doping concentration of the first doping region of the first conductivity type is smaller than that of the second doping region of the first conductivity type. The first conductive type first doped region is used for forming a drift region of the groove type SiC power device, the first conductive type doped region is used for forming a well region of the groove type SiC power device, and the first conductive type second doped region is used for forming a contact source region of the groove type SiC power device. The trench gate structure extends vertically from a surface contacting the source region to the drift region. The trench gate structure includes a gate insulating layer covering a surface of the gate trench, and a polysilicon gate surrounded by the gate insulating layer.
The gate insulating layer comprises a first gate insulating layer positioned at the bottom of the polysilicon gate and a second gate insulating layer positioned on the side wall of the polysilicon gate. The dielectric constant of the material of the first gate insulating layer is greater than or equal to the dielectric constant of the material of the second gate insulating layer, and the dielectric constant of the material of the first gate insulating layer is greater than the dielectric constant of silicon oxide. According to the technical scheme provided by the embodiment of the invention, the first gate insulating layer at the bottom of the polysilicon gate is set as the dielectric layer of high-k material, so that the problem that the gate insulating layer at the bottom of the polysilicon gate is easy to break down in a trench type power device can be solved, the gate insulating layer at the bottom of the polysilicon gate (the first gate insulating layer) and the gate insulating layer at the side wall of the polysilicon gate (the second gate insulating layer) are formed step by step, the thicknesses of the gate insulating layers at the bottom and the side wall of the gate trench can be accurately controlled respectively, the shape with thick bottom and thin side wall can be easily obtained, and the control capability of the polysilicon gate on the device is ensured.
The above is a core inventive concept of the present invention, and a manner of disposing the gate insulating layer is specifically described below with reference to the accompanying drawings.
Based on the above embodiments, in one embodiment of the present invention, fig. 1 is a schematic structural cross-section of a trench type power device according to the embodiment of the present invention, referring to fig. 1, the dielectric constant of the material of the second gate insulating layer 322 is greater than that of silicon oxide, and the thickness of the first gate insulating layer 321 is greater than that of the second gate insulating layer 322 located on the sidewall of the polysilicon gate 31.
Specifically, the gate trench is formed by etching the semiconductor epitaxial layer 20, etching the surface of the semiconductor epitaxial layer 20 away from the substrate 10 into the first doped region 21 of the first conductivity type, and forming the trench gate structure 30 in the gate trench, so that the trench gate structure 30 extends vertically from the surface contacting the source region to the drift region. After forming a first gate insulating layer 321 at the bottom of the gate trench and forming a second gate insulating layer 322 at the sidewall of the gate trench, the gate trench is filled with a polysilicon material to form a polysilicon gate 31. The polysilicon gate 31, the first gate insulating layer 321 at the bottom of the polysilicon gate 31, and the second gate insulating layer 322 at the sidewall of the polysilicon gate 31 are used to form the trench gate structure 30.
The dielectric constant of the material of the first gate insulating layer 321 is greater than that of silicon oxide, and the dielectric constant of the material of the second gate insulating layer 322 is greater than that of silicon oxide, i.e., the material of the first gate insulating layer 321 and the material of the second gate insulating layer 322 are both high-k materials. k refers to the dielectric constant, which measures the charge storage capacity of a material. Low dielectric (low-k) materials and high dielectric (high-k) materials are classified according to the dielectric constant. Typically Low-K materials have a dielectric constant below 3.0, and High-K materials have a dielectric constant, relative to SiO 2, of 3.9 greater than SiO 2, typically referred to as High-K materials. Exemplary High-k materials include, but are not limited to, oxides such as ZrO 2、Al2O3、HfO2. In the embodiment of the invention, the high-k dielectric layer is used as the gate insulating layer (the first gate insulating layer 321) at the bottom of the groove, so that the gate insulating layer at the bottom of the groove is prevented from being broken down to a great extent, the reliability of the device is improved, and the high-k dielectric layer is used as the second gate insulating layer 322 on the side wall of the groove on the basis of the high-k gate oxide at the bottom, so that the electron mobility is properly improved, and the starting rate of the device is further improved. Alternatively, the high-k material of the first gate insulating layer 321 may be the same as or different from the high-k material of the second gate insulating layer 322.
In addition, the first gate insulating layer 321 and the second gate insulating layer 322 are formed in an asynchronous manner, so that the thicknesses of the gate insulating layers at the bottom and on the side walls of the gate groove can be accurately controlled, the appearance of thick bottom and thin side walls can be easily obtained, the problem that the electric field effect at the channel is weakened due to the fact that the thickness of the gate insulating layer on the side wall of the polysilicon gate 31 is too thick is prevented, and the control capability of the polysilicon gate on the device is guaranteed. Wherein the thickness of the first gate insulation layer 321 at the bottom of the gate trench is determined by a first high-k material deposition and the thickness of the second gate insulation layer 322 at the sidewall is determined by a second high-k material deposition.
On the basis of the above embodiment, in one embodiment of the present invention, fig. 2 is a schematic structural cross-section of another trench type power device provided in the embodiment of the present invention, referring to fig. 2, the trench type power device further includes a third gate insulating layer 323 located between the first gate insulating layer 321 and the polysilicon gate 31, wherein the third gate insulating layer 323 is made of the same material as the second gate insulating layer 322, and the third gate insulating layer 323 is integrally disposed with the second gate insulating layer 322.
Specifically, the third gate insulating layer 323 is disposed between the first gate insulating layer 321 and the polysilicon gate electrode 31, so that the thickness of the gate insulating layer at the bottom of the polysilicon gate electrode 31 can be increased, thereby further preventing the gate insulating layer at the bottom of the trench from being broken down, and improving the reliability of the device. The third gate insulating layer 323 and the second gate insulating layer 322 are integrally formed, which means that the third gate insulating layer 323 and the second gate insulating layer 322 are formed in the same manufacturing process, and the third gate insulating layer 323 and the second gate insulating layer 322 are integrally formed, so that the manufacturing process of the third gate insulating layer 323 and the second gate insulating layer 322 can be simplified.
Based on the above embodiments, in one embodiment of the present invention, fig. 3 is a schematic structural cross-section of another trench type power device according to the embodiment of the present invention, and referring to fig. 3, the material of the second gate insulating layer 322 includes silicon oxide.
Specifically, on the basis that the first gate insulating layer 321 is made of a high-k material, the side wall of the gate trench is directly subjected to thermal oxidation to form the second gate insulating layer 322, and an additional high-k material deposition process is not required to form the second gate insulating layer 322, so that the process steps can be simplified, the production cost can be saved, and the manufacturing time can be reduced. In addition, compared with the formation of the high-k second gate insulating layer 322 on the sidewall of the gate trench shown in fig. 1 and fig. 2, the embodiment of the invention uses an autoxidation method to grow the SiO 2 second gate insulating layer 322 on the sidewall of the gate trench, so that the interface defect between the SiO2 second gate insulating layer 322 and the SiC semiconductor epitaxial layer 20 is fewer, which is more beneficial to the channel generation.
On the basis of the above embodiments, referring to fig. 1 to 3, the trench power device further includes:
the source electrode grooves are positioned on two opposite sides of the grid electrode groove and are arranged at intervals with the grid electrode groove;
the trench source structure 40 is positioned in the source trench, the trench source structure 40 comprises a polysilicon source 41, a first source insulation layer 421 positioned at the bottom of the polysilicon source 41 and a second source insulation layer 422 positioned on the side wall of the polysilicon source 41, wherein the material of the first source insulation layer 421 is the same as that of the first gate insulation layer 321, and the material of the second source insulation layer 422 is the same as that of the second gate insulation layer 322;
The semiconductor epitaxial layer 20 further includes a second doped region 24 of a second conductivity type, wherein the second doped region 24 of the second conductivity type is located at the bottom and sidewalls of the trench source structure 40. The doping concentration of the second conductive-type second doping region 24 may be greater than the doping concentration of the second conductive-type first doping region 22.
Specifically, the semiconductor epitaxial layer 20 is etched, and a gate trench is formed in the semiconductor epitaxial layer 20, and a source trench is formed on opposite sides of the gate trench, and the source trench and the gate trench are spaced apart from each other. After the source trench is etched, dopant ions of the second doping type are implanted into the sidewalls and bottom of the source trench to form a second doping region 24 of the second conductivity type. After the second conductive-type second doping region 24 is formed, the first source insulating layer 421 and the first gate insulating layer 321 are simultaneously formed in the same process, the second source insulating layer 422 and the second gate insulating layer 322 are simultaneously formed in the same process, and the polysilicon source 41 and the polysilicon gate 31 are simultaneously formed in the same process.
A depletion region is formed between the second doped region 24 of the second conductivity type and the first doped region 21 of the first conductivity type (drift region), which can play a role of shielding an electric field on the side surface of the trench gate structure 30, thereby improving the breakdown problem of the second gate insulating layer 322 on the side wall in the trench power device and ensuring the reliability of the device operation. Alternatively, the source trench may be a ring-shaped trench disposed around the trench gate structure 30 in a top view of the trench-type power device, or the source trench may be a dot-shaped trench, with a plurality of source trenches disposed around the trench gate structure 30. Preferably, the source trench is a ring-shaped trench, and the gate insulating layer of the trench gate structure 30 is protected from all directions that may be from the side of the trench gate structure 30.
On the basis of any of the above embodiments, referring to fig. 1 to 3, N-type doping ions are doped in the first conductive type first doping region 21 and the first conductive type second doping region 23;
P +、N+ in the drawing indicates that the ion doping concentration in this region is high, and P -、N- indicates that the ion doping concentration in this region is low. Wherein, the N-type doping ion can be P (phosphorus) or N (nitrogen) ion, and the P-type doping ion can be Al (aluminum) ion or B (boron) ion. The polysilicon (Poly) material in the gate trench is used to form the polysilicon gate 31 and the polysilicon (Poly) material in the source trench is used to form the polysilicon source 41.
Or the first conductive type first doped region 21 and the first conductive type second doped region 23 are doped with P-type doping ions, and the second conductive type first doped region 22 and the second conductive type second doped region 24 are doped with N-type doping ions.
On the basis of the above embodiments, please continue to refer to fig. 1-3, the trench power device further includes an interlayer insulating layer ILD located on a side of the semiconductor epitaxial layer 20 away from the substrate 10 and covering the trench gate structure 30, a source electrode S located on a side of the interlayer insulating layer ILD away from the substrate 10 and on a surface of the semiconductor epitaxial layer 20 uncovered by the interlayer insulating layer ILD, and a drain electrode D located on a surface of the substrate 10 away from the semiconductor epitaxial layer 20. The interlayer insulating layer ILD is used to isolate the source electrode S from the trench gate structure 30, and the material of the interlayer insulating layer ILD may include silicon oxide. The materials of the source electrode S and the drain electrode D include metals. When a positive bias voltage is applied to the trench gate structure 30, an N-channel is formed between the N-type drift region and the N-type source contact region, and electron current is injected from the N-type source contact region, flows through the N-type drift region through the N-channel, and the source electrode S and the drain electrode D are turned on. The trench type power device may further include a passivation layer and a protection layer sequentially on the source electrode. The material of the passivation layer may include silicon nitride (SiN), and the material of the protective layer may include Polyimide (PI).
The embodiment of the invention also provides a method for preparing the trench type power device, which is used for preparing the trench type power device described in any embodiment, and fig. 4 is a flowchart of the method for preparing the trench type power device provided in the embodiment of the invention, and referring to fig. 4, the method for preparing the trench type power device comprises:
S110, providing a substrate.
S120, forming a semiconductor epitaxial layer on one side of the substrate.
Specifically, referring to fig. 5, the semiconductor epitaxial layer 20 sequentially includes a first conductive type first doping region 21, a second conductive type first doping region 22, and a first conductive type second doping region 23 along the direction in which the semiconductor outer layer 20 is epitaxially grown. The first conductive type first doped region 21 and the first conductive type second doped region 23 are doped with N-type dopant ions, and the second conductive type first doped region 22 and the second conductive type second doped region 24 are doped with P-type dopant ions. In some embodiments of the present invention, the first conductive type first doped region 21 and the first conductive type second doped region 23 are doped with P-type doping ions, and the second conductive type first doped region 22 and the second conductive type second doped region 24 are doped with N-type doping ions.
And S130, forming a gate groove on the surface of the side, away from the substrate, of the semiconductor epitaxial layer.
Specifically, referring to fig. 6, the semiconductor epitaxial layer 20 may be etched by a photolithography process to form a gate trench 01 in the semiconductor epitaxial layer 20, the gate trench 01 extending from a surface of the semiconductor epitaxial layer 20 on a side remote from the substrate 10 to the first conductive-type first doping region 21. The photolithography (photolithography) process is an important step in the semiconductor device manufacturing process, and is used for describing a geometric figure structure on a photoresist layer by means of exposure and development, transferring a figure on a photomask to a mask layer through an etching process to realize patterning of the photomask layer, and etching the silicon carbide epitaxial layer exposed by the mask layer through the etching process to obtain a groove with a preset shape.
And S140, forming a trench gate structure in the gate trench, wherein the trench gate structure comprises a polysilicon gate, a first gate insulating layer positioned at the bottom of the polysilicon gate and a second gate insulating layer positioned on the side wall of the polysilicon gate, wherein the dielectric constant of the material of the first gate insulating layer is greater than or equal to that of the material of the second gate insulating layer, and the dielectric constant of the material of the first gate insulating layer is greater than that of silicon oxide.
Specifically, referring to fig. 1 to 3, the trench gate structure 30 includes a polysilicon gate 31, a first gate insulating layer 321 located at the bottom of the polysilicon gate 31, and a second gate insulating layer 322 located at the sidewall of the polysilicon gate 31. The material of the first gate insulating layer 321 is a high-k material having a dielectric constant greater than that of silicon oxide. In fig. 1, the material of the second gate insulating layer 322 is a high-k material having a dielectric constant greater than that of silicon oxide. In fig. 2, the second gate insulating layer 322 is made of a high-k material having a dielectric constant greater than that of silicon oxide, and a third gate insulating layer 323 is further disposed between the first gate insulating layer 321 and the polysilicon gate electrode 31, and the third gate insulating layer 323 and the second gate insulating layer 322 are integrally disposed. In fig. 3, the material of the second gate insulating layer 322 is a silicon oxide material.
Referring to fig. 8 to 16 for the structure shown in fig. 1, step S140 forms a trench gate structure 30 in a gate trench 01, which specifically includes:
S411, a mask layer 50 is formed on the surface of the semiconductor epitaxial layer 20 away from the substrate 10 and the wall of the gate trench 01.
S412, etching the mask layer 50 at the bottom of the gate trench 01 to expose the bottom of the gate trench 01.
Specifically, referring to fig. 8, the mask layer 50 is a hard mask, and the material thereof may be, for example, silicon nitride. After forming the mask layer 50 on the surface of the semiconductor epitaxial layer 20 away from the substrate 10 and on the sidewalls and bottom of the gate trench 01, the mask layer 50 on the bottom of the gate trench 01 is etched by a photolithography process, thereby exposing the bottom of the gate trench 01.
S413, a first gate initial insulating layer 61 is formed on a surface of the mask layer 50 on a side away from the substrate 10, a surface of the mask layer 50 in the gate trench 01 away from the sidewall of the gate trench 01, and a bottom of the gate trench 01.
Specifically, referring to fig. 9, a first gate initial insulating layer 61 may be formed by depositing a high-k material through, for example, an ALD deposition process. Exemplary High-k materials include, but are not limited to, oxides such as ZrO 2、Al2O3、HfO2.
S414, forming photoresist PR on the surface of the first gate initial insulating layer 61 away from the substrate 10 and in the gate trench 01, and patterning the photoresist PR to form a plurality of openings 03 exposing the surface of the first gate initial insulating layer 61 away from the substrate 10.
Specifically, referring to fig. 10, a photoresist PR is coated such that the photoresist PR covers a surface of the first gate initial insulating layer 61 on a side far from the substrate 10 and fills the gate trench 01, and the photoresist PR is patterned by an exposure developing process to form a plurality of openings 03 exposing the surface of the first gate initial insulating layer 61 on the side far from the substrate 10.
S415, based on the opening 03 in the photoresist PR, the first gate initial insulating layer 61 and at least part of the mask layer 50 are etched.
Specifically, referring to fig. 11, based on the opening 03 in the photoresist PR, the first gate initial insulating layer 61 located at a side surface of the mask layer 50 remote from the substrate 10 is etched through, and the mask layer 50 is continuously etched at least partially in thickness. Preferably, a portion of the thickness of the mask layer 50 is etched to avoid damage to the surface of the semiconductor epitaxial layer 20 during the etching process when the mask layer 50 is etched through.
And S416, removing the photoresist PR, and removing the mask layer 50 and the first gate initial insulating layer 61 positioned on the surface of the mask layer 50 by using an etching solution based on an ultrasonic vibration mode to form a first gate insulating layer 321 at the bottom of the gate trench 01.
Specifically, referring to fig. 12 and 13, after the photoresist PR is removed, the mask layer 50 is etched by an etching solution and under ultrasonic vibration to remove the mask layer 50 and remove the first gate initial insulating layer 61 attached to the mask layer 50 when the mask layer 50 is removed. Since the first gate initial insulating layer 61 at the bottom of the gate trench 01 is not attached to the mask layer 50, the first gate initial insulating layer 61 at the bottom of the gate trench 01 remains and serves as the first gate insulating layer 321.
S417, forming a second gate initial insulating layer 62 on a surface of the semiconductor epitaxial layer 20 on a side away from the substrate 10, a sidewall of the gate trench 01, and a surface of the first gate insulating layer 321, wherein a dielectric constant of a material of the second gate initial insulating layer 62 is greater than a dielectric constant of silicon oxide.
Specifically, referring to fig. 14, a second gate initial insulating layer 62 may be formed by depositing a high-k material, for example, by an ALD deposition process. Exemplary High-k materials include, but are not limited to, oxides such as ZrO 2、Al2O3、HfO2. The high-k material of the second gate initial insulating layer 62 may be the same as or different from the high-k material of the first gate initial insulating layer 61, which is not limited in the embodiment of the present invention.
S418, removing the second gate initial insulating layer 62 on the surface of the semiconductor epitaxial layer 20 away from the substrate 10 by dry etching, and removing the second gate initial insulating layer 62 on the surface of the first gate insulating layer 321 away from the substrate 10 to form the second gate insulating layer 322 on the sidewall of the gate trench 01.
Specifically, referring to fig. 15, the second gate initial insulating layer 62 located at a side surface of the semiconductor epitaxial layer 20 away from the substrate 10 is removed and the second gate initial insulating layer 62 located at a side surface of the first gate insulating layer 321 away from the substrate 10 is removed by dry etching. The second gate initial insulating layer 62 located at the sidewall of the gate trench 01 remains and serves as the second gate insulating layer 322.
S419, filling the gate trench 01 with a polysilicon material to form the polysilicon gate 31. Reference is made in particular to fig. 16.
Compared with a conventional device, the preparation method provided by the embodiment of the invention can respectively accurately control the thickness of the dielectric layers at the bottom and the side wall of the gate trench 01, so that the morphology of the dielectric layers with thick bottom and thin side wall can be obtained easily. Wherein the thickness of the dielectric layer at the bottom of the gate trench 01 is determined by a first high-k deposition and the thickness of the gate oxide layer at the sidewall is determined by a second high-k deposition. On the basis that the bottom gate oxide layer is made of high-k material, the gate oxide layer made of high-k material is also used on the side wall of the groove, so that the electron mobility can be improved, and the opening rate of the device can be improved.
For the structure shown in fig. 2, step S140 forms a trench gate structure 30 in the gate trench 01, comprising:
s421, a mask layer 50 is formed on the surface of the semiconductor epitaxial layer 20 away from the substrate 10 and the wall of the gate trench 01. Specific reference may be made to step S411, and details are not repeated here.
S422, etching the mask layer 50 at the bottom of the gate trench 01 to expose the bottom of the gate trench 01. Reference is made specifically to step S412, and details thereof are not repeated here.
S423, a first gate initial insulating layer is formed on a surface of the mask layer 50 on a side away from the substrate 10, a surface of the mask layer 50 in the gate trench away from the sidewall of the gate trench 01, and a bottom of the gate trench 01. Reference is made specifically to step S413, and details thereof are not repeated here.
At S424, photoresist is formed on the surface of the first gate initial insulating layer away from the substrate 10 and in the gate trench 01, and the photoresist is patterned to form a plurality of openings 03 exposing the surface of the first gate initial insulating layer away from the substrate 10. Reference is made specifically to step S414, and details thereof are not repeated here.
S425, etching the first gate initial insulating layer and at least part of the mask layer 50 based on the opening 03 in the photoresist. Specific reference may be made to step S415, and details thereof are not repeated here.
And S426, removing the photoresist, and removing the mask layer 50 and the first gate initial insulating layer positioned on the surface of the mask layer 50 by using an etching solution based on an ultrasonic vibration mode to form a first gate insulating layer 321 at the bottom of the polysilicon gate 31. Reference is made specifically to step S416, and details thereof are not repeated here.
S427, forming a second gate initial insulating layer on the surface of the semiconductor epitaxial layer 20, which is far away from the substrate 10, the side wall of the gate groove 01 and the surface of the first gate insulating layer 321, wherein the dielectric constant of the material of the second gate initial insulating layer is larger than that of silicon oxide. Specific reference is made to step S417, and details are not repeated here.
S428, filling photoresist in the gate trench 01 to cover the second gate initial insulating layer in the gate trench 01.
Specifically, referring to fig. 17, the gate trench 01 is filled with the photoresist PR such that the photoresist PR covers the second gate initial insulating layer 62 located in the gate trench 01, i.e., covers the second gate initial insulating layer 62 located at the sidewall of the gate trench 01 and the second gate initial insulating layer 62 located at the bottom of the gate trench 01. The photoresist PR is used to protect the second gate initial insulating layer 62 located at the sidewall of the gate trench 01 and the second gate initial insulating layer 62 located at the bottom of the gate trench 01 when the second gate initial insulating layer 62, which may be located on the surface of the semiconductor epitaxial layer 20 on the side remote from the substrate 10, is etched by a dry method in step S429.
S429, the second gate initial insulating layer 62 on the surface of the semiconductor epitaxial layer 20 on the side away from the substrate 10 is removed by dry etching to form the second gate insulating layer 322 on the sidewall of the gate trench 01 and the third gate insulating layer 323 on the surface of the first gate insulating layer 321 on the side away from the substrate 10.
Specifically, referring to fig. 18, based on the protection of the second gate initial insulating layer 62 located in the gate trench 01 by the photoresist PR, the second gate initial insulating layer 62 located on the surface of the semiconductor epitaxial layer 20 on the side away from the substrate 10 may be removed by dry etching while the second gate initial insulating layer 62 located in the gate trench 01 remains, and the second gate initial insulating layer 62 located in the gate trench 01 is taken as the second gate insulating layer 322 and the second gate initial insulating layer 62 located at the bottom of the gate trench 01 is taken as the third gate insulating layer 323. The photoresist PR is removed.
S4210, filling the gate trench 01 with a polysilicon material to form a polysilicon gate 31. Reference is made in particular to fig. 19.
On the basis of the embodiment, in the embodiment of the invention, by additionally adding the photoetching step, the redundant high-k dielectric layer is deposited on the etched surface, and simultaneously, the photoresist PR is used for protecting the high-k material deposited at the bottom of the gate trench 01 for the second time, so that the influence on the quality of the bottom gate oxide film in the whole dry etching can be avoided.
In one embodiment of the present invention, for the structure shown in fig. 3, step S140 forms a trench gate structure 30 in the gate trench 01, specifically including:
in S431, a mask layer 50 is formed on the surface of the semiconductor epitaxial layer 20 away from the substrate 10 and the wall of the gate trench 01. Specific reference may be made to step S411, and details are not repeated here.
S432, etching the mask layer 50 at the bottom of the gate trench 01 to expose the bottom of the gate trench 01. Reference is made specifically to step S412, and details thereof are not repeated here.
S433, a first gate initial insulating layer 61 is formed on the surface of the mask layer 50 on the side away from the substrate 10, the surface of the mask layer 50 in the gate trench away from the sidewall of the gate trench 01, and the bottom of the gate trench 01. Reference is made specifically to step S413, and details thereof are not repeated here.
At S434, photoresist is formed on the surface of the first gate initial insulating layer on the side far from the substrate 10 and in the gate trench 01, and the photoresist is patterned to form a plurality of openings 03 exposing the surface of the first gate initial insulating layer 61 on the side far from the substrate 10. Reference is made specifically to step S414, and details thereof are not repeated here.
S435, based on the opening 03 in the photoresist, the first gate initial insulating layer 61 and at least part of the mask layer 50 are etched. Specific reference may be made to step S415, and details thereof are not repeated here.
S436, removing the photoresist PR, and removing the mask layer 50 and the first gate initial insulating layer 61 on the surface of the mask layer 50 by using an etching solution based on an ultrasonic oscillation manner, so as to form the first gate insulating layer 321 at the bottom of the polysilicon gate 31. Reference is made specifically to step S416, and details thereof are not repeated here.
And S437, oxidizing the side wall of the gate groove 01 and the surface of the semiconductor epitaxial layer 20, which is far away from the side of the substrate 10, by a thermal oxidation mode to form a second gate initial insulating layer, wherein the material of the second gate initial insulating layer comprises silicon oxide. Specifically, referring to fig. 20, the sidewall of the gate trench 01 and the surface of the semiconductor epitaxial layer 20 on the side remote from the substrate 10 are oxidized by thermal oxidation to form a second gate initial insulating layer 70 made of silicon oxide.
And S438, filling photoresist in the gate trench 01 to cover the second gate initial insulating layer in the gate trench 01. Referring specifically to fig. 21.
S439, the second gate initial insulating layer on the surface of the semiconductor epitaxial layer 20 on the side remote from the substrate 10 is removed by dry etching to form a second gate insulating layer 322 on the sidewall of the gate trench 01.
Specifically, referring to fig. 22, based on the protection of the second gate initial insulating layer 70 located in the gate trench 01 by the photoresist PR, the second gate initial insulating layer 70 located on the surface of the semiconductor epitaxial layer 20 on the side away from the substrate 10 may be removed by dry etching while the second gate initial insulating layer 70 located at the sidewall of the gate trench 01 is remained, and the second gate initial insulating layer 70 located at the sidewall of the gate trench 01 is taken as the second gate insulating layer 322. The photoresist PR is removed.
S4310, the gate trench 01 is filled with a polysilicon material, thereby forming a polysilicon gate 31. Referring specifically to fig. 23.
On the basis of the above embodiment, according to the preparation scheme provided by the embodiment of the invention, the SiO 2 film layer is grown on the side wall of the gate trench 01 as the second gate insulation layer 322 on the side wall of the gate trench in an autoxidation mode, a deposition process is not required to be additionally adopted, the preparation process of the device is simplified, the production cost is saved, the manufacturing time is reduced, and compared with the mode of depositing high-k material later, the interface defect between the autoxidation grown SiO 2 and SiC is fewer, so that the channel is more beneficial to the generation.
The trench type power device further comprises a source trench located at two opposite sides of the gate trench and spaced apart from the gate structure, a trench source structure 40 located in the source trench, the trench source structure 40 comprising a polysilicon source 41, a first source insulating layer 421 located at the bottom of the polysilicon source 41 and a second source insulating layer 422 located at the side wall of the polysilicon source 41, the first source insulating layer 421 being made of the same material as the first gate insulating layer 321, the second source insulating layer 422 being made of the same material as the second gate insulating layer 322, wherein the semiconductor outer layer further comprises a second doped region 24 of a second conductivity type, the second doped region 24 of a second conductivity type being located at the bottom and the side wall of the trench source structure 40.
Thus, referring to FIG. 6, etching the semiconductor epitaxial layer 20, forming a gate trench 01 in the semiconductor epitaxial layer 20, further includes forming source trenches 02 on opposite sides of the gate trench 01, the source trenches 02 being spaced apart from the gate trench 01. Referring to fig. 7, before forming the trench gate structure 30 in the gate trench 01, a step S1401 of implanting dopant ions of the second doping type into the sidewall and bottom of the source trench 02 to form a second doping region 24 of the second conductivity type is further included. Referring to fig. 8-23, forming the trench gate structure 30 in the gate trench 01 includes forming a trench source structure 40 in the source trench 02. The method of fabricating the trench source structure 40 in the source trench 02 is the same as the manner of forming the trench gate structure 30 in the gate trench 01. The first source insulating layer 421 and the first gate insulating layer 321 are formed simultaneously in the same process, the second source insulating layer 422 and the second gate insulating layer 322 are formed simultaneously in the same process, and the polysilicon source 41 and the polysilicon gate 31 are formed simultaneously in the same process. For the semiconductor device shown in fig. 2, a third source insulating layer 423 is further included between the polysilicon source 41 and the first source insulating layer 421.
On the basis of the above embodiment, optionally, after step S140, the method further includes:
S140, forming an interlayer insulating layer ILD on one side of the semiconductor epitaxial layer 20 away from the substrate 10;
and S150, forming a source electrode S on one side of the interlayer insulating layer ILD far away from the substrate 10 and the surface of the semiconductor epitaxial layer 20 uncovered by the interlayer insulating layer, and forming a drain electrode D on the surface of the substrate 10 far away from the semiconductor epitaxial layer 20.
Specifically, a deposited isolation dielectric material, such as a SiO 2 material, is formed on the side of the semiconductor epitaxial layer 20 remote from the substrate 10, thereby forming an interlayer insulating layer ILD covering the trench gate structure 30, and then the source hole is opened. Forming a Ti/TiN/Al metal layer in the source hole as a source electrode S, depositing SiO2 and/or SiN by PECVD to form a passivation layer, coating polyimide on the passivation layer to form a protective layer, performing back thinning, metal deposition and the like to form a drain electrode D on the surface of the substrate 10 far from the semiconductor epitaxial layer 20.
The embodiment of the invention also provides a power module, which comprises a substrate and at least one groove-type power device according to any embodiment of the invention, wherein the substrate is used for bearing the groove-type power device. Has the same technical effects and is not described in detail herein.
According to another aspect of the present invention, there is provided a power conversion circuit for one or more of current conversion, voltage conversion, power factor correction;
The power conversion circuit comprises a circuit board and at least one groove-type power device according to any embodiment of the invention, wherein the groove-type power device is electrically connected with the circuit board. Has the same technical effects and is not described in detail herein.
According to another aspect of the present invention, there is provided a vehicle including a load and the power conversion circuit according to any embodiment of the present invention, the power conversion circuit being configured to convert alternating current into direct current, alternating current into alternating current, direct current into direct current, or direct current into alternating current, and then input the alternating current into the load. Has the same technical effects and is not described in detail herein.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
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