CN119133243A - Semiconductor power device, preparation method, power module, conversion circuit and vehicle - Google Patents
Semiconductor power device, preparation method, power module, conversion circuit and vehicle Download PDFInfo
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Abstract
The invention discloses a semiconductor power device, a preparation method, a power module, a conversion circuit and a vehicle, wherein the semiconductor power device comprises a substrate, a semiconductor epitaxial layer, a grid groove and a grid structure, wherein the semiconductor epitaxial layer is positioned on one side of the substrate, the semiconductor epitaxial layer comprises a drift region, a body region and a contact region which are sequentially far away from the substrate, the grid groove is positioned on the surface of one side of a semiconductor far away from the substrate, the grid structure is positioned in the grid groove, a superjunction structure is positioned in the drift region and is positioned on one side of the grid structure close to the substrate, the superjunction structure comprises a first conductive type superjunction and second conductive type superjunctions which are positioned on two opposite sides of the first conductive type superjunction in a direction parallel to the substrate, the second conductive type superjunction is opposite to the conductivity type of the drift region, and the second conductive type superjunction covers corners between the bottom surface and the side wall of the grid structure. The technical scheme provided by the invention improves the breakdown problem of the gate insulation layer and reduces the on-resistance of the device.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a semiconductor power device, a manufacturing method, a power module, a conversion circuit and a vehicle.
Background
Silicon carbide (SiC) has excellent physical and electrical characteristics as a representative of third generation semiconductor materials. Compared with silicon materials, the SiC material has the advantages of large forbidden bandwidth, high breakdown electric field, high heat conductivity, high electron saturation rate, strong radiation resistance and the like, so that the semiconductor power device prepared from the SiC material can stably operate at a higher temperature and is also suitable for high-voltage and high-frequency scenes.
The trench type SiC power device prepared by the SiC material at present has the advantages of high current density, small cell size and the like, but in the trench type SiC power device, the high electric field at the bottom and the trench angle of a gate trench can increase the electric field on a gate insulating layer, so that the gate insulating layer is easy to break down. Fig. 1 is a schematic structural view of a semiconductor power device provided in the related art, fig. 2 is a schematic structural view of an electric field shielding structure formed in a manufacturing process of the structure shown in fig. 1, referring to fig. 1 and 2, in the related art, after an epitaxial layer 2 is formed on a substrate 1, source trenches 5 with deeper depths are formed on opposite sides of a gate trench 4 by etching, ions with opposite conductivity types to the epitaxial layer 2 are implanted into the bottom and the side walls of the source trenches 5, so that an electric field shielding structure 3 with a depth greater than the depth of the gate trench is formed on both sides of the gate trench 4, if the substrate 1 is a heavily doped N-type substrate, the epitaxial layer 2 is an N-type epitaxial layer, the electric field shielding structure 3 is a P-type heavily doped region formed in the N-type epitaxial layer, and p+ and n+ shown in the drawing indicate that the ion doping concentration of the region is high, and P-N-indicates that the ion doping concentration of the region is low. The P-type heavily doped region is easy to form a wider depletion layer with the N-type epitaxial layer due to high ion implantation concentration, and a current conduction path is reduced, so that the on-resistance of the semiconductor power device is increased. Therefore, how to improve the problem of breakdown of the gate insulation layer in the semiconductor power device and reduce the on-resistance of the device is a technical problem to be solved by the person in the art.
Disclosure of Invention
The embodiment of the invention provides a semiconductor power device, a preparation method, a power module, a conversion circuit and a vehicle, which are used for improving the problem of breakdown of a gate insulation layer in the semiconductor power device and reducing on-resistance.
According to an aspect of the present invention, there is provided a semiconductor power device including:
A substrate;
the semiconductor epitaxial layer is positioned on one side of the substrate and comprises a drift region, a body region and a contact region which are sequentially far away from the substrate;
The semiconductor epitaxial layer comprises a substrate, a grid electrode groove and a grid electrode structure, wherein the grid electrode groove is positioned on the surface of one side of the semiconductor epitaxial layer, which is far away from the substrate;
the super junction structure is positioned in the drift region and at one side of the grid structure close to the substrate, and comprises a first conductive type super junction and second conductive type super junctions which are positioned at two opposite sides of the first conductive type super junction in a direction parallel to the substrate, wherein the second conductive type super junction is opposite to the conductive type of the drift region, and the second conductive type super junction covers a corner between the surface of the grid structure close to one side of the substrate and the side wall.
Optionally, the contact region includes a first conductivity type contact region and a second conductivity type contact region; the first conductive type contact region is positioned between the gate trench and the second conductive type contact region and is positioned at one side of the body region away from the substrate;
wherein the distance from the second conductive type contact region to the substrate is greater than the distance from the gate trench to the substrate.
Optionally, the gate trench includes at least two sub-trenches, the at least two sub-trenches are sequentially arranged in a direction that the semiconductor epitaxial layer points to the substrate, and a width of a sub-trench close to the substrate in the two adjacent sub-trenches is smaller than a width of a sub-trench far away from the substrate;
the bottom of the sub-groove closest to the substrate is provided with the first conductive type super junction, and the second conductive type super junction extends to a step surface between two adjacent sub-grooves closest to the substrate along the side wall of the sub-groove closest to the substrate.
Optionally, the gate trench includes two sub-trenches, which are a first-stage sub-trench and a second-stage sub-trench located at the bottom of the first-stage sub-trench;
The second-conductivity-type superjunction is positioned at two opposite sides of the first-conductivity-type superjunction and extends to the first-stage sub-trench along the side wall of the second-stage sub-trench.
Optionally, the second conductive type contact region is positioned at one side of the body region away from the substrate, and the thickness of the second conductive type contact region is smaller than the total thickness of the first conductive type contact region and the body region;
Or the second conductive type contact region is positioned on one side of the first conductive type contact region away from the gate trench and one side of the body region away from the gate trench, and the thickness of the second conductive type contact region is greater than or equal to the total thickness of the first conductive type contact region and the body region.
Optionally, the semiconductor epitaxial layer further comprises a current diffusion layer;
The current diffusion layer is located between the body region and the drift region in the case that the second conductivity type contact region is located at a side of the body region away from the substrate, and the thickness of the second conductivity type contact region is smaller than the total thickness of the first conductivity type contact region and the body region;
The current diffusion layer is located between the body region and the drift region, and between the second conductivity type contact region and the drift region, in a case where the second conductivity type contact region is located on a side of the first conductivity type contact region and the body region away from the gate trench, and a thickness of the second conductivity type contact region is greater than or equal to a total thickness of the first conductivity type contact region and the body region.
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor power device according to any one of the embodiments of the present invention, including,
Providing a substrate;
Forming a semiconductor epitaxial layer on one side of a substrate, wherein the semiconductor epitaxial layer comprises a drift region, a body region and a contact region which are sequentially far away from the substrate, and a super junction structure positioned in the drift region, and the super junction structure comprises a first conductive type super junction and second conductive type super junctions positioned on two opposite sides of the first conductive type super junction in a direction parallel to the substrate, and the second conductive type super junction is opposite to the drift region in conductivity type;
forming a grid groove on the surface of one side of the semiconductor epitaxial layer far away from the substrate;
forming a grid structure in the grid groove, wherein the super junction structure is positioned on one side of the grid structure close to the substrate, and the second conduction type super junction covers the corner between the surface of the grid structure close to one side of the substrate and the side wall.
Optionally, forming a semiconductor epitaxial layer on one side of the substrate includes:
Forming a first semiconductor epitaxial sub-layer of a first conductivity type on one side of the substrate, and performing ion implantation in the first semiconductor epitaxial sub-layer to form the superjunction structure;
forming a second semiconductor epitaxial sub-layer of the first conductivity type on one side of the first semiconductor epitaxial sub-layer far away from the substrate, and performing ion implantation in the second semiconductor epitaxial sub-layer to form a body region and a first conductivity type contact region;
and performing ion implantation again at two ends of the first conductive type contact region to form a second conductive type contact region, wherein the contact region comprises the first conductive type contact region and the second conductive type contact region, and the distance from the bottom surface of the second conductive type contact region to the substrate is larger than the distance from the bottom surface of the gate trench to the substrate.
Optionally, before the ion implantation is performed in the second semiconductor epitaxial sublayer to form the body region and the first conductivity type contact region, the method further comprises:
A current spreading layer is formed between the body region and the drift region.
Optionally, the gate trench includes a first-stage sub-trench and a second-stage sub-trench located at the bottom of the first-stage sub-trench;
Forming a gate groove on the surface of the side, away from the substrate, of the semiconductor epitaxial layer, wherein the gate groove comprises the following steps:
sequentially etching the contact region, the body region and the drift region from the surface of the semiconductor epitaxial layer far away from one side of the substrate to the top of the super junction structure to form a first-stage sub-groove;
Etching the super junction of the first conductivity type at the bottom of the first-stage sub-groove to form a second-stage sub-groove, wherein the width of the second-stage sub-groove is smaller than that of the first-stage sub-groove.
Optionally, forming a gate structure in the gate trench includes
Forming a gate insulating layer on the side wall and the bottom of the gate trench;
and forming a polysilicon gate in the cavity surrounded by the gate insulating layer, wherein the gate structure comprises the gate insulating layer and the polysilicon gate.
According to another aspect of the present invention, there is provided a power module comprising a substrate and at least one semiconductor power device according to any of the embodiments of the present invention, the substrate being configured to carry the semiconductor power device.
According to another aspect of the present invention, there is provided a power conversion circuit for one or more of current conversion, voltage conversion, power factor correction;
The power conversion circuit comprises a circuit board and at least one semiconductor power device according to any embodiment of the invention, wherein the semiconductor power device is electrically connected with the circuit board.
According to another aspect of the present invention, there is provided a vehicle including a load and the power conversion circuit according to any one of the embodiments of the present invention, the power conversion circuit being configured to convert alternating current into direct current, alternating current into alternating current, direct current into direct current, or direct current into alternating current, and then input the alternating current into the load.
According to the technical scheme provided by the embodiment of the invention, the second conductive type super-junction covers the corner between the bottom surface and the side wall of the gate structure, so that the effect of shielding the electric field at the bottom of the gate structure is achieved, the reliability of the device is improved, and the conductive channel can be increased by arranging the first conductive type super-junction between the second conductive type super-junctions, so that the on-resistance of the device is reduced. Instead of providing source trenches on opposite sides of the gate trench in the related art to form an electric field shielding structure with a deeper depth, the problem of increasing on-resistance of the device due to a wider depletion layer formed between the electric field shielding structure and the semiconductor epitaxial layer can be avoided.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural view of a semiconductor power device provided in the related art;
FIG. 2 is a schematic diagram of the structure of FIG. 1 during fabrication to form an electric field shielding structure;
fig. 3 is a schematic structural diagram of a semiconductor power device according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another semiconductor power device according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another semiconductor power device according to an embodiment of the present invention;
Fig. 6 is a schematic structural diagram of another semiconductor power device according to an embodiment of the present invention;
fig. 7 is a flowchart of a method for manufacturing a semiconductor power device according to an embodiment of the present invention;
fig. 8 to fig. 9 are schematic structural diagrams corresponding to step S1210 in a method for manufacturing a semiconductor power device according to an embodiment of the present invention;
Fig. 10 to 11 are schematic structural diagrams corresponding to step S1220 in the method for manufacturing a semiconductor power device according to the embodiment of the present invention;
Fig. 12 is a schematic diagram of another structure corresponding to step S1220 in the method for manufacturing a semiconductor power device according to the embodiment of the present invention;
fig. 13 is a schematic structural diagram corresponding to step S1230 in the method for manufacturing a semiconductor power device according to the embodiment of the present invention;
fig. 14 is a schematic structural diagram corresponding to step S1310 in a method for manufacturing a semiconductor power device according to an embodiment of the present invention;
fig. 15 is a schematic structural diagram corresponding to step S1320 in the method for manufacturing a semiconductor power device according to the embodiment of the present invention;
fig. 16 is a schematic structural diagram corresponding to step S1420 in a method for manufacturing a semiconductor power device according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
An embodiment of the present invention provides a semiconductor power device, and fig. 3 is a schematic structural diagram of the semiconductor power device provided in the embodiment of the present invention, and referring to fig. 3, the semiconductor power device includes:
A substrate 10;
the semiconductor epitaxial layer 20 is positioned on one side of the substrate 10, and the semiconductor epitaxial layer 20 comprises a drift region 21, a body region 22 and a contact region which are sequentially far away from the substrate 10;
a gate trench and a gate structure 30, the gate trench being located on a surface of the semiconductor on a side remote from the substrate 10;
The super junction structure 40 is located in the drift region 21 and located at one side of the gate structure 30 close to the substrate 10, wherein the super junction structure 40 comprises a first conductive type super junction 41 and second conductive type super junctions 42 located at two opposite sides of the first conductive type super junction 41 in a direction parallel to the substrate 10, the second conductive type super junctions 42 are opposite to the conductive type of the drift region 21, and the second conductive type super junctions 42 cover corners between the surface of the gate structure 30 close to one side of the substrate 10 and the side walls.
Specifically, the material of the substrate 10 may be the same as or different from the material of the semiconductor epitaxial layer 20. In the embodiment of the present invention, the material of the substrate 10 and the material of the semiconductor epitaxial layer 20 may be SiC. That is, the semiconductor power device in the embodiment of the invention may be a trench type SiC power device. SiC has excellent physical and electrical properties. Compared with silicon materials, the SiC material has the advantages of large forbidden bandwidth, high breakdown electric field, high heat conductivity, high electron saturation rate, strong radiation resistance and the like, so that a semiconductor device prepared from the SiC material can stably operate at a higher temperature and is also suitable for high-voltage and high-frequency scenes.
The surface of the semiconductor epitaxial layer 20 on the side remote from the substrate 10 comprises at least one gate trench. The gate trench may be formed by etching the contact region, the body region 22, and the drift region 21 up to a partial thickness sequentially from the surface of the semiconductor epitaxial layer 20 on the side remote from the substrate 10. The gate structure 30 is disposed in the gate trench, and the gate structure 30 includes a polysilicon gate 31 and a gate insulating layer 32 disposed between the polysilicon gate 31 and the gate trench. The material of the gate insulating layer 32 may include at least one of aluminum oxide and silicon oxide.
The semiconductor epitaxial layer 20 further includes a superjunction structure 40, and the superjunction structure 40 is located in the drift region 21 at the bottom of the gate structure 30. The super junction structure 40 includes a first conductive type super junction 41 and second conductive type super junctions 42 located at opposite sides of the first conductive type super junction 41. The first conductive type super junction 41 is the same conductive type as the drift region 21, and the first conductive type super junction 41 may cover the bottom surface of the gate structure 30. The second conductivity type superjunction 42 is opposite to the conductivity type of the drift region 21, and the second conductivity type superjunction 42 covers corners between the bottom surface and the sidewalls of the gate structure 30. The second conductive type super junction 42 is disposed at the corner between the bottom surface and the sidewall of the gate structure 30, which can play a role of shielding the electric field at the bottom of the gate structure 30, prevent the gate insulation layer 32 at the trench corner of the gate trench from being broken down, thereby improving the reliability of the device, and the first conductive type super junction 41 is disposed between the second conductive type super junction, which can increase the conductive path at the bottom of the gate structure 30, thereby reducing the on-resistance of the device.
According to the semiconductor power device provided by the embodiment of the invention, the super junction structure 40 is arranged at the bottom of the gate structure 30, the super junction structure 40 comprises the first conductive type super junction 41 and the second conductive type super junctions 42 positioned on two opposite sides of the first conductive type super junction 41, the first conductive type super junction 41 is the same as the conductive type of the drift region 21, the second conductive type super junction 42 is opposite to the conductive type of the drift region 21, the second conductive type super junction 42 covers the corners between the bottom surface and the side wall of the gate structure 30, the effect of shielding the electric field at the bottom of the gate structure 30 can be achieved, the reliability of the device is improved, and the conductive channel can be increased by arranging the first conductive type super junctions 41 between the second conductive type super junctions, so that the on-resistance of the device is reduced. Instead of providing source trenches on opposite sides of the gate trench in the related art to form an electric field shielding structure having a deeper depth, the problem of increasing on-resistance of the device due to a wider depletion layer formed between the electric field shielding structure and the semiconductor epitaxial layer 20 (drift region 21) can be avoided.
The above is a core inventive concept of the present invention, and a semiconductor power device is specifically described below with reference to the accompanying drawings.
Alternatively, the drift region 21 has the same conductivity type as the first conductivity type superjunction 41 and the body region 22 has the same conductivity type as the second conductivity type superjunction 42 and the second conductivity type. If the first conductivity type is N type, the second conductivity type is P type, and if the first conductivity type is P type, the second conductivity type is N type.
Wherein, the N-type doping ion can be P (phosphorus) or N (nitrogen) ion, and the P-type doping ion can be Al (aluminum) ion or B (boron) ion. The doping concentration of ions in the drift region 21 is less than the doping concentration of ions in the first conductivity type superjunction 41 and the doping concentration of ions in the body region 22 is less than the doping concentration of ions in the second conductivity type superjunction 42.
On the basis of the above embodiments, referring to fig. 3, the contact regions may alternatively include a first conductivity type contact region 23 and a second conductivity type contact region 24, the second conductivity type contact region 24 being located at opposite sides of the gate trench, the first conductivity type contact region 23 being located between the gate trench and the second conductivity type contact region 24 and at a side of the body region 22 remote from the substrate 10.
Wherein the first conductivity type contact region 23 and the second conductivity type contact region 24 are both heavily doped regions. The ion doping concentration in the first conductivity type contact region 23 is greater than the ion doping concentration in the first conductivity type superjunction 41, and the ion doping concentration in the second conductivity type contact region 24 is greater than the ion doping concentration in the second conductivity type superjunction 42.
In the embodiment of the present invention, the distance from the bottom surface of the second conductivity type contact region 24 to the substrate 10 is greater than the distance from the bottom surface of the gate structure 30 to the substrate 10. Compared with the mode that the distance from the bottom surface of the electric field shielding structure (the second conductive type heavily doped region) to the substrate 10 is smaller than the distance from the bottom surface of the gate trench to the substrate 10 in the related art, the technical scheme provided by the embodiment of the invention can enable the second conductive type heavily doped regions (the second conductive type contact regions 24) on two sides of the gate trench to be injected shallower, and a wider depletion layer cannot be formed with the drift region 21 of the first conductive type.
On the basis of the above embodiments, optionally, the gate trench includes at least two sub-trenches, the at least two sub-trenches are sequentially arranged in the direction that the semiconductor epitaxial layer 20 points to the substrate 10, and the widths of the sub-trenches close to the substrate 10 in the adjacent two sub-trenches are smaller than the widths of the sub-trenches far away from the substrate 10, namely, the widths of the sub-trenches gradually decrease, and the adjacent two sub-trenches are mutually communicated, wherein at least the bottom of the sub-trench closest to the substrate 10 is provided with a first conductivity type superjunction 41, and the second conductivity type superjunction 42 extends along the sidewall of the sub-trench closest to the substrate 10 at least to the step surface between the adjacent two sub-trenches closest to the substrate 10. The gate structure 30 is a step structure including at least two steps.
In fig. 3, the gate trench includes two sub-trenches, namely a first-level sub-trench and a second-level sub-trench at the bottom of the first-level sub-trench, a first-conductivity-type superjunction 41 at the bottom of the second-level sub-trench, and second-conductivity-type superjunctions 42 at opposite sides of the first-conductivity-type superjunction 41 and extending along sidewalls of the second-level sub-trench toward the first-level sub-trench.
With continued reference to fig. 3, in addition to the above embodiments, the second conductivity-type contact region 24 may be optionally located on a side of the body region 22 away from the substrate 10, and the thickness of the second conductivity-type contact region 24 may be smaller than the total thickness of the first conductivity-type contact region 23 and the body region 22. The depth of implantation of the second conductive type heavily doped region at two sides of the gate trench can be reduced, and the second conductive type heavily doped region is separated from the drift region 21 by the lightly doped body region 22, so that on-state current of the semiconductor device provided by the embodiment of the invention can be further increased, and on-state resistance is reduced.
Fig. 4 is a schematic structural diagram of another semiconductor power device according to the embodiment of the present invention, referring to fig. 4, in another embodiment of the present invention, the second conductive type contact region 24 is located on a side of the first conductive type contact region 23 away from the gate trench and a side of the body region 22 away from the gate trench, and the thickness of the second conductive type contact region 24 may be greater than or equal to the total thickness of the first conductive type contact region 23 and the body region 22. The thickness of the second conductive-type contact region 24 may be determined according to circumstances. It should be noted that, in order to ensure that the device has a smaller on-resistance, the distance from the second conductivity type contact region 24 to the substrate 10 is greater than the distance from the gate structure 30 to the substrate 10.
On the basis of the above embodiments, fig. 5 is a schematic structural diagram of another semiconductor power device according to an embodiment of the present invention, and fig. 6 is a schematic structural diagram of another semiconductor power device according to an embodiment of the present invention, and referring to fig. 5 and fig. 6, the semiconductor epitaxial layer 20 may further include a current diffusion layer 25.
Wherein the current spreading layer 25 may be formed by implanting dopant ions of the first conductivity type. The ion doping concentration in the current diffusion layer 25 is greater than the ion doping concentration in the drift region 21.
Referring to fig. 5, in the case where the second conductive-type contact region 24 is located at a side of the body region 22 away from the substrate 10, the thickness of the second conductive-type contact region 24 is smaller than the total thickness of the first conductive-type contact region 23 and the body region 22, the current diffusion layer 25 is located between the body region 22 and the drift region 21;
Referring to fig. 6, in the case where the second conductive type contact region 24 is located at a side of the first conductive type contact region 23 and the body region 22 away from the gate trench, the thickness of the second conductive type contact region 24 is greater than or equal to the total thickness of the first conductive type contact region 23 and the body region 22, the current diffusion layer 25 is located between the body region 22 and the drift region 21, and between the second conductive type contact region 24 and the drift region 21.
According to the technical scheme provided by the embodiment of the invention, the on-resistance of the device can be further reduced by additionally arranging the current diffusion layer 25 with the first conductivity type with higher concentration.
Based on the above embodiments, referring to fig. 3 to 6, optionally, the semiconductor power device further includes:
a first electrode 50 located on a side of the substrate 10 remote from the semiconductor epitaxial layer 20;
the second electrode 60 is located on a surface of the semiconductor epitaxial layer 20 on a side away from the substrate 10 and is in contact with the first conductivity type contact region 23 and the second conductivity type contact region 24.
The materials of the first electrode 50 and the second electrode 60 may each include a metal material. The first electrode 50 may be the drain electrode D and the second electrode 60 may be the source electrode S, or the first electrode 50 may be the source electrode S and the second electrode 60 may be the drain electrode D. In the embodiment of the present invention, the first electrode 50 is a drain electrode D, and the second electrode 60 is a source electrode S, for conducting the device.
Further, an interlayer insulating layer ILD is formed on the upper surface of the gate structure 30, and the second electrode 60 is located on a side of the interlayer insulating layer ILD away from the gate structure 30 and on a contact surface not covered by the interlayer insulating layer ILD. The interlayer insulating layer ILD is used to isolate the second electrode 60 from the gate structure 30.
Further, the semiconductor power device further includes a passivation layer 70 and a protective layer 80 on the second electrode 60. The material of the passivation layer 70 may include silicon nitride (SiN), and the material of the protective layer 80 may include polyimide.
The embodiment of the invention also provides a preparation method of the semiconductor power device, which is used for preparing the semiconductor power device according to any embodiment of the invention. Fig. 7 is a flowchart of a method for manufacturing a semiconductor power device according to an embodiment of the present invention, and referring to fig. 7, the method for manufacturing a semiconductor power device includes:
S110, providing a substrate.
And S120, forming a semiconductor epitaxial layer on one side of the substrate, wherein the semiconductor epitaxial layer comprises a drift region, a body region and a contact region which are sequentially far away from the substrate, and a super junction structure positioned in the drift region, and the super junction structure comprises a first conductive type super junction and second conductive type super junctions which are positioned on two opposite sides of the first conductive type super junction in a direction parallel to the substrate, and the second conductive type super junction is opposite to the drift region in conductivity type.
Specifically, the material of the substrate 10 may be the same as or different from the material of the semiconductor epitaxial layer 20. In the embodiment of the present invention, the material of the substrate 10 and the material of the semiconductor epitaxial layer 20 may be SiC. The drift region 21, the body region 22 and the contact region, which are sequentially remote from the substrate 10, and the superjunction structure 40 located in the drift region 21 may be formed in the semiconductor epitaxial layer 20 by a plurality of ion implantations.
The drift region 21 has the same conductivity type as the first conductivity type superjunction 41 and the body region 22 has the same conductivity type as the second conductivity type superjunction 42 and the second conductivity type. If the first conductivity type is N type, the second conductivity type is P type, and if the first conductivity type is P type, the second conductivity type is N type. Wherein, the N-type doping ion can be P (phosphorus) or N (nitrogen) ion, and the P-type doping ion can be Al (aluminum) ion or B (boron) ion. The doping concentration of ions in the drift region 21 is less than the doping concentration of ions in the first conductivity type superjunction 41 and the doping concentration of ions in the body region 22 is less than the doping concentration of ions in the second conductivity type superjunction 42.
The contact regions include a first conductive type contact region 23 and a second conductive type contact region 24, the second conductive type contact region 24 being formed at opposite sides of the gate trench, the first conductive type contact region 23 being formed between the gate trench and the second conductive type contact region 24. Wherein the first conductivity type contact region 23 and the second conductivity type contact region 24 are both heavily doped regions. The ion doping concentration in the first conductivity type contact region 23 is greater than the ion doping concentration in the first conductivity type superjunction 41, and the ion doping concentration in the second conductivity type contact region 24 is greater than the ion doping concentration in the second conductivity type superjunction 42.
And S130, forming a gate groove on the surface of the side, away from the substrate, of the semiconductor epitaxial layer.
Specifically, at least one gate trench is formed in a surface of the semiconductor epitaxial layer 20 on a side remote from the substrate 10. The gate trench may be formed by etching the contact region, the body region 22, and the drift region 21 to a partial thickness sequentially from the surface of the semiconductor epitaxial layer 20 on the side remote from the substrate 10 by photolithography.
And S140, forming a gate structure in the gate trench, wherein the super junction structure is positioned on one side of the gate structure close to the substrate, and the second conductivity type super junction covers the corner between the surface of the gate structure close to one side of the substrate and the side wall.
According to the preparation method of the semiconductor power device, the super junction structure 40 is formed at the bottom of the gate structure 30, the second conductivity type super junction 42 covers the corner between the bottom surface and the side wall of the gate structure 30, so that the effect of shielding an electric field at the bottom of the gate structure 30 can be achieved, the reliability of the device is improved, and the conductive channel can be increased by forming the first conductivity type super junction 41 between the second conductivity type super junctions, so that the on-resistance of the device is reduced.
On the basis of the above embodiments, optionally, step S120 forms a semiconductor epitaxial layer on one side of the substrate, including:
S1210, forming a first semiconductor epitaxial sub-layer of a first conductivity type on one side of the substrate, and performing ion implantation in the first semiconductor epitaxial sub-layer to form a super junction structure.
In particular, referring to fig. 8, the substrate 10 and the first semiconductor epitaxial sublayer 201 may be formed in different processes. The substrate 10 and the first semiconductor epitaxial sublayer 201 may also be formed in the same preparation process, i.e., the substrate 10 and the first semiconductor epitaxial sublayer 201 may be a monolithic SiC film layer structure formed in the same preparation process, and after the front process is performed on the monolithic SiC film layer structure, the back surface of the SiC film layer structure is thinned, and the back surface of the SiC film layer structure is heavily doped with ions, so as to form the substrate 10.
Referring to fig. 9, ion implantation is performed on a surface of the first semiconductor epitaxial sub-layer 201 on a side remote from the substrate 10, to form the superjunction structure 40. In the process of forming the superjunction structure 40, the position and the pattern of the superjunction structure 40 can be defined through a mask, the second conductive type doping ions are injected to form a second conductive type doping region, then the position and the pattern of the first conductive type superjunction 41 are defined through the mask, the first conductive type doping ions are injected into the second conductive type doping region to form the first conductive type superjunction 41, and the region without the first conductive type doping ions in the second conductive type doping region is the second conductive type superjunction 42.
S1220, forming a second semiconductor epitaxial sub-layer of the first conductivity type on the side, far away from the substrate, of the first semiconductor epitaxial sub-layer, and performing ion implantation in the second semiconductor epitaxial sub-layer to form a body region and a contact region of the first conductivity type.
Specifically, referring to fig. 10, the second semiconductor epitaxial sublayer 202 is continuously grown, and the material of the second semiconductor epitaxial sublayer 202 may be the same as that of the first semiconductor epitaxial sublayer 201.
Referring to fig. 11, for the semiconductor power device shown in fig. 3 and 4, the implantation of the second conductivity type ions and the implantation of the first conductivity type ions are performed from the side of the second semiconductor epitaxial sublayer 202 away from the substrate 10, thereby forming the body region 22 and the first conductivity type contact region 23, respectively.
Referring to fig. 12, for the semiconductor power device shown in fig. 5 and 6, before ion implantation into the second semiconductor epitaxial sublayer 202 to form the body region 22 and the first conductivity type contact region 23, further comprising implanting ions of the first conductivity type to form a current diffusion layer 25 between the body region 22 and the drift region 21.
S1230, performing ion implantation again at two ends of the first conductive type contact region to form a second conductive type contact region, wherein the contact region comprises the first conductive type contact region and the second conductive type contact region, and the distance from the bottom surface of the second conductive type contact region to the substrate is larger than the distance from the bottom surface of the gate trench to the substrate.
Specifically, the position and pattern of the second conductivity type contact region 24 are defined by the mask, and the second conductivity type ions are implanted to form the second conductivity type contact region 24. The second conductive type ion implantation depth is shallower in this step when the semiconductor power device shown in fig. 3 and 5 is formed, and is deeper in this step when the semiconductor power device shown in fig. 4 and 6 is formed. Referring to fig. 13, the depth of the second conductivity type ion implantation during formation of the structure of fig. 6 is schematically illustrated.
On the basis of the above embodiments, optionally, the gate trench includes a first-stage sub-trench 01 and a second-stage sub-trench 02 located at the bottom of the first-stage sub-trench 01, where the width of the second-stage sub-trench 02 is smaller than the width of the first-stage sub-trench 01. Step S130 forms a gate trench on a surface of the semiconductor epitaxial layer on a side away from the substrate, including:
and S1310, sequentially etching the contact region, the body region and the drift region from the surface of the semiconductor epitaxial layer, which is far away from the substrate, until the top of the super junction structure is reached, so as to form a first-stage sub-trench.
Specifically, referring to fig. 14, a first level sub-trench 01 may be formed on a side of the semiconductor epitaxial layer 20 remote from the substrate 10 by a photolithography process. The specific steps may include depositing SiO 2 as a first mask layer on a surface of the semiconductor epitaxial layer 20 on a side away from the substrate 10 by a deposition process such as CVD, spin-coating a photoresist PR on the surface of the first mask layer, forming a photoresist PR of a desired pattern by exposure and development, and then etching the first mask layer based on the patterned photoresist PR, thereby patterning the first mask layer. The patterned first mask layer exposes the preset position of the gate trench. Based on the patterned first mask layer, the semiconductor epitaxial layer 20 is etched until the top of the superjunction structure 40, forming a first level sub-trench 01. The etching process may be a plasma dry etching process, such as RIE or an ICP etching process.
S1320, etching the super junction of the first conductivity type at the bottom part thickness of the first-stage sub-groove to form a second-stage sub-groove.
Specifically, referring to fig. 15, siO 2 is deposited as a second mask layer on the bottom and sidewalls of the first-stage sub-trench 01, the second mask layer is patterned to form an opening exposing only the first-conductivity-type super junction 41, the first-conductivity-type super junction 41 is etched to form a second-stage sub-trench 02 at a thickness of a bottom portion of the first-stage sub-trench 01, and the first mask layer and the second mask layer are removed.
Based on the above embodiments, optionally, step S140 forms the gate structure 30 in the gate trench, including:
s1410, forming a gate insulation on the sidewall and bottom of the gate trench.
S1420, forming a polysilicon gate in the cavity surrounded by the gate insulating layer, wherein the gate structure comprises the gate insulating layer and the polysilicon gate.
Specifically, referring to fig. 16, the material of the gate insulating layer 32 may include at least one of SiO 2 and Al 2O3, and the gate insulating layer 32 may be prepared by at least one of ALD (Atomic Layer Deposition ), thermal oxygen, and wet method. A polysilicon material is filled in the gate trench to form a polysilicon gate 31. The gate structure 30 includes a polysilicon gate 31 and a gate insulating layer 32 surrounding the polysilicon gate 31.
Optionally, the method for manufacturing the semiconductor power device further includes:
an interlayer insulating layer ILD is formed on the upper surface of the gate structure 30, and is used for isolating the second electrode 60 from the gate structure 30;
forming a second electrode 60 on a surface of the semiconductor epitaxial layer 20 on a side remote from the substrate 10, the second electrode 60 being in contact with the first conductive type contact region 23 and the second conductive type contact region 24;
a passivation layer 70 and a protective layer 80 sequentially formed on a side of the second electrode 60 remote from the substrate, wherein a material of the passivation layer 70 may include silicon nitride (SiN), and a material of the protective layer 80 may include polyimide;
The first electrode 50 is formed on the surface of the substrate 10 on the side remote from the semiconductor epitaxial layer 20.
The embodiment of the invention also provides a power module, which comprises a substrate and at least one semiconductor power device according to any embodiment of the invention, wherein the substrate is used for bearing the semiconductor power device. Has the same technical effects and is not described in detail herein.
The embodiment of the invention also provides a power conversion circuit which is used for one or more of current conversion, voltage conversion and power factor correction, and comprises a circuit board and at least one semiconductor power device according to any embodiment of the invention, wherein the semiconductor power device is electrically connected with the circuit board. Has the same technical effects and is not described in detail herein.
The embodiment of the invention also provides a vehicle, which comprises a load and the power conversion circuit according to any embodiment of the invention, wherein the power conversion circuit is used for converting alternating current into direct current, converting alternating current into alternating current, converting direct current into direct current or converting direct current into alternating current and then inputting the alternating current into the load. Has the same technical effects and is not described in detail herein.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (14)
1. A semiconductor power device, comprising:
A substrate;
the semiconductor epitaxial layer is positioned on one side of the substrate and comprises a drift region, a body region and a contact region which are sequentially far away from the substrate;
The semiconductor epitaxial layer comprises a substrate, a grid electrode groove and a grid electrode structure, wherein the grid electrode groove is positioned on the surface of one side of the semiconductor epitaxial layer, which is far away from the substrate;
the super junction structure is positioned in the drift region and at one side of the grid structure close to the substrate, and comprises a first conductive type super junction and second conductive type super junctions which are positioned at two opposite sides of the first conductive type super junction in a direction parallel to the substrate, wherein the second conductive type super junction is opposite to the conductive type of the drift region, and the second conductive type super junction covers a corner between the surface of the grid structure close to one side of the substrate and the side wall.
2. The semiconductor power device of claim 1, wherein,
The contact region includes a first conductivity type contact region and a second conductivity type contact region; the first conductive type contact region is positioned between the gate trench and the second conductive type contact region and is positioned at one side of the body region away from the substrate;
wherein the distance from the second conductive type contact region to the substrate is greater than the distance from the superjunction structure to the substrate.
3. The semiconductor power device according to claim 1, wherein the gate trench comprises at least two sub-trenches, the at least two sub-trenches are sequentially arranged in a direction that the semiconductor epitaxial layer points to the substrate, and a sub-trench width close to the substrate in two adjacent sub-trenches is smaller than a sub-trench width far from the substrate;
the bottom of the sub-groove closest to the substrate is provided with the first conductive type super junction, and the second conductive type super junction extends to a step surface between two adjacent sub-grooves closest to the substrate along the side wall of the sub-groove closest to the substrate.
4. The semiconductor power device of claim 3, wherein the gate trench comprises two sub-trenches, a first level sub-trench and a second level sub-trench at a bottom of the first level sub-trench, respectively;
The second-conductivity-type superjunction is positioned at two opposite sides of the first-conductivity-type superjunction and extends to the first-stage sub-trench along the side wall of the second-stage sub-trench.
5. The semiconductor power device of claim 2, wherein,
The thickness of the second conductive type contact region is smaller than the total thickness of the first conductive type contact region and the body region;
Or the second conductive type contact region is positioned on one side of the first conductive type contact region away from the gate trench and one side of the body region away from the gate trench, and the thickness of the second conductive type contact region is greater than or equal to the total thickness of the first conductive type contact region and the body region.
6. The semiconductor power device of claim 5, wherein the semiconductor epitaxial layer further comprises a current spreading layer;
the current diffusion layer is located between the body region and the drift region in a case where the second conductivity type contact region is located on a side of the body region away from the substrate, the thickness of the second conductivity type contact region being smaller than the total thickness of the first conductivity type contact region and the body region;
The current diffusion layer is located between the body region and the drift region, and between the second conductivity type contact region and the drift region, in a case where the second conductivity type contact region is located on a side of the first conductivity type contact region and the body region away from the gate trench, and a thickness of the second conductivity type contact region is greater than or equal to a total thickness of the first conductivity type contact region and the body region.
7. A method for manufacturing a semiconductor power device is characterized by being used for manufacturing the semiconductor power device according to any one of claims 1-6,
Providing a substrate;
Forming a semiconductor epitaxial layer on one side of a substrate, wherein the semiconductor epitaxial layer comprises a drift region, a body region and a contact region which are sequentially far away from the substrate, and a super junction structure positioned in the drift region, and the super junction structure comprises a first conductive type super junction and second conductive type super junctions positioned on two opposite sides of the first conductive type super junction in a direction parallel to the substrate, and the second conductive type super junction is opposite to the drift region in conductivity type;
forming a grid groove on the surface of one side of the semiconductor epitaxial layer far away from the substrate;
And forming a gate structure in the gate trench, wherein the super junction structure is positioned on one side of the gate structure close to the substrate, and the second conductivity type super junction covers a corner between a surface of the gate structure close to one side of the substrate and a side wall.
8. The method of manufacturing a semiconductor power device according to claim 7, wherein forming a semiconductor epitaxial layer on one side of the substrate comprises:
Forming a first semiconductor epitaxial sub-layer of a first conductivity type on one side of the substrate, and performing ion implantation in the first semiconductor epitaxial sub-layer to form the superjunction structure;
forming a second semiconductor epitaxial sub-layer of the first conductivity type on one side of the first semiconductor epitaxial sub-layer far away from the substrate, and performing ion implantation in the second semiconductor epitaxial sub-layer to form a body region and a first conductivity type contact region;
and performing ion implantation again at two ends of the first conductive type contact region to form a second conductive type contact region, wherein the contact region comprises the first conductive type contact region and the second conductive type contact region, and the distance from the bottom surface of the second conductive type contact region to the substrate is larger than the distance from the bottom surface of the gate trench to the substrate.
9. The method of manufacturing a semiconductor power device according to claim 8, further comprising, before performing ion implantation in the second semiconductor epitaxial sublayer to form a body region and a first conductivity type contact region:
A current spreading layer is formed between the body region and the drift region.
10. The method of manufacturing a semiconductor power device according to claim 7, wherein the gate trench comprises a first-stage sub-trench and a second-stage sub-trench located at a bottom of the first-stage sub-trench;
Forming a gate groove on the surface of the side, away from the substrate, of the semiconductor epitaxial layer, wherein the gate groove comprises the following steps:
sequentially etching the contact region, the body region and the drift region from the surface of the semiconductor epitaxial layer far away from one side of the substrate to the top of the super junction structure to form a first-stage sub-groove;
Etching the super junction of the first conductivity type at the bottom of the first-stage sub-groove to form a second-stage sub-groove, wherein the width of the second-stage sub-groove is smaller than that of the first-stage sub-groove.
11. The method of manufacturing a semiconductor power device as defined in claim 7, wherein forming a gate structure in the gate trench comprises
Forming a gate insulating layer on the side wall and the bottom of the gate trench;
and forming a polysilicon gate in the cavity surrounded by the gate insulating layer, wherein the gate structure comprises the gate insulating layer and the polysilicon gate.
12. A power module comprising a substrate and at least one semiconductor power device according to any of claims 1-6, said substrate being arranged to carry said semiconductor power device.
13. A power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction;
the power conversion circuit comprising a circuit board and at least one semiconductor power device according to any one of claims 1-6, the semiconductor power device being electrically connected to the circuit board.
14. A vehicle comprising a load and the power conversion circuit according to claim 13, wherein the power conversion circuit is configured to convert alternating current into direct current, alternating current into alternating current, direct current into direct current, or direct current into alternating current, and then input the alternating current into the load.
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