CN117809726A

CN117809726A - Dynamic random access memory test method and device

Info

Publication number: CN117809726A
Application number: CN202211166055.0A
Authority: CN
Inventors: 章恒嘉
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-09-23
Filing date: 2022-09-23
Publication date: 2024-04-02
Also published as: WO2024060378A1

Abstract

The disclosure provides a method and a device for testing a dynamic random access memory, and relates to the technical field of memories. The dynamic random access memory comprises a substrate and a plurality of memory cells, each memory cell comprises a memory capacitor and a first transistor, and the memory capacitor of each memory cell is electrically connected with the substrate through the corresponding first transistor. The method comprises the following steps: charging storage capacitors of the respective memory cells by switching a voltage applied to the substrate from a first voltage to a second voltage, the second voltage being higher than the first voltage; and after the storage capacitor of each storage unit is charged for a preset time, testing the dynamic random access memory. The method can shorten the time of writing the background in the test item and improve the test efficiency.

Description

Dynamic random access memory test method and device

Technical Field

The disclosure relates to the technical field of memories, and in particular relates to a method and a device for testing a dynamic random access memory.

Background

As the proportion of the memory in the System On Chip (SOC) increases, the quality of the memory also affects the overall performance of the System On Chip. After the chip is manufactured, testing is an important step for detecting memory failures, such as wafer level testing and package level testing.

Some dynamic random access memory (Dynamic Random Access Memory, DRAM) test methods perform basic function tests through March pattern (March pattern) and find failure modes. Background writing is required in various travel mode test items. In the related art, when writing the background, the Active is performed on a word line by word line basis, after each word line is activated, the Active is written on a bit line by bit line basis (Write), and then the Active is performed on the next word line by pre-charge after the Active is written on the bit line, and the test time spent by the command actions is long, so that the test efficiency is affected.

As described above, how to shorten the time for writing the background in the test item to improve the test efficiency is a problem to be solved.

The above information disclosed in the background section is only for enhancement of understanding of the background of the disclosure and therefore it may include information that does not form the prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

The disclosure aims to provide a method and a device for testing a dynamic random access memory, which at least reduce the time for writing a background in a test item to a certain extent so as to improve the test efficiency.

Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure.

According to an aspect of the present disclosure, there is provided a dynamic random access memory test method, the dynamic random access memory including a substrate and a plurality of memory cells, each memory cell including a storage capacitor and a first transistor, the storage capacitor of each memory cell being electrically connected to the substrate through a corresponding first transistor, the method comprising: charging storage capacitors of respective memory cells by switching a voltage applied to the substrate from a first voltage to a second voltage, the second voltage being higher than the first voltage; and after the storage capacitor of each storage unit is charged for a preset time, testing the dynamic random access memory.

According to an embodiment of the present disclosure, charging a storage capacitor of each memory cell by switching a voltage applied to the substrate from a first voltage to a second voltage includes: a first input signal is sent to an input of a voltage switching circuit to cause the voltage switching circuit to switch a voltage applied to the substrate from the first voltage to the second voltage.

According to an embodiment of the disclosure, the voltage switching circuit includes a first inverter, an input terminal of the first inverter is an input terminal of the voltage switching circuit, the first inverter is a CMOS transistor, a drain of an NMOS transistor and a drain of a PMOS transistor of the first inverter are connected to an output terminal of the voltage switching circuit, an input voltage of a source of the NMOS transistor of the first inverter is the first voltage, and an input voltage of a source of the PMOS transistor of the first inverter is the second voltage; transmitting a first input signal to an input terminal of a voltage switching circuit to cause the voltage switching circuit to switch a voltage applied to the substrate from the first voltage to the second voltage, comprising: the first input signal is sent to the first inverter input to turn off an NMOS transistor of the first inverter and turn on a PMOS transistor of the first inverter.

According to an embodiment of the disclosure, the voltage switching circuit includes a first inverter, an input terminal of the first inverter is an input terminal of the voltage switching circuit, a drain electrode of an NMOS transistor and a drain electrode of a PMOS transistor of the first inverter are connected to an output terminal of the voltage switching circuit, an input voltage of a source electrode of the PMOS transistor of the first inverter is the first voltage, and an input voltage of a source electrode of the NMOS transistor of the first inverter is the second voltage; transmitting a first input signal to an input terminal of a voltage switching circuit to cause the voltage switching circuit to switch a voltage applied to the substrate from the first voltage to the second voltage, comprising: the first input signal is sent to the first inverter input to turn on an NMOS transistor of the first inverter and turn off a PMOS transistor of the first inverter.

According to one embodiment of the present disclosure, after the storage capacitor of each storage unit is charged for a predetermined period of time, the testing the dynamic random access memory includes: after the storage capacitor of each storage unit is charged for a preset time, a second input signal is sent to the input end of the voltage switching circuit, so that the voltage switching circuit switches the voltage applied to the substrate from the second voltage to the first voltage; and testing the dynamic random access memory.

According to an embodiment of the disclosure, the plurality of storage units includes a target storage unit; testing the dynamic random access memory, including: and performing a read operation on the target storage unit to test the dynamic random access memory.

According to still another aspect of the present disclosure, there is provided a dynamic random access memory test device including a substrate and a plurality of memory cells, each memory cell including a storage capacitor and a first transistor, the storage capacitor of each memory cell being electrically connected to the substrate through a corresponding first transistor, the device comprising: a control module for charging storage capacitors of respective memory cells by switching a voltage applied to the substrate from a first voltage to a second voltage, the second voltage being higher than the first voltage; and the test module is used for testing the dynamic random access memory after the storage capacitor of each storage unit is charged for a preset time.

According to an embodiment of the disclosure, the control module is further configured to: a first input signal is sent to an input of a voltage switching circuit to cause the voltage switching circuit to switch a voltage applied to the substrate from the first voltage to the second voltage.

According to an embodiment of the disclosure, the voltage switching circuit includes a first inverter, an input terminal of the first inverter is an input terminal of the voltage switching circuit, the first inverter is a CMOS transistor, a drain of an NMOS transistor and a drain of a PMOS transistor of the first inverter are connected to an output terminal of the voltage switching circuit, an input voltage of a source of the NMOS transistor of the first inverter is the first voltage, and an input voltage of a source of the PMOS transistor of the first inverter is the second voltage; the control module is further configured to: the first input signal is sent to the first inverter input to turn off an NMOS transistor of the first inverter and turn on a PMOS transistor of the first inverter.

According to an embodiment of the disclosure, the voltage switching circuit includes a first inverter, an input terminal of the first inverter is an input terminal of the voltage switching circuit, a drain electrode of an NMOS transistor and a drain electrode of a PMOS transistor of the first inverter are connected to an output terminal of the voltage switching circuit, an input voltage of a source electrode of the PMOS transistor of the first inverter is the first voltage, and an input voltage of a source electrode of the NMOS transistor of the first inverter is the second voltage; the control module is further configured to: the first input signal is sent to the first inverter input to turn on an NMOS transistor of the first inverter and turn off a PMOS transistor of the first inverter.

According to an embodiment of the disclosure, the control module is further configured to: after the storage capacitor of each storage unit is charged for a preset time, a second input signal is sent to the input end of the voltage switching circuit, so that the voltage switching circuit switches the voltage applied to the substrate from the second voltage to the first voltage; and the test module is also used for testing the dynamic random access memory.

According to an embodiment of the disclosure, the plurality of storage units includes a target storage unit; the test module is further configured to: and performing a read operation on the target storage unit to test the dynamic random access memory.

According to still another aspect of the present disclosure, there is provided a dynamic random access memory test apparatus including a dynamic random access memory to be tested and a voltage switching circuit, wherein: the dynamic random access memory to be tested comprises a substrate and a plurality of memory cells, wherein each memory cell comprises a memory capacitor and a first transistor, and the memory capacitor of each memory cell is electrically connected with the substrate through the corresponding first transistor; the voltage switching circuit comprises an output end, and the output end of the voltage switching circuit is electrically connected with the substrate and is used for charging storage capacitors of all storage units by switching a voltage applied to the substrate from a first voltage to a second voltage, wherein the second voltage is higher than the first voltage.

According to an embodiment of the disclosure, the first transistor is an NMOS transistor, and the storage capacitor includes a first plate; the storage capacitor of each storage unit is electrically connected with the substrate through a corresponding first transistor, and comprises: the first polar plate of the storage capacitor of each storage unit is electrically connected with the drain electrode of the corresponding first transistor, and the P-type silicon substrate of the first transistor of each storage unit is electrically connected with the substrate.

According to an embodiment of the disclosure, the voltage switching circuit includes a first inverter, an input terminal of the first inverter is connected to an input terminal of the second inverter, and an output terminal of the first inverter is an output terminal of the voltage switching circuit.

According to an embodiment of the disclosure, the first inverter is a CMOS transistor.

According to an embodiment of the disclosure, a drain of the NMOS transistor and a drain of the PMOS transistor of the first inverter are connected to the output terminal of the voltage switching circuit, an input voltage of a source of the NMOS transistor of the first inverter is the first voltage, and an input voltage of a source of the PMOS transistor of the first inverter is the second voltage; the input end of the first inverter is used for receiving a first input signal so as to enable the NMOS transistor of the first inverter to be turned off and enable the PMOS transistor of the first inverter to be turned on.

According to an embodiment of the disclosure, the input terminal of the first inverter is further configured to receive a second input signal to turn on the NMOS transistor of the first inverter and turn off the PMOS transistor of the first inverter.

According to an embodiment of the disclosure, a drain of the NMOS transistor and a drain of the PMOS transistor of the first inverter are connected to the output terminal of the voltage switching circuit, an input voltage of a source of the PMOS transistor of the first inverter is the first voltage, and an input voltage of a source of the NMOS transistor of the first inverter is the second voltage; the input end of the first inverter is used for receiving a first input signal so as to enable the NMOS transistor of the first inverter to be conducted and enable the PMOS transistor of the first inverter to be cut off.

According to an embodiment of the disclosure, the input terminal of the first inverter is further configured to receive a second input signal to turn off the NMOS transistor of the first inverter and turn on the PMOS transistor of the first inverter.

According to an embodiment of the present disclosure, the output terminal of the voltage switching circuit is electrically connected to the substrate through a connection plug.

According to still another aspect of the present disclosure, there is provided an electronic apparatus including: a memory, a processor, and executable instructions stored in the memory and executable in the processor, the processor implementing any of the methods described above when executing the executable instructions.

According to yet another aspect of the present disclosure, there is provided a computer-readable storage medium having stored thereon computer-executable instructions which, when executed by a processor, implement any of the methods described above.

According to the dynamic random access memory testing method provided by the embodiment of the disclosure, through switching the voltage applied to the substrate of the dynamic random access memory from the first voltage to the second voltage higher than the first voltage, each memory cell is charged through the corresponding first transistor and the storage capacitor electrically connected with the substrate, then after the storage capacitor of each memory cell is charged for a preset time, the dynamic random access memory is tested, and the writing of the test background can be realized by replacing the command actions of activating, writing and precharging word lines by bit lines in the related art, so that the time of activating, writing and precharging command actions can be saved, the time of writing the background in a test item is shortened, and the testing efficiency is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 illustrates a schematic flow diagram of a DRF test project.

Fig. 2 illustrates a flow chart of a write background operation.

Fig. 3 shows a schematic diagram of a DRAM architecture in an embodiment of the present disclosure.

Fig. 4 is a schematic diagram of a side view of a wafer in the DRAM array shown in fig. 3.

FIG. 5 illustrates a flow chart of a method of dynamic random access memory testing in an embodiment of the present disclosure.

Fig. 6 is a schematic diagram of a voltage switching circuit, according to an example embodiment.

Fig. 7 is a schematic diagram of another voltage switching circuit shown according to an example embodiment.

Fig. 8 is a flowchart of another dynamic random access memory test method according to the embodiments shown in fig. 5 to 7.

Fig. 9 is a flow chart illustrating a writing background according to fig. 8.

Fig. 10 is a flow chart of a read operation according to the one shown in fig. 8.

FIG. 11 illustrates a block diagram of a dynamic random access memory test device in an embodiment of the disclosure.

Fig. 12 shows a schematic structural diagram of an electronic device in an embodiment of the disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the aspects of the disclosure may be practiced without one or more of the specific details, or with other methods, apparatus, steps, etc. In other instances, well-known structures, methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless explicitly specified otherwise. The symbol "/" generally indicates that the context-dependent object is an "or" relationship.

In the present disclosure, unless explicitly specified and limited otherwise, terms such as "connected" and the like are to be construed broadly and, for example, may be electrically connected or may communicate with each other; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

The related art adopts a March pattern (March pattern) for basic function test, and finds out a failure mode. The failure modes of the March pattern test overlay memory include Stuck At Fault (SAF), coupling Fault (CF), transition Fault (TF), address decoder Fault (Address decoder Fault, AF), proximity sensitive Fault (Neighbor Pattern Sensitive Fault, NPSF), data retention Fault (Data Rentention Fault, DRF), and the like. Thus, the March pattern test is a more common algorithm for DRAM testing.

March pattern includes a variety of test vector types, such as March A, march B, march LR, march SS, MATS, MATS+, etc., and all of the various March pattern test vectors exemplified by these include a write of "1" (write 1) for all memory cells (cells) of the DRAM array to be tested as a test background. It can be seen that the written background is an unavoidable act of the DRAM test item.

Fig. 1 illustrates a schematic flow diagram of a DRF test project. As shown in fig. 1, when performing a DRF test on the memory array 102, first writing "0" on Bit Line (BL) and Word Line (BL) (S1002), and after waiting for the completion of writing, reading "0" on Bit Line and Word Line (BL) (S1004); then, the "1" is written on a bit line-by-word line basis (S1006), and after the completion of the writing, the "1" is read on a bit line-by-word line basis (S1008). The flow of writing background in which "1" is written on a bit line-by-word line basis can be referred to in fig. 2.

Fig. 2 illustrates a flow chart of a write background operation. As shown in fig. 2, taking an example that the memory array 102 is connected to X word lines and Y bit lines, the current word line is activated (S202), and "1" is written into each bit line after each word line is activated (S204), and when "1" is written, the time for n (n is a positive integer) chips to unselected (Device Deselected, DES) instructions (S206) is waited, wherein the DES instructions are instructions defined in the DRAM command truth table. Then, after the writing of Y bit lines is traversed (S207), the current word line is precharged (S208), and the next word line is activated to traverse X word lines (S209).

In various DRAM test items including the test flows of fig. 1 and 2, writing the background is an unavoidable operation, and in the chip manufacturing process, the proportion of the cost occupied by the chip test is always high, so that the manufacturing cost can be effectively saved by shortening the writing background time. Further, the command operation such as Active, write, precharge used in writing the background may not be able to distinguish whether the failure is a wafer (wafer) defect or abnormal command operation when the DRAM failure occurs, and the accuracy of the test result may be affected.

Therefore, the present disclosure provides a method, in which a voltage applied to a substrate of a dynamic random access memory is switched from a first voltage to a second voltage higher than the first voltage, and each memory cell is charged through a storage capacitor electrically connected to the substrate by a corresponding first transistor, so as to replace a command action of activating, writing and precharging a word line by word line in the related art, to implement writing of a test background, thereby saving time of the command actions of activating, writing and precharging, reducing time of writing the background in a test item, improving test efficiency, and also avoiding whether a failure is a wafer defect or a command action when a DRAM failure occurs in a test, and improving accuracy of a test result.

Fig. 3 shows an exemplary DRAM architecture 30 to which the dynamic random access memory test method or dynamic random access memory test apparatus of the present disclosure may be applied, with the DRAM architecture 30 being illustrated as the dynamic random access memory to be tested in an embodiment of the present disclosure.

The architecture 30 of the dynamic random access memory to be tested may include a plurality of memory cells, two memory cells 3062 and 3064 are shown in fig. 3, referring to fig. 4, a memory capacitor 4062 and a memory capacitor 4064 in fig. 4 are connected to drain electrodes 4082 and 4084 of two NMOS transistors through NC (Node Contact), respectively, the two transistors share a source 3066, the memory capacitor 4062 and the connected transistor form the memory cell 3062 together, and the memory capacitor 4064 and the connected transistor form the memory cell 3064 together. The two (first) transistors share a source 3066 to BL 304 and the gates 4086 and 4088 of the two transistors are to WL 306. The memory cell array of fig. 3 may be disposed on the substrate 402 of fig. 4.

Fig. 4 is a schematic diagram of a side view of a memory cell in the DRAM array shown in fig. 3. Referring to fig. 3, fig. 4 shows a side cross-sectional view of a group 306 of memory cells sharing two sources 3066. A common Top Cell Plate (TCP) 404 of the storage capacitor 4062 and the storage capacitor 4064, and a bottom Plate (i.e., a first Plate) of the storage capacitor 4062 and the storage capacitor 4064 are connected to the drain 4082 and the drain 4084 of the two transistors, respectively, through NC, and a P-type silicon substrate (also referred to as a P-well) of the two transistors is disposed on the substrate 402 to be electrically connected to the substrate so that the storage capacitor 4062 and the storage capacitor 4064 are electrically connected to the substrate through a PN junction of the two transistors.

In some embodiments, a connection plug 410 may be provided that is electrically connected to the substrate 402, and a normal operating voltage V1 may be applied to the substrate 402, i.e., to the lower plates of the storage capacitors 4062 and 4064, through the connection plug 410. Shallow trench isolation (Shallow Trench Isolation, STI) is provided between the connection plug 410 and the PN junction.

In some embodiments, a voltage switching circuit may be provided for changing the voltage applied to the substrate 402, for example, by electrically connecting an output terminal of the voltage switching circuit to the substrate 402 through the connection plug 410, switching the voltage applied to the substrate 402 from a first voltage to a second voltage higher than the first voltage, and charging the storage capacitor 4062 and the storage capacitor 4064.

It should be understood that the number of memory cells in fig. 3 is merely illustrative. There may be any number of memory cells, as desired for implementation.

FIG. 5 is a flow chart illustrating a method of dynamic random access memory testing, according to an exemplary embodiment. The method shown in fig. 5 may be applied to a plurality of memory cells shown in fig. 3 and 4, for example.

Referring to fig. 5, a method 50 provided by an embodiment of the present disclosure may include the following steps.

In step S502, the storage capacitor of each memory cell is charged by switching the voltage applied to the substrate from the first voltage to a second voltage, the second voltage being higher than the first voltage.

In some embodiments, a voltage switching circuit may be provided in electrical communication with the substrate, the voltage switching circuit being operable to switch a voltage applied to the substrate from a first voltage to a second voltage by sending a first input signal to an input of the voltage switching circuit. The specific embodiments can be seen with reference to fig. 6 and 7.

In step S504, the dynamic random access memory is tested after the storage capacitor of each memory cell is charged for a predetermined period of time.

In some embodiments, the dynamic random access memory may be tested after waiting a preset number of command clocks (tCK), which may be, for example, the duration of n DES instructions, after switching the voltage applied to the substrate from the first voltage to the second voltage. The specific embodiments can be seen with reference to fig. 8 and 9.

According to the method for testing the dynamic random access memory, the voltage applied to the substrate of the dynamic random access memory is switched from the first voltage to the second voltage higher than the first voltage, the storage capacitors of the storage units, which are electrically connected with the substrate through the corresponding first transistors, are charged, and then after the storage capacitors of the storage units are charged for a preset time, the dynamic random access memory is tested. The write-in test background is realized by changing the Bulk voltage of the DRAM to replace the instruction actions of activating, writing and precharging by each word line in the related test project flow, so that the time of activating, writing and precharging the instruction actions is saved while the test coverage rate of the related technology is reached, the time of writing the background in the test project is shortened, the test efficiency is improved, the time of writing the background is shortened, and the manufacturing cost is also effectively saved. And because the method of the embodiment of the disclosure does not carry out instruction action when writing the background, the problem that whether the fault comes from a wafer defect or the instruction action cannot be clearly distinguished when the DRAM fault occurs in the test can be avoided, and the accuracy of the test result is improved.

Fig. 6 is a schematic diagram of a voltage switching circuit, according to an example embodiment. The voltage switching circuit shown in fig. 6 may be used to apply a voltage to the substrate of fig. 4, implementing the method shown in fig. 5.

As shown in fig. 6, the voltage switching circuit may include an output 604, with the output 604 of the voltage switching circuit being electrically connected to the substrate 402. The voltage switching circuit may include a first inverter having an input terminal that is an input terminal of the voltage switching circuit for receiving the input signal 602. The first inverter may be a CMOS transistor, the drain of the NMOS transistor M2 and the drain of the PMOS transistor M1 of the first inverter are connected to the output end 604 of the voltage switching circuit, the input voltage of the source of the NMOS transistor M2 of the first inverter is the first voltage V1, and the input voltage of the source of the PMOS transistor M1 of the first inverter is the second voltage V2.

In some embodiments, the first voltage V1 may be a normal operating voltage, for example Vcc (supply voltage of the circuit)/2; the second voltage V2 may be a high voltage, for example, a bit line high Voltage (VBLH).

Referring to fig. 6, an input signal 602 sent to an input terminal of the first inverter may be a low-level first input signal to turn off an NMOS transistor M2 of the first inverter and turn on a PMOS transistor M1 of the first inverter, thereby implementing switching of a voltage applied to the substrate from a first voltage to a second voltage, i.e., applying a high voltage to a lower plate of each storage capacitor. The voltage applied to the upper electrode plate of each storage capacitor is the normal working voltage of the upper electrode plate, and the second voltage is higher than the normal working voltage of the upper electrode plate, so that the storage capacitors of each storage unit can be charged.

In some embodiments, the input signal 602 sent to the input terminal of the first inverter may be a high level second input signal, so that the NMOS transistor M2 of the first inverter is turned on, and the PMOS transistor M2 of the first inverter is turned off, so that the first voltage is recovered to be applied to the substrate, and the storage capacitor of each memory cell is stopped from being charged.

Fig. 7 is a schematic diagram of another voltage switching circuit shown according to an example embodiment. The voltage switching circuit shown in fig. 7 may be used to apply a voltage to the substrate of fig. 4, implementing the method shown in fig. 5.

As shown in fig. 7, the voltage switching circuit may include an output 704, the output 704 of the voltage switching circuit being electrically connected to the substrate 402. The voltage switching circuit may include a first inverter having an input terminal that is an input terminal of the voltage switching circuit for receiving the input signal 702. The drain of the NMOS transistor M4 and the drain of the PMOS transistor M3 of the first inverter are connected to the output terminal 704 of the voltage switching circuit, the input voltage of the source of the PMOS transistor M3 of the first inverter is the first voltage V1, and the input voltage of the source of the NMOS transistor M4 of the first inverter is the second voltage V2.

In some embodiments, the first voltage V1 may be a normal operating voltage, such as Vcc/2; the second voltage V2 may be a high voltage, for example, a bit line high Voltage (VBLH).

Referring to fig. 7, the input signal 702 transmitted to the input terminal of the first inverter may be a high-level first input signal to turn on the NMOS transistor M4 of the first inverter and turn off the PMOS transistor M3 of the first inverter, thereby realizing switching of the voltage applied to the substrate from the first voltage to the second voltage, i.e., applying a high voltage to the lower plate of each storage capacitor. The voltage applied to the upper electrode plate of each storage capacitor is the normal working voltage of the upper electrode plate, and the second voltage is higher than the normal working voltage of the upper electrode plate, so that the storage capacitors of each storage unit can be charged.

In some embodiments, the input signal 702 sent to the input terminal of the first inverter may also be a low level second input signal, so that the NMOS transistor M4 of the first inverter is turned off, and the PMOS transistor M3 of the first inverter is turned on, so as to resume the application of the first voltage to the substrate, and stop charging the storage capacitor of each memory cell.

Referring to fig. 8, a method 80 provided by an embodiment of the present disclosure may include the following steps.

In step S802, the storage capacitor of each memory cell is charged by switching the voltage applied to the substrate from the first voltage to a second voltage, the second voltage being higher than the first voltage.

In some embodiments, the voltage applied to the substrate may be switched from the first voltage to the second voltage using the voltage switching circuit shown in fig. 6 or fig. 7, and the specific implementation may refer to fig. 6 and fig. 7.

In step S804, after the storage capacitors of the respective memory cells are charged for a predetermined period of time, a second input signal is transmitted to the input terminal of the voltage switching circuit to cause the voltage switching circuit to switch the voltage applied to the substrate from the second voltage to the first voltage.

In some embodiments, after the storage capacitor of each memory cell is charged for a predetermined period of time, for example, after waiting for a preset number of command clocks, the voltage applied to the substrate may be switched from the second voltage to the first voltage by sending a second input signal to the input terminal of the voltage switching circuit, i.e., the charging of the storage capacitor of each memory cell is stopped.

In step S806, a read operation is performed on the target memory cell to test the dynamic random access memory.

In some embodiments, after the capacitor is charged, i.e. written with "1", in step S804, the target memory cell is read according to the pattern of the test item, and the embodiment can refer to fig. 10.

Fig. 9 is a flow chart illustrating a writing background according to fig. 8. Referring to fig. 8, the operation of switching the voltage applied to the substrate from the first voltage to the second voltage in step S802 may be referred to as entering the design for testability (Entry Design For Test, entry DFT), and the operation of switching the voltage applied to the substrate from the second voltage to the first voltage in step S804 may be referred to as exiting the design for testability (Exit DFT). As shown in fig. 9, when writing the background using the method shown in fig. 8, the testability design may be entered first (S902), and then after waiting for the duration of n DES instructions (S904), the testability design may be exited (S906).

Referring to fig. 2, when writing a background "1" to the memory cell array of X word lines and Y bit lines by the method of fig. 2, the required writing time is n×y×x DES instructions. The writing time of the method adopting the embodiment of the disclosure is Entry DFT+n DES instructions+exit DFT, and the total time of DFT Entry and Exit is not more than 10tCK, and the writing time is irrelevant to the row and column number of the memory cell array. Thus the time to write background "1" is reduced (n X Y X) - (Entry dft+n+exit DFT), i.e. the test time is greatly reduced.

Fig. 10 is a flow chart of a read operation according to the one shown in fig. 8. As shown in fig. 10, taking a read target memory cell as an example, a word line connected to the target memory cell is activated (S1002), and after the word line is activated, "1" is read on a bit line connected to the target memory cell (S1004), n DES instructions are waited for when "1" is read (S1006), and then the word line connected to the target memory cell is precharged (S1008).

In the case that the fail bit is obtained by writing "1" by the method shown in fig. 2 and reading by the method shown in fig. 10, then writing "1" by the method shown in fig. 5 or fig. 8 and reading by the method shown in fig. 10, it can be verified whether the fail bit is caused by the defect of the wafer itself or by the Write operation abnormality. The methods provided by the embodiments of fig. 5 and 8 may also assist in verifying that Write operations are abnormal.

FIG. 11 is a block diagram illustrating a dynamic random access memory test device, according to an example embodiment. The apparatus shown in fig. 11 can be applied to a plurality of memory cells shown in fig. 3 and 4, for example.

Referring to fig. 11, an apparatus 110 provided by an embodiment of the present disclosure may include a control module 1102 and a test module 1104.

The control module 1102 may be configured to charge the storage capacitance of each memory cell by switching a voltage applied to the substrate from a first voltage to a second voltage, the second voltage being higher than the first voltage.

The control module 1102 may also be configured to send a first input signal to an input of the voltage switching circuit to cause the voltage switching circuit to switch a voltage applied to the substrate from a first voltage to a second voltage.

The control module 1102 may be further configured to send a first input signal to the first inverter input to turn off the NMOS transistor of the first inverter and turn on the PMOS transistor of the first inverter.

The control module 1102 may be further configured to send a first input signal to the first inverter input to turn on the NMOS transistor of the first inverter and turn off the PMOS transistor of the first inverter.

The control module 1102 may be further configured to send a second input signal to the input terminal of the voltage switching circuit after the storage capacitor of each storage cell is charged for a predetermined period of time, so that the voltage switching circuit switches the voltage applied to the substrate from the second voltage to the first voltage.

The test module 1104 may be used to test the DRAM after the storage capacitor of each memory cell is charged for a predetermined period of time.

The test module 1104 may also be used to perform read operations on the target memory cells to test the DRAM.

Specific implementation of each module in the apparatus provided in the embodiments of the present disclosure may refer to the content in the foregoing method, which is not described herein again.

Fig. 12 shows a schematic structural diagram of an electronic device in an embodiment of the disclosure. It should be noted that the apparatus shown in fig. 12 is only an example of a computer system, and should not impose any limitation on the functions and the scope of use of the embodiments of the present disclosure.

As shown in fig. 12, the apparatus 1200 includes a Central Processing Unit (CPU) 1201, which can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 1202 or a program loaded from a storage section 1208 into a Random Access Memory (RAM) 1203. In the RAM 1203, various programs and data required for the operation of the device 1200 are also stored. The CPU1201, ROM 1202, and RAM 1203 are connected to each other through a bus 1204. An input/output (I/O) interface 1205 is also connected to the bus 1204.

The following components are connected to the I/O interface 1205: an input section 1206 including a keyboard, a mouse, and the like; an output portion 1207 including a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, a speaker, and the like; a storage section 1208 including a hard disk or the like; and a communication section 1209 including a network interface card such as a LAN card, a modem, or the like. The communication section 1209 performs communication processing via a network such as the internet. The drive 1210 is also connected to the I/O interface 1205 as needed. A removable medium 1211 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is installed as needed on the drive 1210 so that a computer program read out therefrom is installed into the storage section 1208 as needed.

In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network via the communication portion 1209, and/or installed from the removable media 1211. The above-described functions defined in the system of the present disclosure are performed when the computer program is executed by a Central Processing Unit (CPU) 1201.

It should be noted that the computer readable medium shown in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The modules described in the embodiments of the present disclosure may be implemented in software or hardware. The described modules may also be provided in a processor, for example, as: a processor includes a control module and a test module. The names of these modules do not in any way constitute a limitation of the module itself, for example, a control module may also be described as "a module that sends control signals to the connected circuits".

As another aspect, the present disclosure also provides a computer-readable medium that may be contained in the apparatus described in the above embodiments; or may be present alone without being fitted into the device. The computer readable medium carries one or more programs which, when executed by a device, cause the device to include:

charging storage capacitors of the respective memory cells by switching a voltage applied to the substrate from a first voltage to a second voltage, the second voltage being higher than the first voltage; and after the storage capacitor of each storage unit is charged for a preset time, testing the dynamic random access memory.

Exemplary embodiments of the present disclosure are specifically illustrated and described above. It is to be understood that this disclosure is not limited to the particular arrangements, instrumentalities and methods of implementation described herein; on the contrary, the disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A method of testing a dynamic random access memory, the dynamic random access memory comprising a substrate and a plurality of memory cells, each memory cell comprising a storage capacitor and a first transistor, the storage capacitor of each memory cell being electrically connected to the substrate through a corresponding first transistor, the method comprising:

Charging storage capacitors of respective memory cells by switching a voltage applied to the substrate from a first voltage to a second voltage, the second voltage being higher than the first voltage;

and after the storage capacitor of each storage unit is charged for a preset time, testing the dynamic random access memory.

2. The method of claim 1, wherein charging the storage capacitance of each memory cell by switching a voltage applied to the substrate from a first voltage to a second voltage, comprises:

a first input signal is sent to an input of a voltage switching circuit to cause the voltage switching circuit to switch a voltage applied to the substrate from the first voltage to the second voltage.

3. The method of claim 2, wherein the voltage switching circuit comprises a first inverter, an input terminal of the first inverter is an input terminal of the voltage switching circuit, the first inverter is a CMOS transistor, a drain of an NMOS transistor of the first inverter and a drain of a PMOS transistor are connected to the output terminal of the voltage switching circuit, an input voltage of a source of the NMOS transistor of the first inverter is the first voltage, and an input voltage of a source of the PMOS transistor of the first inverter is the second voltage;

Transmitting a first input signal to an input terminal of a voltage switching circuit to cause the voltage switching circuit to switch a voltage applied to the substrate from the first voltage to the second voltage, comprising:

the first input signal is sent to the first inverter input to turn off an NMOS transistor of the first inverter and turn on a PMOS transistor of the first inverter.

4. The method of claim 2, wherein the voltage switching circuit comprises a first inverter, an input terminal of the first inverter is an input terminal of the voltage switching circuit, a drain electrode of an NMOS transistor of the first inverter and a drain electrode of a PMOS transistor of the first inverter are connected with an output terminal of the voltage switching circuit, an input voltage of a source electrode of the PMOS transistor of the first inverter is the first voltage, and an input voltage of a source electrode of the NMOS transistor of the first inverter is the second voltage;

the first input signal is sent to the first inverter input to turn on an NMOS transistor of the first inverter and turn off a PMOS transistor of the first inverter.

5. The method of claim 2, wherein testing the dynamic random access memory after the storage capacitor of each memory cell has been charged for a predetermined period of time comprises:

after the storage capacitor of each storage unit is charged for a preset time, a second input signal is sent to the input end of the voltage switching circuit, so that the voltage switching circuit switches the voltage applied to the substrate from the second voltage to the first voltage;

and testing the dynamic random access memory.

6. The method of claim 1, wherein the plurality of storage units comprises target storage units;

testing the dynamic random access memory, including:

and performing a read operation on the target storage unit to test the dynamic random access memory.

7. A dynamic random access memory test device, wherein the dynamic random access memory comprises a substrate and a plurality of memory cells, each memory cell comprising a storage capacitor and a first transistor, the storage capacitor of each memory cell being electrically connected to the substrate through a corresponding first transistor, the device comprising:

a control module for charging storage capacitors of respective memory cells by switching a voltage applied to the substrate from a first voltage to a second voltage, the second voltage being higher than the first voltage;

And the test module is used for testing the dynamic random access memory after the storage capacitor of each storage unit is charged for a preset time.

8. The dynamic random access memory testing device is characterized by comprising a dynamic random access memory to be tested and a voltage switching circuit, wherein:

the dynamic random access memory to be tested comprises a substrate and a plurality of memory cells, wherein each memory cell comprises a memory capacitor and a first transistor, and the memory capacitor of each memory cell is electrically connected with the substrate through the corresponding first transistor;

the voltage switching circuit comprises an output end, and the output end of the voltage switching circuit is electrically connected with the substrate and is used for charging storage capacitors of all storage units by switching a voltage applied to the substrate from a first voltage to a second voltage, wherein the second voltage is higher than the first voltage.

9. The apparatus of claim 8, wherein the first transistor is an NMOS transistor and the storage capacitor comprises a first plate;

the storage capacitor of each storage unit is electrically connected with the substrate through a corresponding first transistor, and comprises:

the first polar plate of the storage capacitor of each storage unit is electrically connected with the drain electrode of the corresponding first transistor, and the P-type silicon substrate of the first transistor of each storage unit is electrically connected with the substrate.

10. The apparatus of claim 9, wherein the voltage switching circuit comprises a first inverter, an output of the first inverter being an output of the voltage switching circuit.

11. The apparatus of claim 10, wherein the first inverter is a CMOS transistor.

12. The apparatus of claim 11, wherein the drain of the NMOS transistor and the drain of the PMOS transistor of the first inverter are connected to the output terminal of the voltage switching circuit, the input voltage of the source of the NMOS transistor of the first inverter is the first voltage, and the input voltage of the source of the PMOS transistor of the first inverter is the second voltage;

the input end of the first inverter is used for receiving a first input signal so as to enable the NMOS transistor of the first inverter to be turned off and enable the PMOS transistor of the first inverter to be turned on.

13. The apparatus of claim 12, wherein the input of the first inverter is further configured to receive a second input signal to turn on the NMOS transistor of the first inverter and to turn off the PMOS transistor of the first inverter.

14. The apparatus of claim 11, wherein the drain of the NMOS transistor and the drain of the PMOS transistor of the first inverter are connected to the output terminal of the voltage switching circuit, the input voltage of the source of the PMOS transistor of the first inverter is the first voltage, and the input voltage of the source of the NMOS transistor of the first inverter is the second voltage;

The input end of the first inverter is used for receiving a first input signal so as to enable the NMOS transistor of the first inverter to be conducted and enable the PMOS transistor of the first inverter to be cut off.

15. The apparatus of claim 14, wherein the input of the first inverter is further configured to receive a second input signal to turn off an NMOS transistor of the first inverter and turn on a PMOS transistor of the first inverter.

16. The apparatus of claim 8, wherein an output of the voltage switching circuit is electrically connected to the substrate through a connection plug.