CN114783505A

CN114783505A - Memory test method and device and memory system

Info

Publication number: CN114783505A
Application number: CN202210473615.0A
Authority: CN
Inventors: 周坤; 刘欢欢
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-04-29
Filing date: 2022-04-29
Publication date: 2022-07-22

Abstract

The embodiment of the application discloses a method and a device for testing a memory and a memory system, wherein the method comprises the following steps: adjusting a column selection signal waveform to set a read timing margin test environment; performing a write operation and a read operation on a memory cell in the read timing margin test environment; the write operation includes writing test data into the memory cell; and comparing a reading result obtained by executing the reading operation with the test data, and determining whether the memory cell has a defect with insufficient reading timing sequence margin according to the comparison result. According to the method and the device, the test environment of the read timing sequence margin is set by adjusting the waveform of the column selection signal, so that the memory cell with the defect of potential insufficient read timing sequence margin is accurately detected in the test process, and the test coverage rate is improved.

Description

Memory test method and device and memory system

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a method and an apparatus for testing a memory, and a memory system.

Background

Dynamic Random Access Memory (DRAM) is an indispensable component of contemporary computer systems, and is composed of many Memory cells arranged in an array.

In a DRAM, the memory cells require a sufficient read timing margin to ensure that the stored data information can be correctly read.

Therefore, the method has great significance for performance evaluation of the DRAM by accurately detecting the memory cells with the defects with potential insufficient read timing margin in the test process.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a memory testing method, apparatus and memory system to solve at least one problem in the prior art.

In order to achieve the above purpose, the technical solution of the embodiment of the present application is implemented as follows:

in a first aspect, an embodiment of the present application provides a memory testing method, where the method includes:

adjusting a column selection signal waveform to set a read timing margin test environment;

performing a write operation and a read operation on a memory cell in the read timing margin test environment; the write operation includes writing test data into the memory cell;

and comparing a reading result obtained by executing the reading operation with the test data, and determining whether the memory cell has a defect with insufficient reading timing sequence margin according to the comparison result.

In an alternative embodiment, the column selection signal waveform includes a voltage rising period and a voltage sustaining period; the adjusting of the column selection signal waveform to set a read timing margin test environment includes:

adjusting the voltage rise period from a first duration to a second duration; the second duration is greater than the first duration.

reducing a substrate voltage of the memory to adjust the voltage rise period from a first duration to a third duration; the third duration is greater than the first duration.

In an alternative embodiment, the adjusting the column selection signal waveform to set the read timing margin test environment further includes:

reducing a substrate voltage of the memory to adjust the voltage rise period from a second duration to a fourth duration; the fourth duration is greater than the second duration.

In an alternative embodiment, the column selection signal waveform further includes a voltage falling period; the duration of the voltage rise period is greater than the duration of the voltage fall period.

In an alternative embodiment, the performing a write operation on the memory cell includes:

executing a first writing operation on the storage unit, and writing background data into the storage unit;

and executing second write-in operation on the storage unit according to a preset data structure, and writing the test data in the preset data structure into the storage unit.

In an alternative embodiment, the performing the second write operation to the memory cell includes:

adjusting the write recovery time corresponding to the second write operation from a fifth time length to a sixth time length to reduce the signal margin of the memory cell; the sixth duration is less than the fifth duration. In an optional implementation manner, the write recovery time corresponding to the second write operation is smaller than the write recovery time corresponding to the first write operation.

In an alternative embodiment, the background data is first data; the test data in the preset data structure comprises first data and second data, and the storage unit corresponding to the second data is a target storage unit.

In a second aspect, an embodiment of the present application provides a memory test apparatus, including:

the environment setting module is used for adjusting the waveform of the column selection signal so as to set a read timing margin test environment;

a data processing module for performing a write operation and a read operation on a memory cell in the read timing margin test environment; the write operation includes writing test data into the memory cell;

and the comparison module is used for comparing a read result obtained by executing the read operation with the test data and determining whether the memory cell has the defect of insufficient read timing sequence margin according to the comparison result.

In an alternative embodiment, the column selection signal waveform includes a voltage rising period and a voltage sustaining period; the environment setting module is specifically configured to adjust the voltage rise period from a first duration to a second duration; the second duration is greater than the first duration.

In an alternative embodiment, the column selection signal waveform includes a voltage rising period and a voltage sustaining period; the environment setting module is specifically configured to reduce a substrate voltage of the memory to adjust the voltage rise period from a first duration to a third duration; the third duration is greater than the first duration.

In an optional embodiment, the environment setting module is specifically configured to decrease a substrate voltage of the memory to adjust the voltage rise period from a second duration to a fourth duration; the fourth duration is greater than the second duration.

In an alternative embodiment, the column selection signal waveform further includes a voltage drop period; the duration of the voltage rise period is greater than the duration of the voltage fall period.

In an alternative embodiment, the data processing module comprises:

the first writing module is used for executing first writing operation on the storage unit and writing background data into the storage unit;

and the second writing module is used for executing second writing operation on the storage unit according to a preset data structure and writing the test data in the preset data structure into the storage unit.

In an optional implementation, the data processing module further includes:

a write recovery time adjustment module, configured to adjust the write recovery time corresponding to the second write operation from a fifth time period to a sixth time period to reduce a signal margin of the memory cell; the sixth duration is less than the fifth duration.

In an optional implementation manner, the write recovery time corresponding to the second write operation is smaller than the write recovery time corresponding to the first write operation.

In a third aspect, an embodiment of the present application provides a memory system, including: a controller and a plurality of memories coupled to the controller; wherein,

the controller configured to perform the memory test method of the first aspect.

In the technical solution provided by the present application, a method for testing a memory is provided, the method comprising: adjusting a column selection signal waveform to set a read timing margin test environment; performing a write operation and a read operation on a memory cell in the read timing margin test environment; the write operation includes writing test data into the memory cell; and comparing the read result obtained by executing the read operation with the test data, and determining whether the memory cell has a defect with insufficient read timing sequence margin according to the comparison result. According to the method and the device, the read timing margin test environment is set by adjusting the waveform of the column selection signal, and the read timing margin test is performed on the memory unit, so that the memory unit with the defect of insufficient potential read timing margin is easier to detect, and the accuracy of memory performance evaluation is improved.

Drawings

FIG. 1 is a schematic diagram illustrating a structure of a memory cell array in a memory according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram illustrating a structure of a memory cell in a memory cell array according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a circuit structure for a read operation according to an embodiment of the present disclosure;

FIG. 4 is a timing diagram illustrating a read operation according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a waveform of a column selection signal according to an embodiment of the present application;

FIG. 6 is a schematic flowchart illustrating an implementation of a memory testing method according to an embodiment of the present application;

FIGS. 7a-7c are diagrams illustrating the waveforms of column selection signals provided in three specific examples of the embodiment of the present application;

FIGS. 8a-8c illustrate three different default data structures provided by embodiments of the present application;

FIG. 9 is a flowchart illustrating testing a memory according to a specific example of the embodiment of the present application;

FIG. 10 is a schematic diagram illustrating an exemplary embodiment of a memory test apparatus;

fig. 11 is a schematic structural diagram of a memory system according to an embodiment of the present application.

Detailed Description

Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be appreciated that spatial relationship terms, such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially descriptive terms used herein are interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

The block diagrams shown in the figures are functional entities only and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in the form of software, or in one or more software-hardened modules, or in different networks and/or processor devices and/or microcontroller devices.

The Memory device according to the embodiment of the present application may include a Dynamic Random Access Memory (DRAM), and is particularly suitable for a double data rate synchronous dynamic random Access Memory (DDR sdram) adopting a DDR4 Memory specification and a DDR5 Memory specification, and a low power consumption DDR sdram adopting an LPDDR5 Memory specification. It should be noted that the embodiments of the present application are not limited to the DRAM, but in the following description, for clarity of description, only the DRAM is taken as an example for illustration.

Fig. 1 is a schematic structural diagram of a memory cell array in a memory according to an embodiment of the present disclosure. As shown in fig. 1, in a DRAM, an array of memory cells is typically arranged in rows and columns such that a particular memory cell can be addressed by designating the row and column of its array. The memory cell array includes a plurality of word lines ("WLs" shown in fig. 1), a plurality of bit line pairs ("BLBs" shown in fig. 1), a plurality of memory cells ("■" shown in fig. 1) located at intersections of the word lines and the bit lines, and a plurality of sense amplifiers ("SAs" shown in fig. 1) connected to the bit line pairs. Also shown in fig. 1 are a column select signal (CSL) that controls the activation of the bit lines, a write enable signal (WE) that controls the write driver, and a plurality of local input output line pairs (LIO/LIOB shown in fig. 1).

Fig. 2 is a schematic structural diagram of a memory cell in a memory cell array according to an embodiment of the present disclosure. As shown in fig. 2, each memory cell in a DRAM generally includes a Capacitor (SC) and A Transistor (AT), the gate of the Transistor AT is connected to a word line WL, the drain is connected to a bit line, and the source is connected to the Capacitor SC. The voltage signal on the word line WL can control the transistor AT to be turned on or off, and thus data information stored in the capacitor SC is read through the bit line BL or written into the capacitor SC through the bit line BL for storage.

The data reading process of the memory cell is described with reference to fig. 3 and fig. 4, in which fig. 3 is a schematic circuit structure diagram during a read operation, and fig. 4 is a timing chart of the read operation.

As shown in fig. 3, the sense amplifier 100 includes four transistors, which are a first transistor 101, a second transistor 102, a third transistor 103, and a fourth transistor 104, wherein the first transistor 101 and the third transistor 103 are both PMOS (Positive channel Metal Oxide Semiconductor) transistors, and the second transistor 102 and the fourth transistor 104 are both NMOS (Negative channel Metal Oxide Semiconductor) transistors. A gate of the first transistor 101 is connected to a reference bit line BLB, and a drain and a source of the first transistor 101 are respectively connected to a bit line BL and a P-type Sense Amplifier Control Signal (SAP); the gate of the third transistor 103 is connected to the bit line BL, and the drain and source of the third transistor 103 are connected to the reference bit lines BLB and SAP, respectively; a gate of the second transistor 102 is connected to a reference bit line BLB, and a drain and a source of the second transistor 102 are respectively connected to a bit line BL and an N-type Sense Amplifier Control Signal (SAN); the gate of the fourth transistor 104 is connected to the bit line BL, and the drain and source of the fourth transistor 104 are connected to the reference bit lines BLB and SAN, respectively.

The precharge section 120 includes a fifth transistor 105, a sixth transistor 106, and a seventh transistor 107. The drain and source of the fifth transistor 105 are connected to the Bit Line BL and the Bit Line precharge Voltage VBLP (Voltage of Bit Line precharge), the drain and source of the sixth transistor 106 are connected to the reference Bit Line BLB and the Bit Line precharge Voltage VBLP, the drain and source of the seventh transistor 107 are connected to the Bit Line BL and the reference Bit Line BLB, the gate of the fifth transistor 105, the gate of the sixth transistor 106, and the gate of the seventh transistor 107 are all connected to a precharge signal Line, and the precharge signal Line is connected to a Voltage Equalizer (VEQ), so that when the precharge signal Line is turned on, the Bit Line BL and the reference Bit Line BLB are charged to the Bit Line precharge Voltage VBLP.

The voltage applied to one plate of capacitor SC in memory cell 110 is always the power supply voltage V_CCIs half of V_CCAnd/2, when the data information stored in the capacitor SC is '1', the voltage on the other plate is V_CCAt this time, the charge amount stored by the capacitor SC is + Vcc/2C, wherein C is the capacitance of the capacitor SC; when the capacitor SC stores data information of "0", the voltage on the other substrate is 0, and the amount of charge stored by the capacitor SC at this time is-Vcc/2C. The following description will be given taking as an example a write operation and a read operation of one memory cell 110 for executing data information "1".

Fig. 4 is a timing chart of a read operation, in which the horizontal axis represents time and the vertical axis represents signal level. As shown in fig. 4, one Read operation (Read) includes four phases: a Precharge (Precharge) phase Q1, a Charge Sharing (Charge Sharing) phase Q2, a Sensing (Sensing) phase Q3, and a Restore (Restore) phase Q4.

In the precharge phase Q1, referring to fig. 3 and 4, after the precharge command (PRE), the WL is turned off, the sense amplifier is turned off after a certain time, and the fifth transistor 105, the sixth transistor 106 and the seventh transistor 107 are turned on by controlling the precharge signal, so as to stabilize the voltages on the bit line BL and the reference bit line BLB at Vref, where Vref is V_CC/2＝VBLP。

After the precharge phase Q1, the voltages of BL and BLB have stabilized AT Vref, and in the obtaining phase Q2, the precharge signal line is turned off, the WL is turned on by controlling the WL signal after the Active Command (ACT) and a fixed time T1 delay, the transistor AT in the memory cell 110 is turned on, the positive charges stored in the capacitor flow to BL, and the voltage of BL is pulled up to Vref +, and then the sensing phase Q3 is entered.

Since the voltage of BL is pulled up to Vref + during the acquisition phase Q2, the fourth transistor 104 is more conductive than the second transistor 102, and the first transistor 101 is more conductive than the third transistor 103. In the sensing phase Q3, the voltage at SAN is set to logic 0 and the voltage at SAP is set to logic 1, i.e. high V_CC. Since the fourth transistor 104 is more conductive than the second transistor 102, the voltage on BLB is pulled to a logic 0 voltage Gnd (representing ground voltage, also referred to as Vss) faster by SAN, and the voltage on BLB is also pulled to a logic 0 voltage Gnd (representing Vss)The voltage on BL will also be pulled to the logic 1 voltage more quickly by SAP. Then, the first transistor 101 and the fourth transistor 104 are turned on, and the third transistor 103 and the second transistor 102 are turned off. Finally, the voltages of both BL and BLB enter a steady state, correctly presenting the information stored by the capacitors.

After the operation of the sensing phase Q3 is completed, in the recovery phase Q4, BL is at a stable logic 1 voltage V_CCAt this time, BL charges the capacitor. After a certain period of time, the charge of the capacitor can be restored to the state before the read operation. When the read command RD is executed, the column selection transistor 141 is turned on by controlling the column selection signal CSL, and the information stored in the capacitor SC is output from the sense amplifier to the local input/output line LIO, so that the external device can read specific information.

Part of the process of the Write operation (Write) is the same as the read operation, including a Write recovery (Write recovery) phase Q5, in addition to the precharge phase Q1, the charge sharing phase Q2, the sensing phase Q3, and the recovery phase Q4. In the write recovery phase Q5, a write enable transistor (not shown) is turned on by controlling a write enable signal WE. At this time, BL is pulled to a logic 1 level, and BLB is pulled to a logic 0 level. After a certain time, when the capacitor SC is charged to a state of 1, the transistor AT connected to the capacitor SC is turned off by controlling WL, and the operation of writing 1 is completed.

In a read operation, the column selection signal CSL has a waveform as shown in FIG. 5, and the CSL waveform includes three portions: a voltage rising period, a voltage maintaining period and a voltage falling period, the corresponding time lengths are respectively T₁、T₂And T₃. After the voltage rising period, the column selection transistor is turned on, and the data information amplified by the sense amplifier is outputted to the local input/output line LIO. Taking the reading of data 1 as an example, the output process of the data information is actually a process in which the voltage on the local input/output line LIO is gradually pulled up to the logic 1 voltage, and if the voltage maintaining period of the CSL is insufficient, i.e. the read timing margin of the memory cell is insufficient, which may cause the voltage not to reach the logic 1 voltage, the CSL has entered the voltage dropping periodThe column select transistor is then turned off, causing a data read error.

In the production stage of the memory, due to the influence of process deviation, environment, equipment and other factors, some memory cells have defects with potential insufficient read timing margin, and the CSL waveform of the defective memory cell is deformed. During a test phase of the memory, a memory cell with a defect with insufficient read timing margin may be difficult to detect because the CSL waveform is not deformed enough to cause data read errors. However, after the memory is repeatedly read and written, the CSL waveforms of all the memory cells are degraded to some extent, and at this time, the memory cells with the defect of insufficient read timing margin are exposed first, which results in the shortened life of the memory. In addition, when the application scenario of the memory changes and the operation speed of the memory needs to be increased, the timing parameters of the memory are reduced, the voltage sustaining period of the CSL of all the memory cells is compressed, and in this case, the probability of failure of the memory cell with a defect with insufficient potential read timing margin is higher than that of a normal memory cell.

Therefore, how to detect the memory cells with the potential defect of insufficient read timing margin in time in the test stage becomes an urgent problem to be solved, and has important significance for performance evaluation of the DRAM.

In view of this, the present application proposes the following embodiments.

The embodiment of the application provides a memory test method. Fig. 6 is a schematic implementation flowchart of a memory testing method according to an embodiment of the present disclosure. As shown in fig. 6, the memory test method includes the steps of:

step 601: adjusting a column selection signal waveform to set a read timing margin test environment;

in some embodiments, the column selection signal waveform includes a voltage rising period and a voltage sustaining period; adjusting a column selection signal waveform to set a read timing margin test environment, comprising: adjusting the voltage rise period from a first duration to a second duration; the second duration is greater than the first duration.

In the embodiment of the present application, the adjustment of the CSL waveform may be achieved by providing a soft-start circuit in the column selection signal generation circuit, and the soft-start circuit may reduce the rate of voltage rise, thereby extending the voltage rise period. Here, the soft start circuit may be a resistance-capacitance circuit composed of a resistance element and a capacitance element, or a segmented control circuit composed of a voltage comparator, a resistance element and a capacitance element, or a digital control circuit composed of a digital-to-analog converter, or any other circuit capable of reducing a voltage rise rate.

In some embodiments, providing a soft-start circuit in the column selection signal generation circuit may extend the voltage rise period by 65-100 ps. In a specific example, after the soft start circuit is provided in the column selection signal generation circuit so that the voltage rising period is extended by 85ps, the CSL waveform is shown in fig. 7a, and the slope of the voltage rising period is reduced as compared with the CSL waveform in fig. 5, and the voltage rising period is T₁(first period of time) to T_1a(second duration), the voltage rising period is extended by 85ps, and the voltage maintaining period is prolonged by T₂Is reduced to T_2aThe voltage sustaining period is reduced by 85 ps. Therefore, after the voltage rising period is prolonged by arranging the soft start circuit in the column selection signal generating circuit, the voltage maintaining period is correspondingly reduced, so that the situation that the CSL waveform is degraded in the actual use process of the memory or the voltage maintaining period is compressed due to the improvement of the operation speed of the memory can be simulated, and the memory cell with the defect of insufficient potential reading timing sequence margin is easier to detect.

In some embodiments, adjusting the column select signal waveform to set the read timing margin test environment includes: reducing a substrate voltage of the memory to adjust the voltage rise period from a first duration to a third duration; the third duration is greater than the first duration.

In the embodiment of the application, the substrate voltage of the memory can be reduced to achieve the purpose of adjusting the voltage rising period, and the threshold voltage of the column selection transistor can be increased by reducing the substrate voltage of the memory, so that the column selection transistor needs longer time to be turned on.

In some embodiments, the substrate voltage of the memory can be lowered by 180 mV 220mV for the purpose of adjusting the voltage rise period. In a specific example, after the substrate voltage of the memory is reduced by 200mV, the CSL waveform is shown in FIG. 7b, and the slope of the voltage rise period is reduced compared to the CSL waveform in FIG. 5, where the voltage rise period is represented by T₁(first duration) is adjusted to T_1b(third period of time), the voltage maintaining period is represented by T₂Is reduced to T_2b. Therefore, the slope of the voltage rising period can be reduced by reducing the substrate voltage of the memory, the voltage maintaining period is compressed, and the situation that the CSL waveform is degraded in the actual use process of the memory or the voltage maintaining period is compressed due to the improvement of the operation speed of the memory can be simulated, so that the memory cell with the defect of insufficient potential read timing margin can be detected more easily.

In some embodiments, adjusting column select signal waveforms to set a read timing margin test environment includes: adjusting the voltage rise period from a first duration to a second duration; the second duration is greater than the first duration; reducing a substrate voltage of the memory to adjust the voltage rise period from a second duration to a fourth duration; the fourth duration is greater than the second duration.

In an embodiment of the present application, after the voltage rising period is adjusted from the first duration to the second duration by setting the soft start circuit in the column selection signal generating circuit, the voltage rising period is adjusted from the second duration to the fourth duration by reducing the substrate voltage of the memory, so as to set a read timing margin test environment. In another embodiment of the present application, after the voltage rising period is adjusted from the first duration to the second duration by reducing the substrate voltage of the memory, the voltage rising period is adjusted from the second duration to the fourth duration by providing the soft start circuit in the column selection signal generating circuit, so as to set the read timing margin test environment. In other words, in the embodiment of the present application, the read timing margin test environment may be set by providing the soft start circuit in the column selection signal generation circuit in combination with the substrate voltage of the memory, so as to further improve the detection rate of the memory cell having the defect with the potential insufficient read timing margin.

In some embodiments, the read timing margin test environment can be set by providing a soft start circuit in the column selection signal generation circuit to extend the voltage rise period by 65-100ps and then lowering the substrate voltage of the memory by 180-220 mV. In a specific example, after the soft start circuit is set to extend the voltage rising period by 85ps and the substrate voltage of the memory is lowered by 200mV, the CSL waveform is shown in FIG. 7c, and the slope of the voltage rising period is reduced compared to the CSL waveform in FIG. 5, and the voltage rising period is T₁(first duration) is adjusted to T_1C(fourth period of time), the voltage sustaining period is represented by T₂Is reduced to T_2C. Therefore, by simultaneously setting the soft start circuit and reducing the substrate voltage of the memory, the voltage maintaining period can be further compressed, so that the situation that the CSL waveform of the simulated memory is degraded in the actual use process or the voltage maintaining period is compressed due to the increase of the operating speed of the memory is simulated, and the memory cell with the defect of insufficient potential reading timing sequence margin is easier to detect.

In some embodiments, the column selection signal waveform further includes a voltage drop period; the duration of the voltage rise period is greater than the duration of the voltage fall period.

In the embodiment of the application, when the CSL waveform is adjusted to set the read timing margin test environment, the total duration of the voltage rise period, the voltage maintenance period and the voltage fall period is not changed, and the duration of the voltage fall period is not changed, so that the voltage rise period can be adjusted to reduce the voltage maintenance period, degradation of the CSL waveform occurs in the actual use process of the analog memory, or the voltage maintenance period is compressed due to the improvement of the operation speed of the memory, so that a memory cell with a potential defect of insufficient read timing margin can be detected more easily, and the test time cannot be increased.

Step 602: performing a write operation and a read operation on a memory cell in the read timing margin test environment; the write operation includes writing test data into the memory cell;

in some embodiments, performing a write operation on a memory cell includes: executing a first writing operation on the storage unit, and writing background data into the storage unit; and executing second write-in operation on the storage unit according to a preset data structure, and writing the test data in the preset data structure into the storage unit.

In some embodiments, the performing a second write operation to the memory cell includes: adjusting the write recovery time corresponding to the second write operation from a fifth time length to a sixth time length to reduce the signal margin of the memory cell; the sixth duration is less than the fifth duration. In some embodiments, a write recovery time corresponding to the second write operation is less than a write recovery time corresponding to the first write operation.

Here, the Write Recovery Time (tWR) is a Time period between generation of the Write enable signal WE and generation of the precharge command PRE. If the write recovery time is too short, it may cause the previous write operation to be incomplete and the next precharge operation to begin, i.e., the voltage on capacitor SC has not reached + V_CCThe WL is turned off. Since factors affecting the read result include a Signal Margin (SM) of the memory cell in addition to the read timing Margin of the memory cell, when the Signal Margin of the memory cell is sufficiently large, it is difficult to expose a defect with an insufficient read timing Margin, and therefore, in the embodiment of the present application, the Signal Margin of the memory cell can be reduced by reducing the write recovery time of the second write operation, i.e., the write recovery time of the test data write.

In a specific example, the write recovery time (the sixth duration) of the second write operation may be the shortest write recovery time for the memory cell to correctly write data, so that the defective cell caused by insufficient read timing margin and/or insufficient signal margin can be detected, thereby greatly improving the test coverage.

In some embodiments, the background data is first data; the test data in the preset data structure comprises first data and second data, and the storage unit corresponding to the second data is a target storage unit.

Here, when the first data is 0, the second data is 1, and the memory cell corresponding to 1 is a target memory cell; when the first data is 1, the second data is 0, and the memory cell corresponding to 0 is a target memory cell.

In the embodiment of the present application, when the first data is 1 and the second data is 0, the preset data structure may be a checkerboard pattern (two preset data structures shown in fig. 8 a) with 1 and 0 alternately arranged, a stripe pattern (two preset data structures shown in fig. 8 b) with 1 and 0 alternately arranged in rows, a pattern (eight preset data structures shown in fig. 8 c) with 0 data on one BL, or other patterns with 0 and 1 randomly arranged. In the preset data structure, the storage units of the storage 1 exist around the target storage unit of the storage 0, so that the electric leakage of the target storage unit can be aggravated, and the signal margin of the storage unit is properly reduced, so that the defective units caused by insufficient read timing sequence margin and/or insufficient signal margin can be detected, and the test coverage rate is greatly improved. Taking the preset data structure shown in fig. 8c as an example for explanation, it is possible to provide 8 different preset data structures shown in fig. 8c, where each preset data structure includes test data corresponding to 8 word lines, and by combining with a writing manner of spacing 8 word lines, the test coverage can be improved to the maximum extent.

In some embodiments, the second write operation and the read operation are in units of Burst Length (Burst Length). In a specific example, the second write operation may be an X-FAST write operation, where the X-FAST write operation is an X-direction (row direction) write operation manner, before each write operation is performed, all word lines on the same bit line are sequentially turned on, one word line is turned on and after data of a burst length is sequentially written on the word line, the word line is turned off, and then the next word line is turned on, that is, data of a burst length is sequentially written on each word line for all word lines connected to the same bit line. The read operation may be an X-FAST read operation, which is a read operation in the X direction (row direction), and before each read operation is performed, all word lines on the same bit line are sequentially turned on, one word line is turned on, and after the burst length of data on the word line is sequentially read, the word line is turned off, and then the next word line is turned on, that is, the data in the memory cells on each word line are sequentially read for all word lines connected to the same bit line.

In another specific example, the second write operation may be a Y-FAST write operation, which is a write operation in the Y direction (column direction), and one word line is turned on before each write operation is performed, and turned off after data of one burst length is sequentially written; then, the word line is turned on again, and data of one burst length is sequentially written. The same word line is repeatedly opened and closed until all the corresponding memory cells on the word line are written in sequence by taking the burst length as a unit, and then the next word line is opened to execute the same operation. The read operation can be a Y-FAST read operation, which is a read operation mode in the Y direction (column direction), and before each read operation, a word line is opened, and after a burst length of data is read in sequence, the word line is closed; then, the word line is turned on again, and the data of one burst length is read out sequentially. The same word line is repeatedly opened and closed until all the corresponding memory cells on the word line are read out in sequence by taking the burst length as a unit, and then the next word line is opened to execute the same operation.

Here, the burst length refers to the number of memory cells involved in continuously reading and writing data from and to adjacent memory cells in the same word line. For example, DDR4 supports a burst length of 8 or 4 (i.e., BL8 or BL4), and when DDR4 is 16 bits wide, 8 × 16bit data or 4 × 16bit data can be read/written at a time; the burst length supported by LPDDR4 is 32 or 16 (i.e., BL32 or BL16), and when the bit width of LPDDR4 is 16 bits, 32 × 16 bits of data or 16 × 16 bits of data can be read/written at a time.

Step 603: and comparing the read result obtained by executing the read operation with the test data, and determining whether the memory cell has a defect with insufficient read timing sequence margin according to the comparison result.

In the embodiment of the application, when a reading result obtained by performing reading operation on a memory cell is inconsistent with test data, determining that the memory cell has a defect of insufficient reading timing sequence margin; and when the read result obtained by performing the read operation on the memory cell is consistent with the test data, determining that the memory cell has no defect with insufficient read timing margin.

In order to further apply the above-mentioned memory test method to an actual memory read timing margin test, a specific example is provided in the present application.

Fig. 9 is a flowchart of testing a memory according to a specific example of the embodiment of the present application, and as shown in fig. 9, the testing process includes the following steps:

step 901: setting a read timing margin test environment;

in the embodiment of the application, the read timing margin test environment is set by adjusting the CSL waveform. The method for adjusting the CSL waveform may be to provide a soft start circuit in the column selection signal generation circuit to extend the voltage rising period of the CSL waveform, where the voltage rising period can be extended by 65-100ps by providing the soft start circuit, and the CSL waveform after the voltage rising period is extended by 85ps is shown in fig. 7 a; the method for adjusting the CSL waveform may further be to decrease the substrate voltage of the memory to extend the voltage rising period of the CSL waveform, where the substrate voltage of the memory may be decreased by 180 mV and 220mV, and the CSL waveform after the substrate voltage is decreased by 200mV is shown in FIG. 7 b; the method for adjusting the CSL waveform may also be to set the soft start circuit and lower the substrate voltage of the memory at the same time, and the adjusted CSL waveform is shown in fig. 7 c. In this way, by arranging the soft start circuit in the column selection signal generating circuit and/or reducing the substrate voltage of the memory to adjust the voltage rising period of the CSL waveform, the voltage maintaining period of the CSL waveform can be reduced, so that the situation that the CSL waveform is degraded in the actual use process of the simulated memory or the voltage maintaining period is compressed due to the improvement of the operating speed of the memory is simulated, and the memory cell with the defect of potential insufficient reading timing sequence margin is easier to detect.

In the embodiment of the application, when the CSL waveform is adjusted to set a read timing margin test environment, the total duration of the voltage rise period, the voltage maintenance period and the voltage fall period is unchanged, and the duration of the voltage fall period is unchanged, so that the voltage maintenance period can be reduced by adjusting the voltage rise period without increasing the test time, and the CSL waveform is simulated to be degraded in the actual use process of the memory, or the voltage maintenance period is compressed due to the improvement of the operation speed of the memory, so that a memory cell with a potential defect of insufficient read timing margin can be detected more easily.

Step 902: executing a first writing operation, and writing background data;

in the embodiment of the present application, the background data is written in all the memory cells by performing the first write operation on the memory cells.

Step 903: performing an auto-refresh operation;

in the embodiment of the present application, in order to maintain the background data of the memory cells, after the first write operation is performed, an auto-refresh operation is performed on all the memory cells.

Step 904: executing a second writing operation, and writing test data according to a preset data structure;

in an embodiment of the present application, a plurality of different preset data structures are provided; and for each preset data structure in the plurality of different preset data structures, sequentially writing the test data into the storage unit through a second writing operation. The first preset data structure is adopted during the first circulation, the second preset data structure is adopted during the second circulation, and the like, until all the preset data structures are traversed, the traversal of all the storage units can be realized through a plurality of different preset data structures.

In the embodiment of the present application, a second write operation is performed on the storage unit according to the preset data structure, and the test data in the preset data structure is written into the target storage unit.

Here, when the background data is 1, the memory cell corresponding to 0 in the preset data structure is a target memory cell.

In the embodiment of the application, the signal margin of the memory cell is reduced by reducing the write recovery time corresponding to the second write operation, and the write recovery time of the second write operation is smaller than that of the first write operation.

Here, the write recovery time of the second write operation may be reduced to the shortest write recovery time for the memory cell to correctly write data, so that defective cells due to insufficient read timing margin and/or insufficient signal margin can be detected, greatly improving test coverage. The second write operation is an X-FAST write operation or a Y-FAST write operation, with a burst length of 8 bits, 16 bits, or 32 bits.

Step 905: executing a read operation;

here, the read operation is an X-FAST read operation or a Y-FAST read operation.

Step 906: comparing the read result with the test data;

in the embodiment of the application, the comparison of the read result and the test data can determine whether the memory cell has a defect with insufficient read timing margin. Returning to execute the step 902, and writing the background data into all the storage units again; and switching to a next preset data structure to execute step 904, writing the test data in the next preset data structure into the memory cell by a second write operation; and if the preset data structure at the moment is the last preset data structure, exiting the test. Here, it is possible to complete a read timing margin test once for all memory cells in the memory as target memory cells by using a plurality of preset data structures. For example, when the preset data structure in the first loop is the first preset data structure shown in fig. 8a, the preset data structure is changed to the second preset data structure shown in fig. 8a at the second loop; when the preset data structure in the first loop is the first preset data structure shown in fig. 8b, changing the preset data structure to the second preset data structure shown in fig. 8b at the second loop; when the preset data structure in the first loop is the first preset data structure shown in fig. 8c, the preset data structure is changed to the second preset data structure shown in fig. 8c in the second loop, and so on, until all the preset data structures shown in fig. 8c are traversed. Therefore, all the storage units in the memory can be used as target storage units to finish one-time reading timing sequence margin test, and the traversal of the storage units can be realized.

Step 907: and outputting a test result.

In the embodiment of the application, after all the preset data structures are traversed, the test result is output. Here, when the read result is inconsistent with the test data, the memory cell has a defect of insufficient potential read timing margin, and the test result is a failure; when the reading result is consistent with the test data, the memory unit has no defect of insufficient potential reading timing sequence margin, and the test result is passed.

It should be noted that the above description of the test flow of the memory is similar to the above description of the embodiment of the memory test method, and has similar beneficial effects to the embodiment of the memory test method, and therefore, the description is omitted. For technical details not disclosed in the testing process of the memory in the embodiment of the present application, please refer to the description about the memory testing method in the embodiment of the present application for understanding.

Based on the same technical concept of the foregoing memory test method, an embodiment of the present application provides a memory test apparatus, and fig. 10 is a schematic structural diagram of the memory test apparatus provided in the embodiment of the present application, as shown in fig. 10, the memory test apparatus 1000 includes:

an environment setting module 1001 for adjusting a column selection signal waveform to set a read timing margin test environment;

a data processing module 1002, configured to perform a write operation and a read operation on a memory cell in the read timing margin test environment; the write operation includes writing test data into the memory cell;

a comparing module 1003, configured to compare a read result obtained by performing the read operation with the test data, and determine whether the memory cell has a defect with an insufficient read timing margin according to the comparison result.

In an alternative embodiment, the column selection signal waveform includes a voltage rising period and a voltage sustaining period; the environment setting module 1001 is specifically configured to adjust the voltage rising period from a first duration to a second duration; the second duration is greater than the first duration.

In an alternative embodiment, the environment setting module 1001 may include a soft start circuit (not shown) for adjusting the voltage rise period from a first duration to a second duration.

In an alternative embodiment, the column selection signal waveform includes a voltage rising period and a voltage sustaining period; the environment setting module 1001 is specifically configured to decrease a substrate voltage of the memory to adjust the voltage rise period from a first duration to a third duration; the third duration is greater than the first duration.

In an alternative embodiment, the environment setting module 1001 is specifically configured to decrease the substrate voltage of the memory to adjust the voltage rise period from the second duration to a fourth duration; the fourth duration is greater than the second duration.

In an alternative embodiment, the data processing module 1002 includes:

a first writing module (not shown in the figure) for performing a first writing operation on the storage unit and writing the background data into the storage unit;

and a second writing module (not shown in the figure) configured to perform a second writing operation on the storage unit according to a preset data structure, and write the test data in the preset data structure into the storage unit.

In an optional implementation, the data processing module 1002 further includes:

a write recovery time adjustment module (not shown in the figure) configured to adjust a write recovery time corresponding to the second write operation from a fifth time period to a sixth time period to reduce a signal margin of the memory cell; the sixth duration is less than the fifth duration.

In an alternative embodiment, the background data is first data; the test data in the preset data structure comprises first data and second data, and a storage unit corresponding to the second data is a target storage unit.

As shown in fig. 11, the memory system provided in the embodiment of the present application includes a controller 1101 and a plurality of memories 1102 coupled to the controller; wherein,

a controller 1101 configured to execute the aforementioned memory test method.

In some embodiments, the storage device is a dynamic random access memory.

In some embodiments, the dram memory conforms to the DDR2 memory specification.

In some embodiments, the dram memory conforms to the DDR3 memory specification.

In some embodiments, the dram memory conforms to the DDR4 memory specification.

In some embodiments, the dram memory conforms to the DDR5 memory specification.

In some embodiments, the memory of the DRAM conforms to the LPDDR4 memory specification.

In some embodiments, the memory of the DRAM complies with the LPDDR5 memory specification.

The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.

The features disclosed in the several apparatus embodiments provided in the present application may be combined in any combination to arrive at new apparatus embodiments without conflict.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for testing a memory, the method comprising:

and comparing the read result obtained by executing the read operation with the test data, and determining whether the memory cell has a defect with insufficient read timing sequence margin according to the comparison result.

2. The memory test method according to claim 1, wherein the column selection signal waveform includes a voltage rise period and a voltage sustain period; the adjusting of the column selection signal waveform to set a read timing margin test environment includes:

3. The memory test method according to claim 1, wherein the column selection signal waveform includes a voltage rise period and a voltage sustain period; the adjusting of the column selection signal waveform to set a read timing margin test environment includes:

4. The method of claim 2, wherein the adjusting the column selection signal waveform to set a read timing margin test environment further comprises:

5. The memory test method of any of claims 2-4, wherein the column selection signal waveform further comprises a voltage drop period; the duration of the voltage rise period is greater than the duration of the voltage fall period.

6. The method of claim 1, wherein the performing a write operation on the memory cell comprises:

7. The memory test method of claim 6, wherein the performing a second write operation to the memory cell comprises:

adjusting the write recovery time corresponding to the second write operation from a fifth time length to a sixth time length to reduce the signal margin of the memory cell; the sixth duration is less than the fifth duration.

8. The method according to claim 6, wherein a write recovery time corresponding to the second write operation is shorter than a write recovery time corresponding to the first write operation.

9. The memory test method of claim 6, wherein the background data is first data; the test data in the preset data structure comprises first data and second data, and the storage unit corresponding to the second data is a target storage unit.

10. A memory test apparatus, the apparatus comprising:

the data processing module is used for executing write operation and read operation on the storage unit under the read timing margin test environment; the write operation includes writing test data into the memory cell;

11. The memory test device according to claim 10, wherein the column selection signal waveform includes a voltage rise period and a voltage sustain period; the environment setting module is specifically configured to adjust the voltage rise period from a first duration to a second duration; the second duration is greater than the first duration.

12. The memory test apparatus of claim 10, wherein the column selection signal waveform includes a voltage rise period and a voltage sustain period; the environment setting module is specifically configured to decrease a substrate voltage of the memory to adjust the voltage rise period from a first duration to a third duration; the third duration is greater than the first duration.

13. The memory test device of claim 11, wherein the environment setting module is specifically configured to decrease a substrate voltage of the memory to adjust the voltage rise period from a second duration to a fourth duration; the fourth duration is greater than the second duration.

14. The memory test device of any of claims 11-13, wherein the column selection signal waveform further comprises a voltage drop period; the duration of the voltage rise period is greater than the duration of the voltage fall period.

15. The memory test device of claim 10, wherein the data processing module comprises:

16. The memory test device of claim 15, wherein the data processing module further comprises:

a write recovery time adjustment module, configured to adjust a write recovery time corresponding to the second write operation from a fifth time duration to a sixth time duration to reduce a signal margin of the memory cell; the sixth duration is less than the fifth duration.

17. The apparatus according to claim 15, wherein a write recovery time corresponding to the second write operation is shorter than a write recovery time corresponding to the first write operation.

18. The memory test apparatus of claim 15, wherein the background data is first data; the test data in the preset data structure comprises first data and second data, and the storage unit corresponding to the second data is a target storage unit.

19. A memory system comprising a controller and a plurality of memories coupled to the controller; wherein

The controller configured to perform the method of any of claims 1-9.