CN115620795A

CN115620795A - Memory fault testing method, device, equipment and storage medium

Info

Publication number: CN115620795A
Application number: CN202110800102.1A
Authority: CN
Inventors: 邹武
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-07-13
Filing date: 2021-07-13
Publication date: 2023-01-17

Abstract

The disclosure provides a memory fault testing method, device, equipment and storage medium, and relates to the technical field of semiconductors. The method comprises the following steps: performing a first round of testing on a memory to be tested including a plurality of different types of first failure tests performed in sequence, the performing the first failure tests including: performing writing operation and reading operation of preset test data on a storage unit in a memory to obtain read data; obtaining a first fault test result according to the preset test data and the read data; and under the condition that the memory passes the first round of test according to the first fault test result, performing a second round of test including a second fault test on the memory, wherein the second fault test is at least one of a plurality of different types of first fault tests, and the preset test data written in the second fault test is different from the preset test data written in the first fault test in the corresponding first round of test. The method improves the efficiency of the memory fault test.

Description

Memory fault testing method, device, equipment and storage medium

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a method, an apparatus, a device, and a readable storage medium for testing a memory failure.

Background

The most fundamental links in the fabrication of memory chip products include design, tape-out, packaging, and testing, where testing is an important link for detecting memory failures. Most memory failures are caused by the phenomenon that the internal memory cell arrays of the memory are dense, parasitic coupling possibly exists among the memory cell arrays, and the like. The memory failure can be reflected as read-write abnormality of the memory cell array, and therefore, the failure test can be performed by reading after writing test data. Different test algorithms exist according to different fault models, and the modes of writing data and reading data are different in different test algorithms. Some test algorithms also need to be run multiple times, with some types of failures being detected by writing different data at each test, and running these tests multiple times takes a lot of time.

As described above, how to improve the efficiency of the memory failure test while ensuring the test effect is an urgent problem to be solved.

The above information disclosed in this background section is only for enhancement of understanding of the background of the disclosure and therefore it may contain information that does not constitute prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

The invention aims to provide a memory fault testing method, a device, equipment and a readable storage medium, which improve the efficiency of memory fault testing at least to a certain extent.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.

According to an aspect of the present disclosure, there is provided a memory failure test method, including: performing a first round of testing on a memory to be tested, the first round of testing including a plurality of different types of first failure tests performed in sequence, wherein performing the first failure tests includes: writing preset test data into the storage unit in the memory; reading a storage unit in the memory to obtain read data; obtaining a first fault test result according to the preset test data and the read data; determining whether the memory passes the first round of testing according to the first fault test result; and if the memory passes the first round of test, performing a second round of test on the memory, wherein the second round of test comprises a second fault test, the second fault test is at least one of the first fault tests with different types, and the preset test data written in the second fault test is different from the preset test data written in the corresponding first fault test in the first round of test.

According to an embodiment of the present disclosure, the second round of test includes performing a plurality of third failure tests, where the third failure test is one of the second failure tests, and the plurality of preset test data respectively written in the plurality of third failure tests include different test data.

According to an embodiment of the present disclosure, the second failure test is at least two of the plurality of different types of first failure tests; the second round of test also comprises a plurality of fourth fault tests, wherein the fourth fault test is one of the second fault tests different from the third fault test, and a plurality of preset test data respectively written in the fourth fault tests comprise different test data.

According to an embodiment of the present disclosure, a plurality of predetermined test data are written in a second predetermined mode in the plurality of fourth failure tests, respectively.

According to an embodiment of the present disclosure, the performing a second round of testing on the memory includes: and sequentially performing a plurality of times of third fault tests and a plurality of times of fourth fault tests on the memory according to a preset first priority, wherein a plurality of preset test data are respectively written in a first preset mode in the plurality of times of third fault tests, and a plurality of preset test data are respectively written in a second preset mode in the plurality of times of fourth fault tests.

According to an embodiment of the present disclosure, a plurality of predetermined test data are respectively written in a first predetermined mode in a plurality of third failure tests.

According to an embodiment of the present disclosure, the second round of test includes a plurality of second failure tests of different types that are performed in sequence, and the preset test data written in at least one of the second failure tests is different from the preset test data written in the corresponding first failure test.

According to an embodiment of the present disclosure, the plurality of second failure tests correspond to the plurality of first failure tests one to one.

According to an embodiment of the present disclosure, the memory includes a plurality of memory cells; the operation of writing preset test data into the memory cells in the memory comprises: writing preset test data into each storage unit; the reading operation of the memory unit in the memory, and obtaining read data includes: reading each storage unit to obtain read data of each storage unit; the obtaining a first fault test result according to the preset test data and the read data comprises: comparing whether the read data and the written preset test data of the same storage unit are the same or not; and if the read data of each storage unit in the memory is the same as the written preset test data, obtaining that the first fault test result is a pass.

According to an embodiment of the present disclosure, the obtaining a first failure test result according to the preset test data and the read data further includes: and if the read data and the written preset test data of at least one storage unit in the memory are different, the first fault test result is obtained as failure.

According to an embodiment of the present disclosure, the memory includes a plurality of memory cells; the operation of writing preset test data into the memory unit in the memory comprises the following steps: and writing the same preset test data into the plurality of memory units in the memory.

According to an embodiment of the present disclosure, the performing of the first round of testing on the memory includes: and sequentially carrying out the plurality of different types of first fault tests on the memory according to a preset second priority.

According to still another aspect of the present disclosure, there is provided a memory failure test apparatus including: the test module is used for carrying out a first round of test on a memory to be tested, the first round of test comprises a plurality of first fault tests of different types which are sequentially carried out, and the first fault test comprises obtaining a first fault test result according to preset test data written into a storage unit in the memory and data read from the storage unit in the memory; determining whether the memory passes the first round of testing according to the first fault testing result; if the memory passes the first round of testing, performing a second round of testing on the memory, wherein the second round of testing comprises a second fault testing, the second fault testing is at least one of the first fault testing of the plurality of different types, and preset testing data written in the second fault testing is different from preset testing data written in the first fault testing in the corresponding first round of testing; the data writing module is used for writing preset test data into the storage unit in the memory when the first fault test is carried out; and the data reading module is used for reading the storage unit in the memory to obtain read data when the first fault test is carried out.

According to an embodiment of the present disclosure, the second failure test is at least two of the plurality of different types of first failure tests; the second round of test further includes performing a fourth failure test a plurality of times, where the fourth failure test is one of the second failure tests different from the third failure test, and a plurality of preset test data written in the fourth failure tests respectively include different test data.

According to an embodiment of the disclosure, the data writing module is further configured to write a plurality of preset test data in a second preset mode in the fourth failure test for a plurality of times, respectively.

According to an embodiment of the present disclosure, the test module is further configured to: and sequentially performing a plurality of times of third fault tests and a plurality of times of fourth fault tests on the memory according to a preset first priority, wherein a plurality of preset test data are respectively written in a first preset mode in the plurality of times of third fault tests, and a plurality of preset test data are respectively written in a second preset mode in the plurality of times of fourth fault tests.

According to an embodiment of the disclosure, the data writing module is further configured to write a plurality of preset test data in a first preset mode in the third failure test for a plurality of times, respectively.

According to an embodiment of the present disclosure, the plurality of second failure tests corresponds to the plurality of first failure tests one to one.

According to an embodiment of the present disclosure, the memory includes a plurality of memory cells; the data writing module is further configured to perform an operation of writing preset test data into each storage unit; the data reading module is further configured to perform a read operation on each storage unit to obtain read data of each storage unit; the test module is further configured to: comparing whether the read data and the written preset test data of the same storage unit are the same or not; and if the read data of each storage unit in the memory is the same as the written preset test data, obtaining that the first fault test result is a pass.

According to an embodiment of the present disclosure, the test module is further configured to: and if the read data and the written preset test data of at least one storage unit in the memory are different, the first fault test result is obtained as failure.

According to an embodiment of the present disclosure, the memory includes a plurality of memory cells; the data writing module is further configured to perform an operation of writing the same preset test data into the plurality of storage units in the memory.

According to an embodiment of the disclosure, the test module is further configured to sequentially perform the plurality of different types of first failure tests on the memory according to a preset second priority.

According to still another aspect of the present disclosure, there is provided a test apparatus including: a memory, a processor and executable instructions stored in the memory and executable in the processor, the processor implementing any of the methods described above when executing the executable instructions.

According to yet another aspect of the present disclosure, there is provided a computer-readable storage medium having stored thereon computer-executable instructions that, when executed by a processor, implement any of the methods described above.

The memory fault testing method provided by the embodiment of the disclosure includes the steps of firstly carrying out a first round of test including a plurality of first fault tests of different types which are sequentially carried out on a memory to be tested, and then carrying out a second round of test including a second fault test on the memory under the condition that the memory passes the first round of test according to a first fault test result, wherein the step of carrying out the first fault test includes: the method comprises the steps of writing preset test data into a storage unit in a memory, reading the storage unit in the memory to obtain read data, and obtaining a first fault test result according to the preset test data and the read data, wherein a second fault test is at least one of a plurality of first fault tests of different types, and the preset test data written in the second fault test are different from the preset test data written in the corresponding first fault test; through carrying out a plurality of different types of first fault tests of writing in one kind of preset test data in first round of test, can detect out most trouble storage ware samples in first round of test, then repeatedly carry out the second fault test that needs to write in into a plurality of kinds of preset test data in second round of test, detect out remaining trouble sample gradually to can realize improving the efficiency that detects out the trouble sample when guaranteeing trouble sample relevance ratio.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 shows a schematic diagram of a system architecture in an embodiment of the disclosure.

FIG. 2 is a flow chart illustrating a method for testing memory failures in an embodiment of the present disclosure.

FIG. 3 is a schematic diagram illustrating a memory test flow according to an example embodiment.

FIG. 4 is a schematic diagram illustrating another memory test flow according to an example embodiment.

FIG. 5 is a block diagram illustrating a memory failure testing arrangement according to an example embodiment.

Fig. 6 shows a schematic structural diagram of an electronic device in an embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, apparatus, steps, etc. In other instances, well-known structures, methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise. The symbol "/" generally indicates that the former and latter associated objects are in an "or" relationship.

In the present disclosure, unless otherwise expressly specified or limited, the terms "connected" and the like are to be construed broadly, e.g., as meaning electrically connected or in communication with each other; may be directly connected or indirectly connected through an intermediate. The specific meaning of the above terms in the present disclosure can be understood as a specific case by a person of ordinary skill in the art.

The most basic links for manufacturing the memory chip product comprise design, tape-out, packaging and testing, wherein the cost of the four links is about 20% of the design, 40% of the tape-out, 35% of the packaging and 5% of the testing, although the cost of the testing is not high, the testing is the last link for controlling the product quality, if no good testing is available, the PPM (part PerMillion, million failure rate) of the product is too high, and the loss caused by return or compensation is far from 5% of the cost.

The testing process of the memory chip comprises four stages corresponding to the following four types of tests, and each stage of test aims at finding out device faults.

CP (Chip bonding, chip Probe) test: the method is characterized in that a probe is used for binding chips on a Wafer (Wafer), various signals are input into the chips, and the output responses of the chips are captured, compared and calculated.

Ft (Final Test ): in application and function test, performance test and reliability test, whether the chip functions normally and whether defects are generated in the packaging process are checked.

SLT (System Level Test): the test is carried out in a system environment, namely, the chip is put into a normal working environment to run functions so as to detect the quality of the chip.

4. And (3) reliability testing: such as ESD (Electro-Static Discharge) testing, HTOL (High Temperature Operating Life) testing, HAST (High Accelerated Stress Test), etc.

The memory failure is mostly caused by the phenomena of parasitic coupling and the like which may exist among the memory cells in the memory due to the dense memory cell array. For example:

1. Stuck-At Fault (SAF): the value in the memory cell is fixed to 0 or to l, and cannot be changed.

2. Open Fault (OF): one or more memory cells in the memory cell array are open-to-0 (open-to-0) or open-to-1 (open-to-1).

3. Transition Fault (TF): the memory cell cannot complete a 0-to-l conversion or a 1-to-0 conversion within a desired time when writing a value different from the current content. This failure can be seen as a special case of the SAF, which is substantially different because when the failed cell has a combinational failure with other cells at the same time, the above-mentioned incomplete conversion may be completed when the combinational failure is activated.

4. Coupling Fault (CF): a change in one cell of the memory results in a change in another adjacent cell. The coupling fault may in turn include: inversion (inversion) coupling failure: when the value of one cell changes, the value of the other cell is caused to change to its opposite state; idempotent coupling failure: when the memory cell is turned over, the coupling cell is forced to be '0' or '1'; bridge coupling failure (BF) a bridge coupling failure occurs when a short circuit or bridge exists between two or more units or signals, each bridge exhibiting certain logical behavior; state (state) coupling failure: when a value is a unit, it will cause another unit to be fixed to another value, for example, when the value of unit i is 1, the value of unit j will be 0 (i, j are positive integers).

5. Address decoder Fault (AF): the method comprises 4 cases:

the first is that a certain address cannot access any memory location;

the second is that a certain address can access a plurality of memory units simultaneously;

the third is that a certain memory cell cannot be accessed by any address;

the fourth is that a memory location can be accessed by multiple addresses simultaneously.

6. Maintenance Fault (RF): the memory cell cannot maintain its logic value over time, and such failure is typically caused by the pull-up blocking switch.

7. Neighboring mode Sensitive Fault (NPSF): the content of one cell or the ability to change the content of this cell is influenced by the content of another cell in the memory. For example, if the content of cell j is 1, then the content of cell i must be l, and so on.

As described above, these types of memory failures can be reflected as read-write anomalies of the memory cell array, and therefore, a failure test can be performed by reading out after writing test data. For the fault models, different test algorithms can be operated to perform fault tests in each test stage, and the modes of writing data and reading data are different for the different test algorithms. There are some memory samples that are hard to find faults that can be detected through multiple rounds of testing involving multiple algorithms, in which case some testing algorithms may need to be performed multiple times, some types of faults being detected by writing different data at each test, and multiple times of performing these tests take a lot of time.

Therefore, the present disclosure provides a memory failure testing method, which can detect most of failed memory samples in a first round of testing by performing a plurality of different types of first failure tests in which one type of preset test data is written in the first round of testing, and then repeatedly perform a second failure test in which a plurality of types of preset test data are written in a second round of testing, and gradually detect the remaining failed samples, thereby improving the efficiency of detecting the failed samples while ensuring the detection rate of the failed samples.

FIG. 1 illustrates an exemplary system architecture 10 to which the memory failure testing method or memory failure testing apparatus of the present disclosure may be applied.

As shown in fig. 1, system architecture 10 may include a memory 102, logic circuitry 104, and an upper computer 106. The Memory 102 may be a Random-Access Memory (RAM), such as a Dynamic Random-Access Memory (DRAM), a Static Random-Access Memory (SRAM), a Flash Memory (Flash Memory), and so on.

The logic circuit 104 is designed on the periphery of the memory 102, processes the address and data of the memory 102 under the control of the upper computer 106, and then directly applies the address and data to the corresponding pins of the memory 102. In the process of testing the memory 102, corresponding test vectors can be generated by software in the upper computer 106 according to different test algorithms and test chips, then the logic circuit 104 directly applies the test vectors to each pin of the memory 102, and then the logic circuit 104 sends the test results back to the upper computer 106 through a serial port. The comparison module of the upper computer 106 compares the test result with the standard response, and finally gives the test result of the memory 102.

Taking a DRAM with 64 pins as an example, the memory 102 has 64 bits each, and each test vector can only be 8 bits of data during serial port transceiving, so that data received by a serial port needs to be converted into 64 bits under clock control, and the data can be shifted by a shift register eight times to form a 64-bit data. After the shift register finishes four shifts, the test is started, the test result of the memory 102 is read out from the corresponding data output pin, and finally the test result is sent to the upper computer software through the serial port, and the test result is compared and further analyzed through the upper computer software.

It should be understood that the number of memories, logic circuits, and upper computers in FIG. 1 are merely illustrative. There may be any number of memories, logic circuits and upper computers as required by the implementation.

FIG. 2 is a flow chart illustrating a method of memory failure testing in accordance with an exemplary embodiment. The method shown in fig. 2 may be applied to the upper computer 106 of the above system, for example.

Referring to fig. 2, a method 20 provided by an embodiment of the present disclosure may include the following steps.

In step S202, a first round of testing is performed on the memory to be tested, where the first round of testing includes a plurality of first failure tests of different types that are performed in sequence, and performing the first failure test includes: writing preset test data into a storage unit in the memory; reading a storage unit in a memory to obtain read data; and obtaining a first fault test result according to the preset test data and the read data.

In some embodiments, a plurality of different types of first failure tests may be performed on the memory in sequence at a preset second priority. The priority of the test algorithm may be set according to factors such as the type of the memory, the major faults detected, and the like, and a plurality of first fault tests of different types may be selected in the first test round, such as a marching (March) algorithm, a Bit equalization (Bit equalization) algorithm, a Bit walking (Bit Walk) algorithm, a Random Address (Random Address) algorithm, a Pseudo-Random code Sequence alignment (PRBS Align) algorithm, and the like. By taking DRAM as an example, the test can be sequentially carried out according to the sequence of the March C algorithm, the Random Access algorithm, the other algorithms, the Bit Walk algorithm and the Bit Equalize algorithm in the first round of test, the fault coverage rate of the March C algorithm is higher, so the priority of the March C algorithm is higher, and the other algorithms can be a PRBS Align data algorithm, a PRBS Align Address algorithm and the like.

In some embodiments, the memory includes a plurality of memory cells, such as a DRAM, in which the smallest unit of memory function is implemented by a capacitor, referred to as a "bit," i.e., a binary bit. When a data reading operation is performed on the DRAM, the capacitance is connected to the data line through a switch, and then the high or low of the voltage on the capacitor is read, thereby determining whether it is a logic "0" or "1"; similarly, if "0" or "1" is written into the storage bit, the capacitor is connected to the data line, so that charge transfer occurs between the capacitor and the data line, and the voltage of the storage capacitor can be set to the voltage of the data line, thereby completing the data modification. The 8 bits may constitute one byte, and one memory cell may store one byte, that is, 8 binary bits. For example, the March C algorithm includes an operation of writing "0" or "1" in each bit in an ascending or descending order of address, that is, "0x00" or "0xFF" is written in each memory cell during the test.

In some embodiments, different test algorithms may be used to write memory cells different from read memory cells, such as the Random Address algorithm. Different test algorithms may write the same predetermined test data (e.g. all logic "0") or different predetermined test data in each memory cell, for example, a Checkerboard algorithm, in which the predetermined test data is initialized to make each memory bit have different values from its adjacent four bits, and then the bits of logic "0" and logic "1" are read/written respectively.

In some embodiments, when the first failure test is performed, an operation of writing preset test data is performed on each memory cell, a read operation is performed on each memory cell to obtain read data of each memory cell, and whether the read data and the written preset test data of the same memory cell are the same or not is compared. If the read data of each storage unit in the memory is the same as the written preset test data, obtaining a first fault test result as passing; and if the read data of at least one storage unit in the memory is different from the written preset test data, obtaining that the first fault test result is failed.

In step S204, it is determined whether the memory passes the first round of testing according to the first failure test result.

In some embodiments, a plurality of first fault tests of different types are sequentially performed, and after a current first fault test result is obtained, if the current first fault test result passes, a next first fault test is performed; if the current first fault test result is failed, the next first fault test can not be carried out, the first round of test is failed, the test is directly finished, and the memory is determined to be a fault sample. After each first failure test in the first round of tests passes, the memory is determined to pass the first round of tests, and a second round of tests can be performed.

In step S206, if the memory passes the first round of test, a second round of test is performed on the memory, where the second round of test includes a second failure test, where the second failure test is at least one of a plurality of different types of first failure tests, and the preset test data written in the second failure test is different from the preset test data written in the corresponding first failure test. The flow of detecting a failing memory sample through two rounds of testing can be seen with reference to FIG. 3.

In some embodiments, the second round of testing includes performing a plurality of third failure tests, where a third failure test is one of the second failure tests, and the plurality of preset test data written in the plurality of third failure tests respectively include different test data. The third failure test may be a test for detecting a memory failure in the first failure test, mainly by performing different preset test data (datatop) writing and reading operations a plurality of times, for example, a Bit equal algorithm, a Bit Walk algorithm, or the like.

In some embodiments, a plurality of predetermined test data may be respectively written in a first predetermined pattern in a plurality of third failure tests. Similarly, a plurality of predetermined test data are written in a second predetermined pattern in a plurality of fourth failure tests, respectively. For example, when the Bit Equalize algorithm is used for the third failure test or the fourth failure test, the Bit Equalize algorithm principle is Bit flipping with 6321 in units of 4 bits (bits), that is, by repeating the operations of writing and reading in ascending order of address for a plurality of times, where 0x00, 0x11, 0x22, 0x77 \8230iswritten in each memory cell in sequence during each test, where \8230iswritten in the first 4 bits or the last 4 bits of one memory cell in the mode of writing a logic value: 60, 61, 60, 8230, 30, 31, 30, 8230, 20, 21, 20 8230, 10, 1, 0 8230, and 8230. In such a test, a corresponding type of fault, such as a stuck-at fault, an open fault, a transition fault, a coupling fault, an adjacent mode sensitive fault, etc., can be detected through a pattern of writing preset test data. The third failure test may be performed in a loop for a plurality of times to detect the error data of the failed memory cell with a low recurrence rate, for example, in the case that the preset test data 0xEF is written into each memory cell 30 times, wherein one or more memory cells are read out as the error data 0xEE 3 times, that is, the recurrence rate of the error data is 3/30.

In some embodiments, the second failure test is at least two of a plurality of different types of first failure tests; the second round of testing may further include performing a plurality of fourth failure tests, where a fourth failure test is one of the second failure tests different from the third failure test, and the plurality of preset test data written in the plurality of fourth failure tests respectively include different test data. Embodiments of the fourth failure test may refer to the third failure test, for example, the third failure test may employ a Bit Walk algorithm and the fourth failure test may employ a Bit Equalize algorithm.

In some embodiments, a plurality of third failure tests and a plurality of fourth failure tests are sequentially performed on the memory according to a preset first priority, wherein a plurality of preset test data are respectively written in a first preset mode in the plurality of third failure tests, and a plurality of preset test data are respectively written in a second preset mode in the plurality of fourth failure tests. For example, the third failure test may employ a Bit Walk algorithm in which 0x01, 0x02, 0x04, 0x08 \ 8230; \8230;, and the fourth failure test may employ a Bit equize algorithm in which 0x00, 0x11, 0x22, 0x77 \8230;, and/or the fourth failure test may be sequentially written in each memory cell at each test. The test flow of performing the third failure test and the fourth failure test a plurality of times in the second round of test can refer to fig. 3.

In some embodiments, the second round of tests includes a plurality of second failure tests of different types performed in sequence, and the preset test data written in at least one of the second failure tests is different from the preset test data written in the corresponding first failure test. The second round of test may be a multi-round test, and the test for detecting the memory failure by performing different datatop writing and reading operations a plurality of times (i.e. the third failure test and the fourth failure test in the first round of test) is selected to be repeated once at each round of test, and the datatop written each time is different.

In some embodiments, the plurality of second failure tests may correspond to the plurality of first failure tests one to one, that is, each first failure test in the first round of tests may be repeated once in each round of tests in a plurality of rounds of tests of the second round of tests, and for a test in which a memory failure is detected by performing different datatop writing and reading operations a plurality of times, the datatop written each time is written in a preset pattern. The detailed implementation process can refer to fig. 4.

According to the memory fault testing method provided by the embodiment of the disclosure, a first round of testing including a plurality of first fault tests of different types which are sequentially performed is performed on a memory to be tested, and then a second round of testing including a second fault test is performed on the memory under the condition that the memory passes the first round of testing is determined according to a first fault testing result, wherein the performing of the first fault test includes: the method comprises the steps of writing preset test data into a storage unit in a memory, reading the storage unit in the memory to obtain read data, and obtaining a first fault test result according to the preset test data and the read data, wherein a second fault test is at least one of a plurality of first fault tests of different types, and the preset test data written in the second fault test is different from the preset test data written in the corresponding first fault test; through carrying out a plurality of different types of first fault tests of writing in one kind of preset test data in first round of test, can detect out most trouble storage ware samples in first round of test, then repeated the second fault test that needs to write in multiple kind of preset test data in second round of test, detect out remaining trouble sample gradually to can realize improving the efficiency that detects out the trouble sample when guaranteeing trouble sample relevance ratio.

FIG. 3 is a schematic diagram illustrating a memory test flow according to an example embodiment. As shown in fig. 3, after the test is started (S302), a first round of tests (S304) is performed, and different types of tests including a progress test (S3042), a random test (S3044), other tests (S3046), a bit walking test (S3048) in which 1 st type of preset test data (datatop-1) is written, a bit equalization test (S30410) in which 1 st type of preset test data (datatop-1) is written, and other tests (S30412) are sequentially performed in the first round of tests, where datatop-1 is representative data for selecting a corresponding test algorithm, a failure sample (a non-defective sample) is detected if the test fails in each test, the test flow is ended (S310), and a next test is performed if the test passes. The first round of test does not take a lot of time to detect the fault by using the change of datatop, and most of the faults are covered by different test algorithms in a short time, for example, the faults can cover about 70% of DRAM samples.

If the memory to be tested passes the first test round, a second test round is performed (S306). In the second round of test, a plurality of tests of a third failure test and a plurality of tests of a fourth failure test are sequentially performed, the plurality of tests of the third failure test may include a bit walk test (S3062) of writing 2 nd predetermined test data (datatop-2), a bit walk test (S3064) of writing 3 rd predetermined test data (datatop-3), a bit walk test (S3066) of writing nth (n is a positive integer) predetermined test data (datatop-n), and the like, the fourth failure test may include a bit equalization test (S3068) of writing 2 nd predetermined test data (datatop-2), a bit equalization test (S30610) of writing 3 th predetermined test data (datatop-3), a bit equalization test (S30612) of writing nth predetermined test data (datatop-n), and the like, the failure sample (disqualified sample) is detected if the test fails in each test, the test procedure (S310) is ended, the next test is performed if the test passes, and the procedure (S306308) is ended if all the tests pass, and the procedure is ended. By repeatedly executing the same test algorithm based on different DataTops in the second test, the remaining faults which are difficult to be found can be found in a longer time, for example, about 30% of the faults of DRAM samples can be detected.

After the first round of test and the second round of test pass through one time, the result of the qualified sample is obtained in step 308, and the step 302 is returned, and the first round of test and the second round of test are performed again to detect the fault with the lower recurrence rate.

According to the two-round testing process provided by the embodiment of the disclosure, the priority of the testing algorithm for detecting the fault by writing in various preset testing data is reduced, the first round of testing of different types of algorithms is performed in sequence, most faults are covered by different testing algorithms in a short time, the system testing efficiency can be greatly improved, the sample of the fault memory can be found as early as possible, and the testing cost is reduced.

FIG. 4 is a schematic diagram illustrating another memory test flow according to an example embodiment. As shown in fig. 4, after the test is started (S402), a first round of tests is performed (S404), and different types of tests including a forward test (S4042), a random test (S4044), other tests (S4046), a bit walking test (S4048) in which 1 st preset test data (datatop-1) is written, a bit equalization test (S40410) in which 1 st preset test data (datatop-1) is written, and other tests (S40412) are performed in sequence in the first round of tests, and if the tests do not pass, a faulty sample (failed sample) is detected, the test flow is ended (S410), if the tests pass, the next test is performed, and if all the tests pass, a qualified sample is obtained, and the test flow is ended (S308). The first round of test does not take a lot of time to detect the fault by using the change of datatop, and the majority of faults are covered by different test algorithms in a short time, for example, the faults can cover about 70% of DRAM samples.

If the memory to be tested passes the first test, a second test is performed (S406). The second round of test may be a multi-round test, and each first failure test in the first round of test is repeated once in each round of test, including a walk test (S4062), a random test (S4064), other tests (S4066), a bit walk test (S4068) in which xth (x is a positive integer) preset test data (datatop-x) is written, a bit balance test (S40610) in which xth (xth) preset test data (datatop-x) is written, and other tests (S40612), and in each test, if the test fails, a failure sample (failed sample) is detected, the test flow is ended (S410), if the test passes, the next test is performed, and if all passes, the step S4062 is returned, the second round of test of the next round is performed until all preset tests are completed, and if all passes, a qualified sample is obtained, and the test flow is ended (S308).

According to the multi-round test flow provided by the embodiment of the disclosure, a good efficiency improvement can be achieved by adjusting a test architecture, for example, 2GB LPDDR (Low Power Double Data Rate SDRAM (Synchronous Dynamic Random-Access Memory)) 4SLT test, if a bit walking test and a bit balancing test are performed for multiple tests of writing different Data tops in a first round of test, each round of time is about 2 hours, a 10-round repetition time is 20 hours, and a 30-round repetition time is 60 hours, which greatly limits the speed of analyzing and solving problems. By not paying attention to datatop in the first round of testing, most fault memory samples can be found through various types of testing, the system testing efficiency is greatly improved, the fault memory is found as early as possible, and the testing cost is reduced.

FIG. 5 is a block diagram illustrating a memory failure testing arrangement according to an exemplary embodiment. The apparatus shown in fig. 5 can be applied to, for example, the upper computer 106 of the above-described system.

Referring to fig. 5, an apparatus 50 provided by the embodiment of the disclosure may include a test module 502, a data writing module 504, and a data reading module 506.

The test module 502 may be configured to perform a first round of test on a memory to be tested, where the first round of test includes a plurality of first failure tests of different types that are performed in sequence, and the first failure test includes obtaining a first failure test result according to preset test data written into a memory cell in the memory and data read from the memory cell in the memory; determining whether the memory passes the first round of test according to the first fault test result; and if the memory passes the first round of test, performing a second round of test on the memory, wherein the second round of test comprises a second fault test, the second fault test is at least one of a plurality of first fault tests of different types, and the preset test data written in the second fault test is different from the preset test data written in the first fault test in the corresponding first round of test.

The test module 502 may also be used to: and sequentially carrying out a plurality of third fault tests and a plurality of fourth fault tests on the memory according to a preset first priority, wherein a plurality of preset test data are respectively written in the third fault tests in a first preset mode, and a plurality of preset test data are respectively written in the fourth fault tests in a second preset mode.

The test module 502 is further configured to sequentially perform a plurality of different types of first failure tests on the memory according to a preset second priority.

The second round of test includes performing a plurality of third failure tests, where the third failure test is one of the second failure tests, and the plurality of preset test data written in the plurality of third failure tests respectively include different test data.

The second round of test includes a plurality of different types of second fault tests that are performed in sequence, and the preset test data written in at least one second fault test is different from the preset test data written in the corresponding first fault test.

The plurality of second fault tests correspond to the plurality of first fault tests one to one.

The second failure test is at least two of the plurality of different types of first failure tests; the second round of test also comprises a plurality of times of fourth fault tests, wherein the fourth fault tests are different from one of the third fault tests in the plurality of second fault tests, and the plurality of preset test data respectively written in the plurality of times of fourth fault tests comprise different test data.

The test module 502 may also be used to: comparing whether the read data and the written preset test data of the same storage unit are the same or not; and if the read data of each storage unit in the memory is the same as the written preset test data, obtaining a first fault test result as pass.

The test module 502 may also be used to: and if the read data of at least one storage unit in the memory is different from the written preset test data, obtaining that the first fault test result is failed.

The data writing module 504 may be configured to perform an operation of writing preset test data to a memory cell in the memory when performing the first failure test.

The memory may include a plurality of memory cells; the data writing module 504 can also be used for writing the same preset test data into a plurality of memory cells in the memory.

The data writing module 504 may be further configured to write a plurality of predetermined test data in a first predetermined pattern during a plurality of third failure tests, respectively.

The data writing module 504 can also be used for writing preset test data into each memory cell.

The data reading module 506 may be configured to perform a read operation on a memory cell in the memory to obtain read data when performing the first failure test.

The data reading module 506 can also be used to perform a read operation on each memory cell to obtain read data of each memory cell.

The specific implementation of each module in the apparatus provided in the embodiment of the present disclosure may refer to the content in the foregoing method, and is not described here again.

Fig. 6 shows a schematic structural diagram of a testing apparatus in an embodiment of the present disclosure. It should be noted that the apparatus shown in fig. 6 is only an example of a computer system, and should not bring any limitation to the function and the scope of the application of the embodiments of the present disclosure.

As shown in fig. 6, the apparatus 600 includes a Central Processing Unit (CPU) 601 that can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 602 or a program loaded from a storage section 608 into a Random Access Memory (RAM) 603. In the RAM603, various programs and data necessary for the operation of the apparatus 600 are also stored. The CPU601, ROM 602, and RAM603 are connected to each other via a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.

The following components are connected to the I/O interface 605: an input portion 606 including a keyboard, a mouse, and the like; an output portion 607 including a display such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, and a speaker; a storage section 608 including a hard disk and the like; and a communication section 609 including a network interface card such as a LAN card, a modem, or the like. The communication section 609 performs communication processing via a network such as the internet. The driver 610 is also connected to the I/O interface 605 as needed. A removable medium 611 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 610 as necessary, so that a computer program read out therefrom is mounted in the storage section 608 as necessary.

In particular, the processes described above with reference to the flow diagrams may be implemented as computer software programs, according to embodiments of the present disclosure. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method illustrated in the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network through the communication section 609, and/or installed from the removable medium 611. The above-described functions defined in the system of the present disclosure are performed when the computer program is executed by a Central Processing Unit (CPU) 601.

It should be noted that the computer readable media shown in the present disclosure may be computer readable signal media or computer readable storage media or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In contrast, in the present disclosure, a computer-readable signal medium may include a propagated data signal with computer-readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The modules described in the embodiments of the present disclosure may be implemented by software or hardware. The described modules may also be provided in a processor, which may be described as: a processor includes a test module, a data write module, and a data read module. The names of the modules do not limit the modules themselves in some cases, and for example, a test module may also be described as a "module for testing a memory according to a host computer instruction".

As another aspect, the present disclosure also provides a computer-readable medium, which may be contained in the apparatus described in the above embodiments; or may be separate and not assembled into the device. The computer readable medium carries one or more programs which, when executed by a device, cause the device to comprise:

the method comprises the following steps of carrying out a first round of test on a memory to be tested, wherein the first round of test comprises a plurality of first fault tests of different types which are sequentially carried out, and the carrying out of the first fault tests comprises the following steps: writing preset test data into a storage unit in the memory; reading a storage unit in a memory to obtain read data; obtaining a first fault test result according to preset test data and the read data; determining whether the memory passes the first round of testing according to the first fault testing result; and if the memory passes the first round of test, performing a second round of test on the memory, wherein the second round of test comprises a second fault test, the second fault test is at least one of a plurality of first fault tests of different types, and preset test data written in the second fault test is different from preset test data written in the corresponding first fault test in the first round of test.

Exemplary embodiments of the present disclosure are specifically illustrated and described above. It is to be understood that the disclosure is not limited to the precise construction, arrangements, or instrumentalities described herein; on the contrary, the disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A memory failure testing method, comprising:

performing a first round of testing on a memory to be tested, the first round of testing including a plurality of different types of first failure tests performed in sequence, wherein performing the first failure tests includes:

writing preset test data into the storage unit in the memory;

reading a storage unit in the memory to obtain read data; and

obtaining a first fault test result according to the preset test data and the read data;

determining whether the memory passes the first round of testing according to the first fault testing result;

and if the memory passes the first round of test, performing a second round of test on the memory, wherein the second round of test comprises a second fault test, the second fault test is at least one of the first fault tests with different types, and preset test data written in the second fault test is different from preset test data written in the corresponding first fault test in the first round of test.

2. The method of claim 1, wherein the second round of testing includes performing a plurality of third failure tests, wherein the third failure test is one of the second failure tests, and wherein the plurality of predetermined test data written in the plurality of third failure tests respectively includes different test data.

3. The method of claim 2, wherein the second failure test is at least two of the plurality of different types of first failure tests;

the second round of test further includes performing a fourth failure test a plurality of times, where the fourth failure test is one of the second failure tests different from the third failure test, and a plurality of preset test data written in the fourth failure tests respectively include different test data.

4. The method according to claim 3, wherein a plurality of predetermined test data are written in a second predetermined pattern in the plurality of the fourth failure tests, respectively.

5. The method of claim 3, wherein the performing a second round of testing on the memory comprises:

and sequentially performing a plurality of times of third fault tests and a plurality of times of fourth fault tests on the memory according to a preset first priority, wherein a plurality of preset test data are respectively written in a first preset mode in the plurality of times of third fault tests, and a plurality of preset test data are respectively written in a second preset mode in the plurality of times of fourth fault tests.

6. The method according to claim 2, wherein a plurality of predetermined test data are written in a first predetermined pattern in the plurality of third failure tests, respectively.

7. The method according to claim 1, wherein the second round of testing includes a plurality of second failure tests of different types performed sequentially, and the preset test data written in at least one of the second failure tests is different from the preset test data written in the corresponding first failure test.

8. The method of claim 7, wherein a plurality of the second failure tests correspond one-to-one to a plurality of the first failure tests.

9. The method of claim 1, wherein the memory comprises a plurality of memory cells;

the operation of writing preset test data into the memory cells in the memory comprises:

writing preset test data into each storage unit;

the reading operation of the memory unit in the memory, and obtaining the read data includes:

reading each storage unit to obtain read data of each storage unit;

the obtaining a first fault test result according to the preset test data and the read data comprises:

comparing whether the read data and the written preset test data of the same storage unit are the same or not;

and if the read data of each storage unit in the memory is the same as the written preset test data, obtaining that the first fault test result is a pass.

10. The method of claim 9, wherein obtaining a first failure test result according to the predetermined test data and the read data further comprises:

and if the read data of at least one storage unit in the memory is different from the written preset test data, obtaining that the first fault test result is failed.

11. The method of claim 1, wherein the memory comprises a plurality of memory cells;

and writing the same preset test data into the plurality of memory units in the memory.

12. The method of claim 1, wherein the performing a first round of testing on the memory comprises:

and sequentially carrying out the plurality of different types of first fault tests on the memory according to a preset second priority.

13. A memory failure test apparatus, comprising:

the test module is used for carrying out a first round of test on a memory to be tested, the first round of test comprises a plurality of first fault tests of different types which are sequentially carried out, and the first fault test comprises obtaining a first fault test result according to preset test data written into a storage unit in the memory and data read from the storage unit in the memory; determining whether the memory passes the first round of testing according to the first fault test result; if the memory passes the first round of test, performing a second round of test on the memory, wherein the second round of test comprises a second fault test, the second fault test is at least one of the plurality of different types of first fault tests, and preset test data written in the second fault test is different from preset test data written in the corresponding first fault test in the first round of test;

the data writing module is used for writing preset test data into the storage unit in the memory when the first fault test is carried out;

and the data reading module is used for reading the storage unit in the memory to obtain read data when the first fault test is carried out.

14. A test apparatus, comprising: memory, processor and executable instructions stored in the memory and executable in the processor, characterized in that the processor implements the method according to any of claims 1-12 when executing the executable instructions.

15. A computer-readable storage medium having computer-executable instructions stored thereon which, when executed by a processor, implement the method of any one of claims 1-12.