CN117783836A - PRBS generation and self-detection system and PRBS self-detection method - Google Patents
PRBS generation and self-detection system and PRBS self-detection method Download PDFInfo
- Publication number
- CN117783836A CN117783836A CN202410207864.4A CN202410207864A CN117783836A CN 117783836 A CN117783836 A CN 117783836A CN 202410207864 A CN202410207864 A CN 202410207864A CN 117783836 A CN117783836 A CN 117783836A
- Authority
- CN
- China
- Prior art keywords
- prbs
- self
- recovered
- phase interpolator
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 101150071746 Pbsn gene Proteins 0.000 title claims abstract description 85
- 238000001514 detection method Methods 0.000 title claims abstract description 63
- 238000012937 correction Methods 0.000 claims abstract description 63
- 238000012545 processing Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 13
- 238000011084 recovery Methods 0.000 claims description 9
- 230000003111 delayed effect Effects 0.000 claims description 2
- 238000010998 test method Methods 0.000 claims 1
- 238000012360 testing method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000013459 approach Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000013075 data extraction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a PRBS generation and self-detection system and a PRBS self-detection method. In order to solve the problems of how to quickly and low-cost perform phase calibration on clock and simplify system time sequence in a high-speed interface chip, the invention adopts a PRBS detection circuit to perform PRBS self-detection, wherein the PRBS detection circuit comprises: a phase interpolator for phase self-calibrating the recovered clock signal; a detector for detecting an error code in the recovered data signal based on the recovered data signal and a delay clock output from the phase interpolator; and the correction module is used for executing correction processing on the error code detected by the detector and feeding back a correction result to the phase interpolator. The invention carries out phase self-calibration on the clock based on the phase interpolator, saves the cost, simplifies the time sequence of the system and improves the efficiency.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a PRBS (partial response random access memory) generation and self-detection system and a PRBS self-detection method in a high-speed interface chip.
Background
In high speed interface chips, the signal passing through the channel needs to be tested to determine the loss of signal. Pseudo random code (PRBS), which is similar to data transmission in real scenarios, is often used to simulate real data streams for testing high speed serial lanes.
FIG. 1 is a schematic diagram of PRBS testing in the prior art. After entering the PRBS test mode, a PRBS generator in the interface chip generates pseudo-random codes, the pseudo-random codes are input into the signal channel, the signal channel recovers clocks and data, a PRBS detection circuit detects error codes generated by the recovered data after passing through the signal channel, and the error rates are counted.
However, in the conventional serial PRBS detection method, the reference signal of the PRBS generator is compared with the data recovered by the signal path, and since the clock and the data have relative phase delays after passing through the signal path and passing through the trace, the data may be corrupted when the clock is directly used for data extraction, and therefore calibration is required to align the phase relationship between the clock and the data.
In some improved PRBS test schemes, delay-Locked Loop (DLL) or passive polyphase filter (Passive Polyphase Filter, PPF) units are used to phase calibrate the clock, however this approach is implemented with significant power consumption and area costs.
How to quickly and inexpensively calibrate the clock and simplify the system timing is a technical problem that needs to be solved in the field.
Disclosure of Invention
In order to alleviate or partially alleviate the above technical problem, the solution of the present invention is as follows:
a PRBS generation and self-detection system, the PRBS generation and self-detection system comprising: a PRBS generator for generating a pseudo-random code; a signal path having an input coupled to the PRBS generator for clock and data recovery; a PRBS detection circuit having an input coupled to the signal path for detecting an error in the recovered data signal and performing a correction process on the generated error;
wherein, PRBS detection circuit includes: a phase interpolator for phase self-calibrating the recovered clock signal; a detector for detecting an error in the recovered data signal based on the recovered data signal and a delay clock output from the phase interpolator; and the correction module is used for executing correction processing on the error code detected by the detector and feeding back a correction result to the phase interpolator.
In certain classes of embodiments, the PRBS detection circuit further comprises: and the error code statistics circuit is used for counting the error codes and outputting error codes.
In certain classes of embodiments, the PRBS generation and self-detection system includes a correction mode and an error statistics mode.
In some types of embodiments, when the detector detects that the recovered clock signal is not aligned with the recovered data signal, entering a correction mode, performing correction processing on the detection result of the detector, and feeding back the correction result to the phase interpolator; the correction mode ends when the detector detects that the recovered clock signal is aligned with the recovered data signal.
In some class of embodiments, before performing the correction process, it is confirmed whether the recovered clock signal and the recovered data signal are aligned based on the output of the detector, and the correction process is performed when not aligned.
In some embodiments, after the correction mode is finished, an error code statistics mode is entered to count the data codes generated by errors in the recovered data signal and output the data codes.
In certain classes of embodiments, the PRBS detection circuit further comprises:
the frequency divider is coupled between the clock signal recovered by the signal channel and the phase interpolator and is used for dividing frequency; the frequency multiplier is coupled between the phase interpolator and the detector; the frequency division number of the frequency divider is equal to the frequency multiplication number of the frequency multiplier.
In certain classes of embodiments, the signal path utilizes a clock data recovery circuit to derive a recovered clock signal and a recovered data signal.
In certain classes of embodiments, the signal path is a high-speed interface chip.
In certain classes of embodiments, the phase interpolator is a half-rate phase interpolator.
In certain types of embodiments, the PRBS generator is integrated with the signal path and the PRBS detection circuit.
The invention also relates to a PRBS self-detection method, which comprises the following steps:
inputting PRBS codes into a signal channel, and recovering clocks and data by a clock data recovery circuit to obtain recovered clock signals and recovered data signals;
the recovered clock signal is processed by a phase interpolator to obtain a delay clock;
the detector detects error codes in the recovered data signal based on the recovered data signal and the delay clock output by the phase interpolator;
and executing correction processing on the error code detected by the detector, and feeding back a correction result to the phase interpolator to realize a closed loop function of automatic calibration of the clock by the phase interpolator.
In some class of embodiments, the number of bit errors or bit error rate is counted.
In some embodiments, before the phase interpolator processes, the recovered clock signal is divided, and the delayed clock processed by the phase interpolator is multiplied and then transmitted to the detector; wherein the frequency division number is equal to the frequency multiplication number.
In some types of embodiments, when the detector detects that the recovered clock signal is not aligned with the recovered data signal, entering a correction mode, performing correction processing on the detection result of the detector, and feeding back the correction result to the phase interpolator; the correction mode ends when the detector detects that the recovered clock signal is aligned with the recovered data signal.
In some class of embodiments, before performing the correction process, it is confirmed whether the recovered clock signal and the recovered data signal are aligned based on the output of the detector, and the correction process is performed when not aligned.
In some embodiments, after the correction mode is finished, an error code statistics mode is entered to count the data codes generated by errors in the recovered data signal and output the data codes.
The technical scheme of the invention has one or more of the following beneficial technical effects:
(1) The invention adopts the PRBS self-detection method to detect the error code, thereby simplifying the time sequence of the system; in addition, the PRBS detection circuit has no requirement on the input time sequence, and can detect the corresponding PRBS code no matter how much the delay of the input data is;
(2) The invention adopts a half-rate phase interpolator (Phase Interpolator, PI) to carry out phase self-calibration on the clock, thereby saving the cost;
(3) The calibration circuit and the error code statistics circuit adopt a digital-analog mixed scheme, so that the cost is saved, and the efficiency is improved;
(4) The invention comprises a complete set of PRBS generator and PRBS detection circuit, avoids the need of externally connecting related circuits to count the error rate of the traditional interface chip, and greatly simplifies the complicated test flow.
Furthermore, other advantageous effects that the present invention has will be mentioned in the specific embodiments.
Drawings
FIG. 1 is a schematic diagram of PRBS testing in the prior art;
FIG. 2 is a PRBS generation and self-detection system according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the detector output;
FIG. 4 is a PRBS generation and self-test system according to a preferred embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Numerous specific details are set forth in the following description in order to provide a better understanding of the invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.
Pseudo random codes (PRBS), in which the 0 and 1 of the PRBS pattern occur randomly in one period, but the entire data stream has a plurality of periods, and the data stream of any period is identical, and is therefore called Pseudo random.
FIG. 2 is a PRBS generating and self-detecting system according to an embodiment of the present invention, including a PRBS generator, a signal path, and a PRBS detecting circuit.
And the PRBS generator is used for generating pseudo-random codes.
And the signal channel is coupled with the PRBS generator and used for carrying out clock and data recovery to obtain a recovered clock signal and a recovered data signal. Optionally, the signal path includes a clock data recovery circuit (Clock and Data Recovery, CDR).
And the PRBS detection circuit is coupled with the signal channel and is used for detecting error codes in the recovered data signals and performing correction processing on the error codes.
The invention introduces a phase interpolator (Phase Interpolator, PI) in the PRBS detection circuit to carry out phase self-calibration on the recovered clock signal so as to align the phase relation of the clock and the data, thereby saving the cost, realizing the adjustment of the range of 2 Unit Intervals (UI) of clock delay and finding 2 alignment eyes during delay calibration.
Optionally, the phase interpolator is a half-rate phase interpolator, so that the efficiency is further improved, and the power consumption is saved.
Furthermore, the invention adopts a self-detection method to detect the error code so as to simplify the time sequence of the system.
Preferably, the PRBS detection circuit comprises a phase interpolator, a detector, a correction and statistics module.
The input end of the phase interpolator is coupled with the clock signal recovered by the PRBS detection circuit and is used for carrying out phase self-calibration on the recovered clock signal;
and the detector is coupled with the recovered data signal and the delay clock output by the phase interpolator so as to output a phase relation between the recovered clock signal and the recovered data signal and detect the data code generated by mistake in the recovered data signal.
Optionally, the PRBS generation and self-detection system includes a correction module coupled to the detector for correcting and feeding back a correction result to the phase interpolator, and implementing a closed loop function of the phase interpolator for automatic calibration of the clock.
Further, the correction module is replaced with an alignment detection and correction module that recognizes and confirms whether the recovered clock signal and the recovered data signal are aligned based on the output of the detector, and performs correction processing when not aligned.
Preferably, the PRBS generation and self-detection system further comprises an error statistics circuit for performing error statistics and outputting statistics such as error rates.
The correction module and the error code statistics circuit can be designed or integrated together, are collectively called a correction and statistics module, and are used for performing correction processing on generated error codes, performing error code statistics and outputting statistics results when correction is completed. And the correction and statistics module adopts a digital-analog mixing scheme, so that the cost is saved and the efficiency is improved.
FIG. 3 is a schematic diagram of the detector output. The detector detects the phase relation between the recovered clock signal and the recovered data signal, when the recovered clock signal and the recovered data signal are aligned, the detector outputs 0, and occasionally output 1 is an error code, and the voltage approaches to 0 after being filtered by the low-pass filter. When the two are not aligned, the detector outputs a large number of 1 s, and the voltage approaches vdd/2 after being filtered by the low-pass filter, wherein vdd is the power supply voltage.
The PRBS generation and self-detection system of the present invention has two modes: correction mode and error statistics mode.
When the detector detects that the recovered clock signal is not aligned with the recovered data signal, the detector enters a correction mode, performs correction processing on the detection result of the detector, and feeds the correction result back to the phase interpolator to realize the closed loop function of the phase interpolator for automatically calibrating the clock. Alternatively, before the correction process is performed, whether the recovered clock signal and the recovered data signal are aligned is recognized or confirmed based on the output of the detector, and the correction process is performed when not aligned.
The correction mode ends when the detector detects that the recovered clock signal is aligned with the recovered data signal. The system can enter into error code statistics mode to count the error generated data codes in the recovered data signals and output the data codes.
The invention also relates to a PRBS self-detection method, which comprises the following steps:
PRBS code input signal channel, recovering clock and data by clock data recovery circuit, obtaining recovered clock signal and recovered data signal;
the recovered clock signal is processed by a phase interpolator to obtain a delay clock; the detector detects that the PRBS code of high speed is erroneously generated based on the recovered data signal and the delay clock;
the output error code of the detector is input into a correction module to output a digital correction signal, and the error code quantity or error code rate is counted, wherein the correction result is fed back to the phase interpolator, so that the closed loop function of the phase interpolator for automatically calibrating the clock is realized.
FIG. 4 is a PRBS generation and self-test system according to a preferred embodiment of the present invention. The correction and statistics module comprises an alignment detection and correction module and an error code statistics circuit. The alignment detection and correction module comprises a low-pass filter, a comparator and a digital calibration circuit, wherein the low-pass filter is used for filtering the output result of the detector, and the comparator is used for comparing the filtering result of the low-pass filter with a reference signal and outputting the comparison result to the digital calibration circuit for calibration.
The error code statistics circuit comprises an accumulator and an error code statistics circuit, when the recovered clock signal is detected to be aligned with the recovered data signal, the system can enter an error code statistics mode, and the error generated data codes in the recovered data signal are accumulated and counted and output.
Optionally, the PRBS generation and self-detection system further comprises a frequency divider and a frequency multiplier.
The frequency divider is coupled between the clock signal (set as f) recovered by the signal channel and PI for frequency division, and the phase interpolator performs delay adjustment based on the divided clock. Preferably, the frequency divider is a 2-frequency divider, and the phase interpolator implements adjustment of a clock delay by a range of 2 Unit Intervals (UI) and nonlinearity.
The frequency multiplier is coupled between the phase interpolator and the detector and is used for multiplying the frequency division clock to recover the clock with the frequency f and ensure that the output duty ratio is 50 percent so as to ensure the reliability of the system.
Based on the PRBS generation and self-detection system, error code detection is carried out, and only the clock input to the detector is required to be calibrated within a time interval, so that the time sequence of the system is simplified.
The phase interpolator of the invention adopts a half-rate method, realizes the adjustment of 2 time interval ranges of clock delay, and enables the recovered clock signal to be aligned with the middle of a data eye diagram by adjusting the phase of the recovered clock back and forth. Meanwhile, 2 alignment eyes can be found in the calibration process, so that the power consumption area of the phase interpolator module is reduced.
In addition, the PRBS generator, the signal path and the PRBS detection circuit can be integrated together, so that the problem that the PRBS error rate statistics is carried out by externally connecting the PRBS generator and the PRBS detection circuit to a traditional interface chip is avoided, and the flow is simplified.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A PRBS generation and self-detection system, the PRBS generation and self-detection system comprising:
a PRBS generator for generating a pseudo-random code;
a signal path, an input of the signal path being coupled to the PRBS generator to obtain a recovered clock signal and a recovered data signal after clock and data recovery;
a PRBS detection circuit having an input coupled to the output of the signal path for detecting errors in the recovered data signal and performing correction processing on the generated errors;
wherein, PRBS detection circuit includes:
a phase interpolator for performing phase self-calibration on the recovered clock signal;
a detector for detecting an error in the recovered data signal based on the recovered data signal and a delay clock output from the phase interpolator;
and the correction module is used for executing correction processing on the error code detected by the detector and feeding back a correction result to the phase interpolator.
2. The PRBS generation and self-detection system according to claim 1, wherein the PRBS detection circuit further comprises:
and the error code statistics circuit is used for counting the error codes and outputting error codes.
3. The PRBS generation and self-detection system according to claim 2, wherein:
the PRBS generation and self-detection system includes a correction mode and an error statistics mode.
4. A PRBS generation and self-detection system according to any one of claims 1 to 3, characterized in that:
when the detector detects that the recovered clock signal is not aligned with the recovered data signal, the detector enters a correction mode, performs correction processing on the detection result of the detector, and feeds the correction result back to the phase interpolator;
the correction mode ends when the detector detects that the recovered clock signal is aligned with the recovered data signal.
5. The PRBS generation and self-detection system according to claim 4, wherein:
before performing the correction processing, whether the recovered clock signal and the recovered data signal are aligned or not is confirmed based on the output of the detector, and the correction processing is performed when the clock signal and the recovered data signal are not aligned.
6. The PRBS generation and self-detection system according to claim 4, wherein:
after the correction mode is finished, an error code statistics mode is entered to count the data codes generated by errors in the recovered data signals and output the data codes.
7. The PRBS generation and self-detection system according to claim 4, wherein the PRBS detection circuit further comprises:
the frequency divider is coupled between the clock signal recovered by the signal channel and the phase interpolator and is used for dividing frequency;
the frequency multiplier is coupled between the phase interpolator and the detector;
the frequency division number of the frequency divider is equal to the frequency multiplication number of the frequency multiplier.
8. A PRBS self-test method, comprising the steps of:
inputting PRBS codes into a signal channel, and recovering clocks and data by a clock data recovery circuit to obtain recovered clock signals and recovered data signals;
the recovered clock signal is processed by a phase interpolator to obtain a delay clock output by the phase interpolator;
the detector detects error codes in the recovered data signal based on the recovered data signal and the delay clock output by the phase interpolator;
and executing correction processing on the error code detected by the detector, and feeding back a correction result to the phase interpolator to realize a closed loop function of automatic clock calibration.
9. The PRBS self-detection method according to claim 8, wherein:
the PRBS self-detection method further comprises the following steps: and counting the number of error codes or the error rate.
10. The PRBS self-detection method according to claim 8 or 9, characterized in that:
before the phase interpolator processes, the recovered clock signal is divided, and the delayed clock output by the phase interpolator is multiplied and then transmitted to the detector;
wherein the frequency division number is equal to the frequency multiplication number.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410207864.4A CN117783836B (en) | 2024-02-26 | 2024-02-26 | PRBS generation and self-detection system and PRBS self-detection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410207864.4A CN117783836B (en) | 2024-02-26 | 2024-02-26 | PRBS generation and self-detection system and PRBS self-detection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117783836A true CN117783836A (en) | 2024-03-29 |
| CN117783836B CN117783836B (en) | 2024-06-11 |
Family
ID=90396737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410207864.4A Active CN117783836B (en) | 2024-02-26 | 2024-02-26 | PRBS generation and self-detection system and PRBS self-detection method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117783836B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118509130A (en) * | 2024-07-17 | 2024-08-16 | 成都电科星拓科技有限公司 | Phase interpolation calibration method, digital calibration module and pseudo-random detection system |
| CN119011078A (en) * | 2024-07-17 | 2024-11-22 | 成都电科星拓科技有限公司 | High-precision serial PRBS (PRBS) generation and error code detection system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1905435A (en) * | 2005-07-29 | 2007-01-31 | 国际商业机器公司 | Methods and apparatus for clock synchronization |
| CN104348681A (en) * | 2013-08-02 | 2015-02-11 | 阿尔特拉公司 | Apparatus and methods for on-die instrumentation |
| CN110601693A (en) * | 2019-07-31 | 2019-12-20 | 合肥新相微电子有限公司 | Clock data recovery circuit of auxiliary channel in TFT-LCD (thin film transistor-liquid crystal display) in-screen interface |
| CN116545818A (en) * | 2023-05-08 | 2023-08-04 | 上海米硅科技有限公司 | Clock data alignment method and device applied to pseudo-random binary sequence |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100438662C (en) * | 2005-06-10 | 2008-11-26 | 上海华为技术有限公司 | Method for realizing data transmission between baseband-processing unit and RF processing unit |
| CN107634761B (en) * | 2017-09-29 | 2020-11-13 | 中国科学院半导体研究所 | Digital phase-locked loop frequency synthesis device |
| FR3094593B1 (en) * | 2019-03-29 | 2021-02-19 | Teledyne E2V Semiconductors Sas | Method of synchronizing digital data sent in series |
| CN111245529B (en) * | 2020-04-09 | 2020-07-31 | 成都坤恒顺维科技股份有限公司 | Phase calibration method of digital phased array antenna and phased array antenna |
| CN115994504A (en) * | 2022-10-31 | 2023-04-21 | 南京美辰微电子有限公司 | Data recovery system and method based on timing margin detection |
| CN116166088A (en) * | 2022-11-14 | 2023-05-26 | 集益威半导体(上海)有限公司 | Error calibration circuit and method for phase interpolator |
| CN116707521A (en) * | 2023-06-15 | 2023-09-05 | 东南大学 | 8.1Gbps eDP high-speed display interface receiving end clock data recovery key circuit system |
| CN117336848A (en) * | 2023-11-13 | 2024-01-02 | 中国电子科技集团公司第五十四研究所 | Wireless time synchronization method |
-
2024
- 2024-02-26 CN CN202410207864.4A patent/CN117783836B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1905435A (en) * | 2005-07-29 | 2007-01-31 | 国际商业机器公司 | Methods and apparatus for clock synchronization |
| CN104348681A (en) * | 2013-08-02 | 2015-02-11 | 阿尔特拉公司 | Apparatus and methods for on-die instrumentation |
| CN110601693A (en) * | 2019-07-31 | 2019-12-20 | 合肥新相微电子有限公司 | Clock data recovery circuit of auxiliary channel in TFT-LCD (thin film transistor-liquid crystal display) in-screen interface |
| CN116545818A (en) * | 2023-05-08 | 2023-08-04 | 上海米硅科技有限公司 | Clock data alignment method and device applied to pseudo-random binary sequence |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118509130A (en) * | 2024-07-17 | 2024-08-16 | 成都电科星拓科技有限公司 | Phase interpolation calibration method, digital calibration module and pseudo-random detection system |
| CN119011078A (en) * | 2024-07-17 | 2024-11-22 | 成都电科星拓科技有限公司 | High-precision serial PRBS (PRBS) generation and error code detection system |
| CN119011078B (en) * | 2024-07-17 | 2025-05-30 | 成都电科星拓科技有限公司 | High-precision serial PRBS (PRBS) generation and error code detection system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117783836B (en) | 2024-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN117783836B (en) | PRBS generation and self-detection system and PRBS self-detection method | |
| US7533317B2 (en) | Serializer/deserializer circuit for jitter sensitivity characterization | |
| US9838165B2 (en) | Emulation and debug interfaces for testing an integrated circuit with an asynchronous microcontroller | |
| US7869544B2 (en) | System for measuring an eyewidth of a data signal in an asynchronous system | |
| US8468398B2 (en) | Loopback testing with phase alignment of a sampling clock at a test receiver apparatus | |
| US9255966B2 (en) | Receiver circuit, semiconductor integrated circuit, and test method | |
| JP2008175646A (en) | Semiconductor device, semiconductor device test circuit, and test method | |
| US7251765B2 (en) | Semiconductor integrated circuit and method for testing a semiconductor integrated circuit | |
| KR20070086147A (en) | Variable delay device, method of generating predetermined delay and system for on-chip jitter injection | |
| CN101641605A (en) | Data receiving circuit, tester using same, and timing adjusting circuit for strobe signal and method | |
| US6857089B2 (en) | Differential receiver architecture | |
| US6998889B2 (en) | Circuit, apparatus and method for obtaining a lock state value | |
| US20100251042A1 (en) | Double data rate memory physical interface high speed testing using self checking loopback | |
| US20100097102A1 (en) | Semiconductor integrated circuit and method for testing semiconductor integrated circuit | |
| US8155215B2 (en) | Transmission system, transmitter, receiver, and transmission method | |
| CN113055247A (en) | Multi-channel high-speed transceiver loopback test method and device for FPGA | |
| US20050055619A1 (en) | Method, system, and apparatus for bit error capture and analysis for serial interfaces | |
| CN119011078B (en) | High-precision serial PRBS (PRBS) generation and error code detection system | |
| CN110460329B (en) | A Fault-Oriented Phase-Locked Loop Test Circuit | |
| US20080095224A1 (en) | Semiconductor integrated circuit | |
| WO2010018544A1 (en) | Testing of a transmission and reception system | |
| CN118900118B (en) | A control circuit for clock signal delay | |
| US7519139B1 (en) | Signal monitoring systems and methods | |
| JPH06141056A (en) | Error addition circuit | |
| US20060188047A1 (en) | Method and circuitry for extracting clock in clock data recovery system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |