CN118900118B

CN118900118B - A control circuit for clock signal delay

Info

Publication number: CN118900118B
Application number: CN202411379078.9A
Authority: CN
Inventors: 庞高远; 刘德启
Original assignee: Zhongyin Microelectronics Nanjing Co ltd
Current assignee: Zhongyin Microelectronics Nanjing Co ltd
Priority date: 2024-09-30
Filing date: 2024-09-30
Publication date: 2025-02-11
Anticipated expiration: 2044-09-30
Also published as: CN118900118A

Abstract

The purpose of the present invention is to provide a control circuit for clock signal delay, the circuit comprising: a first variable delay line, a second variable delay line and a 1UI/2UI calibration circuit; the input end of the first variable delay line is connected to the clock signal, and the output end is connected to the 1UI/2UI calibration circuit; the input end of the second variable delay line is connected to the clock signal, and the output end is connected to the 1UI/2UI calibration circuit; the 1UI/2UI calibration circuit is calibrated according to the clock signals output by the first variable delay line and the second variable delay line. The present invention calibrates so that DQS samples the correct DQ, and obtains a delay line of the clock signal 1UI/2UI through calibration, and is not affected by the setup time and hold time of the D flip-flop itself, thereby achieving a more accurate 1UI/2UI calibration.

Description

Clock signal delay control circuit

Technical Field

The invention relates to the technical field of electronic circuits, in particular to a control circuit for clock signal delay.

Background

With the development of integrated circuit technology, the speed of the circuit is faster and faster, and the clock frequency is continuously increased. The principle of clock sampling is based on the nyquist sampling theorem, which states that during sampling, the sampling frequency must be equal to or greater than twice the highest frequency in the analog signal to completely recover the original analog signal. The process of clock sampling mainly comprises two steps, sampling and quantization. Sampling refers to instantaneous sampling of an analog signal triggered by a given clock signal. Quantization is the conversion of sampled continuous analog signal values into discrete digital signal values. In clock sampling, the clock signal plays a vital role. The stability and accuracy of the clock signal directly affect the accuracy of the sampling and the quality of the signal recovery. Typically, the clock signal is provided by a crystal oscillator, generated by a frequency-stabilized oscillator, and frequency adjusted by a frequency divider circuit.

In DDR IP applications, the unit time interval (UI, 1UI being half of the clock period) between the Data (DQ) and the sampling clock (DQs) is smaller and smaller, and the relative positions of the DQ and DQs need to be trained to sample the DQs to the correct DQ, and enough free time is reserved. In the DDR PHY circuit, it is necessary to obtain a delay line having a time equal to 1UI and 2UI, and further adjust the DQS relative position to complete sampling of DQ. However, in the existing 1UI calibration circuit, the D flip-flop itself is greatly affected by the setup and hold time, resulting in inaccurate calibration. As shown in fig. 2, when the phase difference between clk_dly and clk_ NDLY is smaller than 1UI, FLAG0 is 0, FLAG1 is 1, when the variable delay line 2 is gradually increased, clk_dly is pushed to have a phase difference of 1UI with clk_ NDLY, FLAG0 jumps to 1, FLAG1 jumps to 0, and at this time, the phase difference of the two variable delay lines is 1UI. However, this result is affected by the setup and hold times of the D flip-flops themselves, which are both present when CLK DLY and CLK NDLY sample each other, resulting in an inaccurate 1UI calibration result, which is essentially a superposition of the value of the clock signal 1UI and the setup/hold times.

Disclosure of Invention

The invention aims to provide a control circuit for clock signal delay, which can train the relative positions of DQ and DQS in DDR PHY IP through calibration, so that DQS samples to correct DQ and enough margin is reserved. The delay line of the clock signal 1UI/2UI is obtained through calibration, and meanwhile, the delay line is not influenced by the built-up time and the holding time of the D trigger, so that more accurate 1UI/2UI calibration is realized.

A control circuit for clock signal delay comprises a first variable delay line, a second variable delay line and a 1UI/2UI calibration circuit;

The input end of the first variable delay line is connected with a clock signal, and the output end of the first variable delay line is connected with a 1UI/2UI calibration circuit;

The input end of the second variable delay line is connected with a clock signal, and the output end of the second variable delay line is connected with a 1UI/2UI calibration circuit;

the 1UI/2UI calibration circuit calibrates according to clock signals output by the first variable delay line and the second variable delay line.

Preferably, the 1UI/2UI calibration circuit comprises a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, a first amplifier, a first signal selector, a second signal selector and a phase discrimination module;

The D end of the first trigger is connected with the CAL EN, the Q end of the first trigger is connected with the input end of the first amplifier, and the CLK end of the first trigger is connected with CLK NDLY;

The end D of the second trigger is connected with the output end of the first amplifier, the end Q is connected with the end 0 of the first signal selector, and the end CLK is connected CLK NDLY;

The end D of the third trigger is connected with CAL EN, the end Q is connected with the end 1 of the first signal selector, and the end CLK is connected with CLK NDLY;

the D end of the fourth trigger is connected with the CAL EN, the Q end of the fourth trigger is connected with the 0 end of the second signal selector, and the CLK end of the fourth trigger is connected with the CLK DLY;

The D end of the fifth trigger is connected with the CAL EN, the Q end of the fifth trigger is connected with the 1 end of the second signal selector, and the CLK end of the fifth trigger is connected with the CLK DLY;

the output ends of the first signal selector and the second signal selector are connected with the input end of the phase discrimination module.

Preferably, the first variable delay line is a fixed length delay line.

Preferably, the length of the second variable delay line is adjusted in accordance with the output of the calibration circuit.

Preferably, the phase discrimination module comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube and a first NOT gate;

The grid electrode of the first MOS tube is connected with the output end of the second signal selector, and the drain electrode is connected with the drain electrode of the second MOS tube and the drain electrode of the fifth MOS tube;

the drain electrode of the second MOS tube is connected with the grid electrode of the third MOS tube;

the grid electrode of the third MOS tube is connected with the grid electrode of the sixth MOS tube, and the drain electrode of the third MOS tube is connected with the input end of the first NOT gate;

The grid electrode of the fourth MOS tube is connected with the output end of the first signal selector, and the drain electrode of the fourth MOS tube is connected with the input end of the first NOT gate;

The drain electrode of the fifth MOS tube is connected with the drain electrodes of the first MOS tube and the second MOS tube, and the source electrode is connected with the drain electrode of the seventh MOS tube;

The grid electrode of the sixth MOS tube is connected with the drain electrode of the first MOS tube, the drain electrode of the second MOS tube is connected with the drain electrode of the fifth MOS tube, the drain electrode is connected with the input end of the first NOT gate, and the source electrode is connected with the drain electrode of the eighth MOS tube;

The grid electrode of the seventh MOS tube is connected with the output end of the second signal selector, and the source electrode of the seventh MOS tube is grounded;

And the grid electrode of the eighth MOS tube is connected with the output end of the first signal selector, and the source electrode of the eighth MOS tube is grounded.

Preferably, the second trigger and the fourth trigger are 2UI paths;

the second flip-flop and the fourth flip-flop are rising edge triggered.

Preferably, the third trigger and the fifth trigger are 1UI paths;

the third trigger and the fifth trigger are falling edge triggers;

and using MOS CAP as a load to compensate the delay from the CLK end to the D end of the third trigger triggered by the rising edge and the delay from the CLK end to the D end of the fifth trigger triggered by the rising edge.

A method of training a control circuit for clock signal delay, comprising:

judging whether the clock signal needs to be calibrated according to the calibration enabling signal;

when the calibration enabling signal is 1, calibrating the clock signal;

Sampling the calibration enable signal by the output signals of the first variable delay line and the second variable delay line;

the first signal selector and the second signal selector select a calibration mode to calibrate according to the sampled calibration enabling signal;

And the phase discrimination module is used for checking the calibration result.

Preferably, the first signal selector and the second signal selector select a calibration mode according to the sampled calibration enable signal to perform calibration includes:

When the output of the signal selector is 1, selecting a 1UI path, and performing 1UI calibration;

the falling edge of CLK_ NDLY samples CAL_EN, output Q2, the rising edge of CLK_DLY samples CLK_EN, and output Q4;

When the first rising edge of clk_dly precedes the first falling edge of clk_ NDLY, the rising edge of Q4 will arrive in advance of Q2, at which time the phase detector output is 0, the code of the second variable delay line increases, clk_dly is pushed until the first rising edge of clk_dly coincides with the first falling edge of clk_ NDLY, the positions of the rising edges of Q2 and Q4 are changed, the rising edge of Q4 falls behind the rising edge of Q2, the phase detector output cal_out jumps to 1, at which time the code corresponding to the second variable delay line is 1UI calibration result.

when the output of the signal selector is 0, selecting a 2UI path, and performing 2UI calibration;

The rising edge of CLK_ NDLY samples CAL_EN, outputs Q0, and when the next rising edge of CLK_ NDLY arrives, outputs Q1, Q1 and Q0 have a phase difference of 2 UI;

The rising edge of CLK_DLY samples CLK_EN and outputs Q3, when the first rising edge of CLK_DLY is earlier than the second rising edge of CLK_ NDLY, the rising edge of Q3 is earlier than Q1, the output of the phase detector is 0, the code of the second variable delay line is increased, CLK_DLY is pushed until the first rising edge of CLK_DLY coincides with the second rising edge of CLK_ NDLY, the sequence positions of the rising edges of Q1 and Q3 are changed, the rising edge of Q3 is later than the rising edge of Q1, the output of CAL_OUT of the phase detector is 1, and the code corresponding to the second variable delay line is 2UI calibration result.

The invention has the beneficial effects that 1, the invention adopts a novel 1UI/2UI calibration mode, can overcome the influence of the self setup time and the retention time of a D trigger, can obtain the delay of 1UI/2UI more accurately in the training of DDR PHY IP, 2, the invention integrates the 1UI and the 2UI calibration into one circuit, saves the circuit area and improves the operation efficiency of the circuit, 3, in the 1UI calibration path, the invention adds load capacitance adjustment to the D trigger sampled at the rising edge, and ensures the delay from CLK to Q as same as the D trigger sampled at the falling edge under the condition that CAL_OUT jumps from 0 to 1, thereby realizing accurate calibration.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.

FIG. 1 is a schematic diagram of a clock signal delay control circuit according to the present invention;

FIG. 2 is a schematic diagram of a 1UI calibration circuit according to the prior art;

FIG. 3 is a schematic diagram of a 1UI/2UI calibration circuit configuration of the invention;

FIG. 4 is a 1UI calibration timing diagram of the present invention;

FIG. 5 is a 2UI calibration timing diagram of the present invention;

FIG. 6 is a schematic diagram of a phase detection module circuit according to the present invention;

fig. 7 is a schematic circuit diagram of a rising edge and falling edge trigger D flip-flop according to the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that all directional indicators (such as up, down, left, right, front, and rear are used in the embodiments of the present invention) are merely for explaining the relative positional relationship, movement conditions, and the like between the components in a certain specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicators are changed accordingly.

Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.

The invention integrates the 1UI and 2UI calibration into one circuit, saves the circuit area and improves the running efficiency of the circuit, and in the 1UI calibration path, the invention adds load capacitance adjustment to the D trigger sampled at the rising edge, and ensures the same delay from CLK to Q as the D trigger sampled at the falling edge when CAL_OUT jumps from 0 to 1 in the training of DDR PHY IP.

Example 1

A control circuit of clock signal delay, referring to fig. 1, includes a first variable delay line, a second variable delay line, and a 1UI/2UI calibration circuit;

The 1UI/2UI calibration circuit performs calibration according to clock signals output by the first variable delay line and the second variable delay line.

The setup time and hold time of the flip-flops are two important timing parameters in the digital circuit design, ‌, which together affect the time requirement that the data be stable before and after the clock signal is triggered, ‌ to ensure that the data can be sampled and read correctly. ‌ set-up time ‌ refers to the time that ‌ data must remain stable until the rising edge of the clock signal of the flip-flop. This time interval ‌ ensures that the input signal has enough time to reach the chip, ‌, and can be sampled correctly on the clock rising edge. ‌ if the input signal does not meet the setup time requirement, ‌ data cannot be clocked into the flip-flop by the current clock, ‌, but can only be sampled on the next clock rising edge. ‌ the hold time ‌ is that after the rising edge of the clock signal of the flip-flop arrives, the ‌ data must also be kept stable for a period of time, ‌, to ensure that the data can be read stably. The importance of the ‌ hold time is that ‌ ensures that ‌ requires a certain transition time for ‌ data to transition high and low due to delay as the signal passes through wiring and logic cells inside the device, ‌ to ensure that the data remains stable for a period of time after the clock signal edge triggers, ‌ to be effectively read and converted to output. ‌ if the retention time is insufficient, ‌ data cannot be effectively read. ‌ setup time and hold time are the time requirements of the test chip between the input signal and the clock signal, ‌ they characterize the time the data needs to be input to the latch for before and after the clock edge is triggered, ‌ is a characteristic of the chip itself. A ‌ failure to meet the requirements of setup and hold times can result in the occurrence of metastable state ‌, ‌, i.e., an output value that is in an indeterminate state for a short period of time, ‌, which can affect the proper operation of the digital system. ‌ A

Due to the presence of the setup time and hold time of the flip-flop, when the signal is sampled, the setup time and hold time of the flip-flop can affect the calibration result of the clock signal, resulting in inaccurate calibration of the clock signal. The invention provides a control circuit for clock signal delay, which comprises a first variable delay line (variable delay line 1), a second variable delay line (variable delay line 2) and a 1UI/2UI calibration circuit. The clock signal CLK, the calibration enable signal cal_en, and the 1UI/2UI calibration mode selection signal MODESEL are input, and the standard signal cal_out is output as a phase detection result.

The end D of the first trigger is connected with CAL EN, the end Q is connected with the input end of the first amplifier, and the end CLK is connected with CLK NDLY;

the D end of the third trigger is connected with CAL EN, the Q end of the third trigger is connected with the 1 end of the first signal selector, and the CLK end of the third trigger is connected with CLK NDLY;

the D end of the fourth trigger is connected with CAL EN, the Q end of the fourth trigger is connected with the 0 end of the second signal selector, and the CLK end of the fourth trigger is connected with CLK DLY;

The D end of the fifth trigger is connected with CAL EN, the Q end of the fifth trigger is connected with the 1 end of the second signal selector, and the CLK end of the fifth trigger is connected with CLK DLY;

The basic block of the flip-flop includes an input block ‌ the flip-flop typically has one or more input signals, ‌ these signals may be voltage or current variations. The ‌ input signal may be continuous or ‌ may be instantaneous. ‌ logic gates ‌ input signals are processed and decoded by logic gates. ‌ logic gates may generate corresponding output signals depending on the particular conditions of the input signals. Common logic gates ‌ include and gates, ‌ or gates, ‌ not gates, and the like. ‌ feedback loop ‌ flip-flop typically contains one or more feedback loops ‌ for recording and storing past input signals. The ‌ feedback loop may hold the state of the trigger ‌ not to trigger until a particular condition is met. ‌ output signal the output signal of ‌ trigger can be level signal, and ‌ also can be pulse signal. The form and nature of the ‌ output signal depends on the type and design of the flip-flop. The ‌ flip-flop may generate an output signal ‌ to cause a corresponding operation or event in the system according to a particular input condition. ‌ different types of triggers have different application scenarios, ‌ for storing and transmitting data, for example in a digital circuit, ‌ or in a control system for detecting and responding to external events. ‌ monitor conditions ‌ the trigger will constantly monitor for specific conditions, ‌ such as specific data states, ‌ time intervals or triggering of external events. ‌ condition verifies that ‌ when the trigger detects that the condition is met, ‌ will trigger further operations. ‌ this generally involves verifying the conditions, ‌, to ensure that certain requirements are met. ‌ trigger operation ‌ once the condition is verified to be correct, the ‌ trigger will initiate the defined operation or procedure. ‌ these operations may be predefined commands, ‌ script, ‌ function, ‌ store procedure, etc., ‌ for responding to a triggering event. ‌ execute logic ‌ trigger operations corresponding logic may be executed as needed. ‌ for example, ‌ in a database, ‌ triggers can be used to automatically perform other operations when data is inserted, updated, or deleted ‌, ‌ such as updating other tables or triggering other triggers. ‌ optional feedback ‌ upon completion of the triggering operation, the ‌ trigger may choose to provide feedback to the user, ‌, for example, to display a message, log ‌ events, or trigger other notification mechanisms.

When cal_en is 1, calibration is performed, the outputs clk_dly, clk_ NDLY of the variable delay lines 1,2 sample the high level cal_en, the phase detector compares the rising edges of the sampling results Q1, Q2, Q3, Q4, the value of cal_out output by the phase detector is 0 when the rising edge of PH1 comes before PH0, and the value of cal_out output by the phase detector is 1 when the rising edge of PH1 comes later than PH 0.

Preferably, the first variable delay line is a fixed length delay line.

The delay line (DELAY LINE) is an electronic device for the transmission and processing of delay signals. The method can delay the arrival time of the input signal for a certain time and then output the signal, and is commonly used in the fields of data communication, digital signal processing, measurement and the like. A delay line is a device that is capable of delaying the arrival time of a signal. It makes it necessary for the input signal to pass through a period of time before reaching the output by introducing a specific delay element in the signal path. The delay line may implement a delay of the signal based on the principles of electromagnetic wave propagation, capacitive coupling, or clocking. The delay line mainly aims to solve the problems of signal synchronization, time sequence calibration, signal compensation, pulse shaping and the like. For example, in communication systems, delay lines are often used to ensure that the different signals arrive in the correct order at the receiving end, thereby enabling efficient data transmission. A clocked delay line is a device that uses a clock signal to synchronize and control delay. The clock pulse control method is used for timing calibration, synchronous data transmission, clock distribution and other scenes through accurate clock pulse control signal delay time. Clock controlled delay lines are widely used in digital systems, high speed communications, and chip scale integrated circuits. The variable delay line can provide accurate signal delay control, and the delay line can delay signals in a high-precision and adjustable mode so as to meet the requirements of different application scenes. The delay line can solve the problems of data dislocation and time sequence caused by inconsistent signal arrival time, and ensure the normal operation of the system. The delay line can be used for signal compensation, pulse shaping, signal waveform correction and other processes, and the system design and debugging process are simplified.

The variable delay line 1 is a delay line of fixed length (initial length) which exists to counteract the inherent delay of the variable delay line 2, the length of the variable delay line 2 being controlled by code, being adjusted from the result of CAL OUT, to be increased from the initial delay. When CAL_OUT jumps from 0 to 1, the variable delay line code at this time corresponds to a 1UI/2UI delay length, and calibration is completed. CAL_EN is a calibration enable signal, and can be calibrated when 1 is the calibration enable signal, MODESEL is a 1UI/2UI calibration mode selection signal, 1UI calibration is performed when 1 is the calibration enable signal, and 2UI calibration is performed when 0 is the calibration enable signal.

Preferably, referring to FIG. 5, the phase discrimination module comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube and a first NOT gate;

The grid electrode of the first MOS tube is connected with the output end of the second signal selector, and the drain electrode of the first MOS tube is connected with the drain electrode of the second MOS tube and the drain electrode of the fifth MOS tube;

The grid electrode of the seventh MOS tube is connected with the output end of the second signal selector, and the source electrode is grounded;

The grid electrode of the eighth MOS tube is connected with the output end of the first signal selector, and the source electrode is grounded.

The CAL_OUT output is 0 when the PH1 rising edge arrives earlier than PH0, and is 1 when the PH1 rising edge arrives later than PH 0. Ch is a kind of

The phase discrimination module can discriminate the device of the phase difference of the input signals, and the circuit enables the output voltage to have a definite relation with the phase difference between the two input signals. In the embodiment of the invention, the phase detection module can judge whether the calibration result of the calibration circuit reaches the standard, and the second variable delay line can adjust the length of the second variable delay line according to the output of the phase detection module so as to adapt to the calibration of the next clock signal.

Preferably, referring to fig. 7, the second trigger and the fourth trigger are 2UI paths;

the second flip-flop and the fourth flip-flop are rising edge triggered.

The "rising edge" refers to the instant when the signal changes from a low level to a high level. In digital circuits and communication systems, a rising edge generally represents the process of a signal state changing from 0 (low level) to 1 (high level), i.e., the beginning edge of a signal. For example, in a digital signal source, when the output signal changes from 0 to 1, a rising edge is said to occur, and a rising edge trigger refers to the instant when the signal changes from a low level (‌ V) ‌ to a high level (‌, e.g., 3.5V or more) ‌. ‌ in digital circuits, ‌ this generally represents the beginning edge of the signal state, and ‌ can trigger many logic gates and flip-flops, ‌ to perform a particular function. ‌ for example, ‌ in a digital signal source, ‌ when the output signal changes from 0 to 1, ‌ a rising edge occurs, ‌ this can be used for timing control, ‌ signal lock and data synchronization. ‌ A

Preferably, the third trigger and the fifth trigger are 1UI paths;

The third trigger and the fifth trigger are falling edge triggers;

The delay from CLK to D of the third flip-flop and the fifth flip-flop triggered by rising edge is compensated by using MOS CAP as load.

The "falling edge" refers to the instant when the signal changes from a high level to a low level. In digital circuits and communication systems, a falling edge generally represents the process of a signal state changing from 1 (high level) to 0 (low level), i.e., the ending edge of a signal. For example, in a digital signal source, when the output signal changes from 1 to 0, it is said that a falling edge occurs at this time. Rising edge triggering and falling edge triggering refer to the instantaneous change of a signal from a low level to a high level or from a high level to a low level, respectively. ‌ A

The falling edge trigger is the instant when the signal changes from high level (‌, e.g., greater than 3.5V) ‌ to low level (‌, 0.3V or less) ‌. ‌ in the digital circuit, ‌ this represents the end edge of the signal state, and ‌ can also trigger logic gates and flip-flops, ‌ to achieve a specific function. ‌ for example, ‌ when the output signal changes from 1 to 0, a falling edge ‌ occurs, and ‌ plays an important role in timing control, ‌ signal locking, data synchronization, and the like. ‌ A

In the invention, the D trigger sampled by CLK_ NDLY under the 1UI path is triggered by a falling edge, and the rest D triggers are all triggered by rising edges, and because the delay from the D trigger CLK to the D end directly influences the accuracy of 1UI/2UI calibration, the delay from the D trigger CLK to the D end triggered by the rising edge is compensated by using MOS CAP as a load under the 1UI path, so that the delay is consistent with the delay of the D trigger triggered by the falling edge, as shown in figure 7. Since the present invention focuses on the state where the Q terminal (cal_out) is changed from 0 to 1, i.e., the state where the Q1 terminal is changed from 1 to 0, this state is driven by BCLK at the falling edge, and the rising edge flip-flop is driven by ACLK, since BCLK is delayed by one inverter from ACLK, the rising edge triggered D flip-flop is compensated using MOS CAP as loading.

Example 2

A training method of a clock signal delay control circuit comprises the following steps:

step S100, judging whether the clock signal needs to be calibrated according to the calibration enabling signal;

the calibration enable signal is a control signal for enabling or disabling a particular function or operation. It typically represents an enable or disable state in the form of a high level (logic 1) or a low level (logic 0). By changing the state of the enable signal, the operating state of the corresponding module or device can be controlled. Such signals are widely used in electronic systems and digital circuits, for example, playing an important role in data storage, logic gates, clock control, and the like. The enabling signal not only helps control the system operation mode, but also saves power consumption. In practical applications, such as motor control, numerically controlled machine tools, etc., the enabling signal ensures safe operation of the device and accurate control of functions. In an embodiment of the invention, the calibration enable signal is used to turn on the calibration circuit.

Step S200, when the calibration enabling signal is1, calibrating the clock signal;

when the calibration enable signal is 1, it is explained that the current clock signal is calibrated, and the calibration circuit starts to operate.

Step S300, output signals of the first variable delay line and the second variable delay line sample the calibration enabling signal;

The first variable delay line and the second variable delay line discretize the continuous calibration enable signal in time. The continuous analog signal is converted into a discrete time series by taking the instantaneous value of the analog signal x (t) point by point at regular time intervals Δt. This is achieved by multiplying the sampling pulse with the analog signal. In short, sampling is the capturing of the value of an analog signal at a particular point in time, changing it from a continuous form to a series of separate time samples. These samples can then be used for digital signal processing and analysis.

Step S400, the first signal selector and the second signal selector select a calibration mode to calibrate according to the sampled calibration enabling signal;

in the embodiment of the invention, the calibration circuit has two calibration modes, namely a 1UI calibration mode and a 2UI calibration mode, wherein 1UI is half of a clock period, 2UI is one clock period,

And S500, checking the calibration result by the phase discrimination module.

The phase discrimination module outputs a voltage proportional to the phase difference by comparing phase information of the two input signals based on the phase comparison. This voltage is then used to adjust an oscillator or frequency synthesizer in the loop to reduce the phase difference between the input signal and the output signal, ultimately achieving frequency and phase synchronization. The demodulation principle of the phase demodulation module relates to the change of phase difference converted into the change of output voltage, in this way, the phase demodulation module realizes demodulation of the phase modulation wave, the original information is extracted, and the phase demodulation module generates output voltage proportional to the phase difference by identifying the phase difference of the input signal, so as to realize demodulation of the phase modulation wave and synchronous control of frequency and phase.

Preferably, in step S400, the first signal selector and the second signal selector select the calibration mode according to the sampled calibration enable signal to perform calibration includes:

step S410A, when the output of the signal selector is 1, selecting a 1UI path to perform 1UI calibration;

As shown in fig. 4, when MODESEL is 1, a 1UI path is selected and 1UI calibration is performed. The falling edge of CLK_ NDLY samples CAL_EN, output Q2, and the rising edge of CLK_DLY samples CLK_EN, output Q4. When the first rising edge of clk_dly precedes the first falling edge of clk_ NDLY, the rising edge of Q4 will arrive in advance of Q2, the output of the phase discriminator is 0, the code of the variable delay line 2 will be increased continuously, and clk_dly is pushed until the first rising edge of clk_dly coincides with the first falling edge of clk_ NDLY, the positions of the rising edges of Q2 and Q4 are changed, the rising edge of Q4 will arrive after Q2, the output of the phase discriminator jumps to cal_out to 1, and the code corresponding to the variable delay line 2 is 1UI calibration result.

Step S410B, when the output of the signal selector is 0, selecting a 2UI path for 2UI calibration;

As shown in fig. 5, when MODESEL is 0, a 2UI path is selected and 2UI calibration is performed. As shown in fig. 4, the rising edge of clk_ NDLY samples cal_en, outputs Q0, and outputs Q1, Q1 and Q0 when the next rising edge of clk_ NDLY arrives, with a phase difference of 2 UI. The rising edge of CLK_DLY samples CLK_EN and outputs Q3, when the first rising edge of CLK_DLY is earlier than the second rising edge of CLK_ NDLY, the rising edge of Q3 is earlier than Q1, the output of the phase detector is 0, the code of the variable delay line 2 is increased, CLK_DLY is pushed until the first rising edge of CLK_DLY coincides with the second rising edge of CLK_ NDLY, the positions of the rising edges of Q1 and Q3 are changed, the rising edge of Q3 is later than the rising edge of Q1, the output of the phase detector is CAL_OUT and is 1, and the code corresponding to the variable delay line 2 is a 2UI calibration result.

The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A control circuit for clock signal delay is characterized by comprising a first variable delay line, a second variable delay line and a 1UI/2UI calibration circuit;

The 1UI/2UI calibration circuit calibrates according to clock signals output by the first variable delay line and the second variable delay line;

The 1UI/2UI calibration circuit comprises a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, a first amplifier, a first signal selector, a second signal selector and a phase discrimination module;

The D end of the first trigger is connected with the CAL EN, the Q end of the first trigger is connected with the input end of the first amplifier, and the CLK end of the first trigger is connected with a signal (CLK NDLY) generated after a clock CLK passes through a first variable delay line of an initial code;

The D end of the second trigger is connected with the output end of the first amplifier, the Q end of the second trigger is connected with the 0 end of the first signal selector, and the CLK end of the second trigger is connected with a signal (CLK NDLY) generated after a clock CLK passes through a first variable delay line of an initial code;

the D end of the third trigger is connected with CAL EN, the Q end of the third trigger is connected with the 1 end of the first signal selector, and the CLK end of the third trigger is connected with a signal (CLK NDLY) generated after a clock CLK passes through a first variable delay line of an initial code;

The D end of the fourth trigger is connected with CAL EN, the Q end of the fourth trigger is connected with the 0 end of the second signal selector, and the CLK end of the fourth trigger is connected with a signal (CLK DLY) generated after a second variable delay line of the code of which the clock CLK is adjusted;

The D end of the fifth trigger is connected with CAL EN, the Q end of the fifth trigger is connected with the 1 end of the second signal selector, and the CLK end of the fifth trigger is connected with a signal (CLK DLY) generated after a second variable delay line of the code of which the clock CLK is adjusted;

2. The control circuit of claim 1, wherein the first variable delay line is a fixed length delay line.

3. A clock signal delay control circuit as recited in claim 1, wherein the length of the second variable delay line is adjusted in accordance with the output of the calibration circuit.

4. The control circuit of clock signal delay of claim 1, wherein the phase discrimination module comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube and a first NOT gate;

5. The control circuit of claim 1, wherein the second flip-flop and the fourth flip-flop are 2UI paths;

the second flip-flop and the fourth flip-flop are rising edge triggered.

6. The control circuit of claim 1, wherein the third flip-flop and the fifth flip-flop are 1UI paths;

the third trigger and the fifth trigger are falling edge triggers;

7. A training method of a clock signal delay control circuit, applied to a clock signal delay control circuit according to any one of claims 1 to 6, comprising:

when the calibration enabling signal is 1, calibrating the clock signal;

8. The method of training a clock signal delay control circuit of claim 7, wherein the first signal selector and the second signal selector select a calibration mode for calibration based on the sampled calibration enable signal comprises:

the falling edge of CLK_ NDLY samples the calibration enable signal (CAL_EN), output Q2, and the rising edge of CLK_DLY samples the calibration enable signal (CAL_EN), output Q4;

9. The method of training a clock signal delay control circuit of claim 7, wherein the first signal selector and the second signal selector select a calibration mode for calibration based on the sampled calibration enable signal comprises:

the rising edge of clk_ NDLY samples the calibration enable signal (cal_en), outputs Q0, and when the next rising edge of clk_ NDLY arrives, there is a phase difference of 2UI between Q1, Q1 and Q0;

The rising edge of CLK_DLY samples the calibration enabling signal (CAL_EN) and outputs Q3, when the first rising edge of CLK_DLY is earlier than the second rising edge of CLK_ NDLY, the rising edge of Q3 will arrive in advance of Q1, the output of the phase detector is 0 at this moment, the code of the second variable delay line increases, CLK_DLY is pushed until the first rising edge of CLK_DLY coincides with the second rising edge of CLK_ NDLY, the sequence positions of the rising edges of Q1 and Q3 are changed, the rising edge of Q3 will arrive later than Q1, the phase detector output CAL_OUT jumps to 1, and the code corresponding to the second variable delay line is the 2UI calibration result at this moment.