CN116707521A - 8.1Gbps eDP high-speed display interface receiving end clock data recovery key circuit system - Google Patents

Abstract

The invention discloses a key circuit system for recovering clock data at a receiving end of an 8.1Gbps eDP high-speed display interface, belonging to the field of high-speed communication, and synchronizing an 8.1Gbps input signal into parallel data through a sampling synchronization module. Afterwards, the phase detector and the majority voter compare the phases of the parallel data and the sampling clock to generate a phase error signal. The phase error signal passes through the digital filter and the data shaper to filter out the high-frequency noise jitter, and finally forms the phase adjustment signal in the phase accumulator. The phase adjustment signal is transmitted to the phase interpolation module to adjust the phase of the sampling clock and realize the closed loop of the system. In the system structure of the present invention, the phase detector has a simple structure and has low power consumption and area, and at the same time, the data shaper can improve data accuracy, effectively suppress system oscillation, and increase system robustness.

Description

For 8.1Gbps eDP high-speed display interface receiving end clock data recovery key circuit road system

technical field

The invention relates to the technical field of high-speed communication, in particular to a key circuit system for clock data recovery of a receiving end of an 8.1Gbps eDP high-speed display interface.

Background technique

As ultra-high-definition video display technology requires higher and higher data transmission rates, traditional data interfaces cannot meet the display requirements of high-definition panels. Therefore, the Video Electronics Standards Association (VESA) has formulated a new embedded display interface (eDP) specification. Its architecture includes 4 main transmission channels, each channel has a transmission rate of up to 8.1Gbps, and the total effective data rate can reach 25.92Gbps.

Although the eDP display interface specification has increased the data transmission rate, in high-frequency data transmission scenarios, the signal rising edge time is shortened and the amplitude is reduced, resulting in the high-frequency effect of the signal dominating. Therefore, Serdes high-speed link design technology needs to be adopted to solve the signal integrity challenges faced by high-speed eDP interfaces. In the long-distance transmission scenario, in order to further reduce the joint influence of channel crosstalk, PVT and other environmental noise on the clock signal and data signal, the high-speed link mainly adopts a serial asynchronous architecture.

Compared with the parallel synchronous architecture, the serial asynchronous architecture has the advantages of not needing to consider the synchronization between parallel data and having low complexity. However, the serial asynchronous architecture has only a single data channel and no independent clock channel. During transmission, the data signal and the clock signal are sent together. Due to the lack of clock information corresponding to the data, the receiver needs a clock data recovery circuit (CDR) to recover the clock from the received signal and reconstruct the original data stream.

Since the eDP protocol is designed for the display environment with a built-in battery, it consumes less power than other types of interfaces, which puts forward low power consumption design requirements for CDR. At the same time, the protocol standard requires higher noise tolerance and frequency tolerance. Under the above-mentioned technical challenges, it is necessary to combine the protocol standard and redesign the circuit system to solve the above problems.

Contents of the invention

The invention provides an 8.1Gbps eDP high-speed display interface receiving terminal clock data recovery key circuit system, which is suitable for various index requirements of the eDP version 1.5 protocol. The system circuit has a phase detector with small area and low power consumption, which is more suitable for the eDP protocol interface with low power consumption. At the same time, the data shaper in the system can improve data accuracy, quickly suppress system oscillation, increase system robustness, and shorten system lock time.

The embodiment of the present invention provides a key circuit system for clock data recovery of the receiving end of the 8.1Gbps eDP high-speed display interface, including: a sampling synchronization module, the input terminal of the sampling synchronization module is connected to the input serial signal, and is used to connect the 8.1Gbps The input signal is synchronized as parallel data;

A phase detector, the input end of the phase detector is connected to the output end of the sampling synchronization module, and is used to judge the phase relationship between the sampling clock and the data bit according to the parallel data, and adjust the sampling according to the phase relationship output Multiple lead and lag signals for clock phase;

A majority voter, the input end of the majority voter is connected to the output end of the phase detector, and is used to judge a plurality of leading and lagging signal samples generated by the phase detector, and output a phase error signal;

A digital filter, the input end of the digital filter is connected to the output end of the majority voter, and is used to perform proportional and integral operations on the phase error signal output by the majority voter, through the proportional path data and the integral path data Finally add to obtain the output data of the digital filter;

A data shaper, the input end of the data shaper is connected to the output end of the digital filter, which is used to compress the output data of the digital filter, reduce the jump range of the output data value, and convert the amplitude information For the duty cycle information, the high-pass filter is used to shape the quantization noise and filter out the low-frequency part;

A phase accumulator, the input end of the phase accumulator is connected to the output end of the data shaper, and the output end is connected to the input end of the phase interpolation module, which is used to record the phase-adjusted information according to the output data of the data shaper , and output a phase adjustment signal corresponding to the data bit width according to the accuracy of the phase interpolation module;

The phase interpolation module, the output terminal of the phase interpolation module is connected to the other input terminal of the sampling synchronization module, and is used to adjust the phase of the sampling clock of the sampling synchronization module according to the phase adjustment signal;

A verification module, the input end of the verification module is connected to the other output end of the sampling synchronization module, and the output end outputs a verification signal and output data, which are used to verify the output data of the sampling synchronization module and determine the system Whether to self-adaptively converge, and verify the bit error rate index according to the verification signal.

Optionally, in one embodiment of the present invention, the sampling synchronization module is further configured to adopt a 1/2 rate oversampling scheme, using two edge sampling clocks and two data sampling clocks to collect synchronous edge bit information respectively and data bit information.

Optionally, in an embodiment of the present invention, the decision formula for the phase detector to judge the phase relationship between the sampling clock and the data bits according to the parallel data is:

Among them, E0 is the information collected by the first edge sampling clock, E1 is the information collected by the second edge sampling clock, D0 is the information collected by the first data sampling clock, Indicates an XOR operation, and the phase detector performs logic operations on a group of adjacent data bit information and edge bit information, and outputs "advance" and "lag" information of the sampling clock phase.

Optionally, in an embodiment of the present invention, the decision calculation formula of the majority voter is:

Among them, up _i means that the i-th data phase detection is a leading signal, dn _i means that the i-th data phase detection is a lagging signal, up _sig means that the number of leading signals in k sets of data is more than the number of lagging signals, and dn _sig means k sets of data The number of lagging signals is more than the number of leading signals, and up_dn is the output value of the majority voter. The first stage of the majority voter will count the number of k leading and lagging signals respectively. The second stage compares the numbers of the two signals. If k When the number of leading signals in the group data is more than the number of lagging signals, the majority voter outputs a leading signal; otherwise, it outputs a lagging signal. When the number of leading signals is equal to the number of lagging signals, the majority of voting devices output no action signal , which means no phase adjustment.

Optionally, in an embodiment of the present invention, the digital filter is further used to perform operations on the output data of the majority voter through a proportional path and an integral path respectively, and the proportional path shifts the data to the left with a signed bit , to achieve power-of-two amplification; the integral path sums the data at each clock cycle, and shifts the summed data to the right with a signed bit to achieve power-of-two reduction, and the proportional path data and integral path data are signed The addition operation of the numbers is used to obtain the output data of the digital filter.

Optionally, in one embodiment of the present invention, the phase interpolation module provides four-phase sampling clocks, the period of the sampling clocks is one-half of the period of the serial data, and each phase difference between the four-phase sampling clocks is fixed by Π /2 phase.

Optionally, in one embodiment of the present invention, the verification module is further configured to randomly take the continuous 32-bit serial data at the input end, and fill them into the 0-31 bit registers sequentially after 32 clocks, and the current verification Circuit 1+X ²⁸ +X ³¹ generates subsequent correct data, and then XORs the generated data with the sampled data, observes the XOR result, and determines whether the current sampled data is correct, and X represents the nth bit of the shift register.

The embodiment of the present invention is oriented to the 8.1Gbps eDP high-speed display interface receiving end clock data recovery key circuit system, which has the following beneficial effects:

1. The phase detector has lower power consumption and area.

2. A data shaper is introduced to change the output data structure of the digital filter, compress the amplitude, and improve the precision of the output data of the digital filter.

3. In the circuit implementation stage, the design method is optimized for the problem of large system loop delay, so as to improve the frequency tolerance of CDR.

Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and easy to understand from the following description of the embodiments in conjunction with the accompanying drawings, wherein:

Fig. 1 is a kind of oriented 8.1Gbps eDP high-speed display interface receiving end clock data recovery key circuit system structural diagram provided according to the embodiment of the present invention;

2 is a block diagram of the hardware structure of a key circuit system for clock data recovery at the receiving end of an 8.1Gbps eDP high-speed display interface provided according to an embodiment of the present invention;

3 is a schematic diagram of the execution process of a key circuit system for clock data recovery at the receiving end of an 8.1Gbps eDP high-speed display interface provided according to an embodiment of the present invention;

4 is a schematic diagram of a four-phase sampling clock of a sampling synchronization module according to an embodiment of the present invention;

5 is an equivalent circuit diagram of a data shaper according to an embodiment of the present invention;

Fig. 6 is a working flow diagram of a phase accumulator according to an embodiment of the present invention;

7 is a schematic diagram of a phase interpolator generating a four-phase sampling clock according to an embodiment of the present invention;

FIG. 8 is a diagram of a noise tolerance performance test of the present invention according to an embodiment of the present invention.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

FIG. 1 is a schematic structural diagram of a key circuit system for clock data recovery at a receiving end of an 8.1 Gbps eDP high-speed display interface according to an embodiment of the present invention.

As shown in Figure 1, the key circuit system for clock data recovery at the receiving end of the 8.1Gbps eDP high-speed display interface includes: an oversampling synchronization module 100, a phase detector 200, a majority voter 300, a digital filter 400, a data shaper 500, a phase accumulator 600 , phase interpolation module 700 and verification module 800 .

The input terminal of the sampling synchronization module 100 is connected to the input serial signal, and is used to synchronize the input signal of 8.1Gbps into parallel data;

The input terminal of the phase detector 200 is connected to the output terminal of the sampling synchronization module 100, and is used to judge the phase relationship between the sampling clock and the data bit according to the parallel data, and adjust multiple advances and lags of the sampling clock phase according to the phase relationship output Signal;

The input terminal of the majority voter 300 is connected with the output terminal of the phase detector 200, and is used for judging a plurality of leading and lagging signal samples generated by the phase detector, and outputting a phase error signal;

The input terminal of the digital filter 400 is connected to the output terminal of the majority voter 300, and is used to perform proportional and integral operations on the phase error signal output by the majority voter, and the final sum of the proportional path data and the integral path data is obtained by the digital filter. Output Data;

The input end of the data shaper 500 is connected with the output end of the digital filter 400, and is used for compressing the output data of the digital filter, reducing the jump range of the output data value, converting the amplitude information into duty cycle information, and passing through the high-pass The filter shapes the quantization noise and filters out the low frequency part;

The input terminal of the phase accumulator 600 is connected to the output terminal of the data shaper 500, and the output terminal is connected to the input terminal of the phase interpolation module 700, which is used to record the phase-adjusted information according to the output data of the data shaper, and interpolate according to the phase The accuracy of the module, output the phase adjustment signal of the corresponding data bit width;

The output terminal of the phase interpolation module 700 is connected to the other input terminal of the sampling synchronization module 100, and is used to adjust the phase of the sampling clock of the sampling synchronization module according to the phase adjustment signal;

The input end of the verification module 800 is connected with another output end of the sampling synchronization module 100, and the output end outputs a verification signal and output data for checking the output data of the sampling synchronization module 100 to determine whether the system is adaptively convergent, and according to Check the signal to verify the bit error rate indicator.

Based on the above modules, the input signal with a rate of 8.1Gbps is synchronized into parallel data through the sampling synchronization module; the phase detector judges the phase relationship between the sampling clock and the data bit according to the parallel data, and outputs the signal to adjust the phase of the sampling clock according to the phase relationship "Lead" and "lag" signals; the majority voter combines multiple samples of the "lead" and "lag" signals produced by the phase detector to output a result with greater confidence; a digital filter scales and sums the output of the majority voter Integral operation, the proportional path data and the integral path data are finally added to obtain the output data of the digital filter; the data shaper compresses the data output by the digital filter, reduces the jump range of its value, and converts the amplitude information into a duty cycle At the same time, the high-pass filter is used to shape the quantization noise and filter out the low-frequency part; the phase accumulator continuously accumulates the output data of the data shaper, records the information after phase adjustment, and outputs the phase of the corresponding data bit width according to the accuracy of the phase interpolation module Adjust the signal; the phase difference module adjusts the phase of the sampling clock according to the phase adjustment signal, tracks the change of the data at the receiving end, and finally realizes the correct collection of the data at the receiving end. The verification module completes the verification of the data output by the sampling synchronization module to indicate whether the current system is adaptively converged and is in a stable working state. At the same time, according to the output signal of the verification module, the bit error rate index can be verified.

In the embodiment of the present invention, the sampling synchronization module 100 adopts a 1/2 rate oversampling scheme, and uses two edge sampling clocks and two data sampling clocks to collect synchronization edge bit information and data bit information respectively.

In an embodiment of the present invention, the phase detector judges the phase relationship between the sampling clock and the data bit according to the parallel data as follows:

Among them, E0 is the information collected by the first edge sampling clock, E1 is the information collected by the second edge sampling clock, D0 is the information collected by the first data sampling clock, Indicates an exclusive OR operation. The phase detector performs logical operations on a group of adjacent data bit information and edge bit information, and outputs the "advanced" and "lag" information of the sampling clock phase.

In an embodiment of the present invention, the judgment calculation formula of the majority voter is:

Among them, up _i means that the phase detection of the i-th data is an advanced signal, dn _i means that the phase detection of the i-th data is a lagging signal, up _sig means that the number of leading signals in k sets of data is more than that of lagging signals, and dn _sig means k sets of data The number of lagging signals is more than the number of leading signals, and up_dn is the output value of the majority voter. The first stage of the majority voter will count the number of k leading and lagging signals respectively. The second stage compares the numbers of the two signals. If k When the number of leading signals in the group data is more than the number of lagging signals, the majority of voters output a leading signal, otherwise, they output a lagging signal. No phasing is done.

In the embodiment of the present invention, as shown in FIG. 2 , the digital filter 400 is further used to perform operations on the output data of the majority voter through the proportional path and the integral path respectively, and the proportional path shifts the data to the left with a signed bit to realize The power of 2 is enlarged; the integral path sums the data in each clock cycle, and the signed bit of the summed data is shifted to the right to realize the power of 2 reduction, and the proportional path data and the integral path data are signed. Addition operation to obtain the output data of the digital filter.

The specific calculation process of the digital filter 400 is as follows: the input is an m-bit X signal and the feedback m-bit signal is added to obtain an m+1-bit quantizer input signal V, and the most significant bit (MSB) can be used to complete 1 bit quantification process. The remaining m-bit signal, which represents the negative value of the quantization error signal, is stored in a register with a bit width of m, and is added to the m-bit input signal X in the next clock cycle. The digital filter changes the output data structure of the digital filter and compresses the amplitude. On the premise of not losing data information, the amplitude of the phase adjustment signal is reduced, and the precision of the output data of the digital digital filter is improved.

In the embodiment of the present invention, the phase interpolation module 700 provides four-phase sampling clocks, the period of the sampling clock is half of the period of the serial data, and the phase difference between the four-phase sampling clocks is fixed by Π/2.

In the embodiment of the present invention, the verification module 800 is further used to randomly take the continuous 32-bit serial data at the input end, and fill them into the 0-31 bit registers sequentially after 32 clocks. The current verification circuit 1+X ²⁸ + X ³¹ generates follow-up correct data, and then performs XOR processing on the generated data and sampled data, observes the XOR result, and determines whether the current sampled data is correct, and X represents the nth bit of the shift register.

Specifically, it can be seen from the PRBS signal generation principle of 1+X ²⁸ +X ³¹ pattern that the output data depends on the XOR result of the 28th bit and the 31st bit, and because the PRBS generation circuit is a cyclic structure, the 28th bit The XOR result of the bit and the 31st bit is also used as the input of the 0th bit register, so the generation of the subsequent data stream depends on the data stored in the 0-31 bit register. Therefore, the principle of the verification circuit is obvious, that is, as long as any continuous 32-bit data generated logically correctly is taken from the generated cyclic data, and filled into the 0-31 bit registers in turn after 32 clocks, the current circuit can generate follow-up correct data. At this time, XOR processing is performed on the generated data and the sampled data, and the XOR result is observed to know whether the current sampled data is correct.

In the circuit realization stage, the present invention analyzes the critical path. Since each of the three parts of the digital filter, the data shaper and the phase accumulator contains a summation circuit, there will be a register beating and registering data in the summation circuit. The structure, that is, the path from the register of the digital filter to the register of the phase accumulation circuit is called the critical path. Timing analysis is performed on the setup time and hold time of the critical path. After comprehensively considering the rationality of the algorithm performance and timing, the summation logic of the data shaper is placed on the feedback branch to obtain the maximum index improvement.

The working principle of the method of the present invention is as follows: the sampling synchronization module collects 8.1Gbps serial data through the four-phase sampling clock, which is divided into two types of data bit information and edge bit information, and is synchronized into parallel data respectively. The phase detector generates phase error signals "lead" and "lag" by performing logical operations on the data bit information and edge bit information. The majority voter compresses the parallel phase error signal, and selects the result with the highest confidence to output. Afterwards, the digital filter and data shaper perform low-pass filtering on the output data of the majority voter, and shape and filter out high-frequency noise, and at the same time realize the learning and accumulation of frequency difference. Finally, a phase adjustment signal is formed in the phase accumulator and transmitted to the phase interpolation module to adjust the phase of the sampling clock to realize a closed-loop system. The circuit system has the function of self-adaptive adjustment. At the initial stage of system startup, even if the phase of the sampling clock is not at the ideal time, under the self-adaptive adjustment of the circuit system, the system gradually converges and tends to be stable, and the phase of the sampling clock gradually tends to the signal Where the eye opening is largest, that is, where the bit error rate of the signal is lowest.

Apply the above key circuit system of clock data recovery to the 8.1Gbps eDP high-speed display interface, the algorithm flow is shown in Figure 3, including the following steps:

(1) The sampling synchronization module uses four-phase sampling clocks with fixed phase differences of Π/2 to sample the input 8.1Gbps serial data, as shown in FIG. 4 . In one cycle, two data bit information and two edge bit information can be sampled. However, in order to reduce the operating frequency of the core circuit, the data is reshaped synchronously, and is synchronized into 9-bit edge bit information and 8-bit data bit information respectively. The edge bit information is one bit more than the data bit information, which means that whether there is a transition edge between adjacent bits can be obtained through XOR logic, and the phase information is judged only when there is transition edge information .

(2) The phase detector performs logical operations on the 9-bit edge bit information and 8-bit data bit information, and the decision relationship between every two bits of data is shown in formula (1).

Two groups of 8-bit wide information indicating phase "advance" and "lag" are respectively obtained, and each bit represents the relationship between the current bit and the phase of the sampling clock.

(3) At this time, the majority voter is also designed to be 8-bit wide, and will count the number of two groups of 8-bit wide "advanced" and "lag" information respectively, and after passing through the comparator, the information with the largest number will be output. The information represents the final phase error relationship.

(4) After the digital filter receives the signal output by the majority of voters, it is processed by the proportional path and the integral path. The proportional path amplifies the data by 8 times through the signed left shift operation, and the integral path reduces the data by 32 through the signed right shift operation. times. The signed shift operation is divided into two cases: when operating on a positive number, the shift can be performed directly, while when operating on a negative number, it is necessary to perform bit expansion first, then take the complement code and then perform the shift operation, and finally perform the shift operation on the negative number The shifted data is complemented again to obtain the negative number after the operation. The integration path accumulates the data after an operation every clock cycle and saves it in the register file, continuously providing frequency difference components to promote phase adjustment. The data of the proportional path and the integral path are added to obtain the final output result of the digital filter.

(5) The threshold of the data shaper is designed to be 1/16. At the circuit design level, the bit width of the data shaper is 4 bits. Therefore, it is only necessary to intercept the data higher than 4 bits in the final output result of the digital filter as output As a result, the remaining lower 4 bits continue to participate in the operation of the accumulation circuit in the data shaper, as shown in FIG. 5 . X[n] is the input data of the data shaper, Y[n] is the output data, and m is 4 in the present invention.

(6) The phase accumulator is designed to be 1/64 according to the accuracy of the phase interpolation module, so the output data range of the phase accumulator is 0-63. For the positive and negative values of the phase adjustment information, the workflow of the phase accumulator is as follows As shown in Figure 6, when there is a frequency difference, the phase adjustment information will continue to be adjusted in one direction. If the phase adjustment information is positive, the output value of the phase accumulator will be updated to 0 when it increases from 0 to the maximum value of 64. If the phase adjustment information is a negative value, when the output value of the phase accumulator decreases from 63 to the minimum value of 0, it is updated to 63.

(7) When there is a positive frequency difference between the transmitting end and the receiving end, when the output of the phase accumulator increases regularly from 0 to the maximum value of 63, the positive phase offset between clk_out and ref_clk reaches the maximum value of 1UI (123ps), which When the clk_out clock is switched to ref_clk inversion, as shown in Figure 6. When there is a negative frequency difference between the sending end and the receiving end, when the output of the phase accumulator regularly decreases from 63 to the minimum value of 0, the negative phase offset between clk_out and ref_clk reaches a maximum value of 1UI (123ps), and the clk_out clock switches It is inverted for ref_clk, and the four-phase sampling clock is generated with clk_out as the reference clock.

Based on the above algorithm flow, the circuit of the present invention forms a negative feedback system, and after the system is started, it can realize self-adaptive adjustment to track frequency difference and noise.

In order to verify the actual effect of the solution provided by the present invention, theoretical analysis and circuit simulation experiments are respectively carried out on the system of the present invention, and the noise tolerance (JTOL) data shown in FIG. 8 is obtained. The uppermost broken line in Figure 8 is the circuit simulation data, the middle curve is the theoretical analysis result, and the bottom dotted line is the 8.1Gbps eDP protocol standard. The circuit simulation data is similar to the theoretical analysis result, representing the rationality of this design, and both are high Based on the protocol standard, it represents the effectiveness of this design.

At the same time, compared with the two documents in recent years, the present invention has certain advantages in terms of noise tolerance and frequency difference index. The document "A2.68mW/Gbps, 1.62-8.1Gb/s Receiver for Embedded DisplayPortVersion1.4b to Support14dB Channel Loss" is based on the actual measurement after tape-out of the 10nm process, the noise margin is 0.45UIpp@10MHz, and the frequency difference is 1500ppm. The literature "A Clock Data Recovery Circuit with Adaptive Adjustment of Loop Bandwidth" is based on the simulation test of the 55nm process, and the noise margin is 0.55UIpp@10MHz. The present invention is based on the simulation test of 40nm process, 0.74UIpp@10MHz, and the frequency difference is 1800ppm. The details are shown in the table below.

To sum up, the present invention provides a design method and system for a key circuit for clock data recovery at the receiving end of an 8.1Gbps eDP high-speed display interface, which has obvious advantages compared with the prior art.

The embodiment of the present invention is oriented to the 8.1Gbps eDP high-speed display interface receiving end clock data recovery key circuit system, and the 8.1Gbps input signal is synchronized into parallel data through the sampling synchronization module. Afterwards, the phase detector and the majority voter compare the phases of the parallel data and the sampling clock to generate a phase error signal. The phase error signal passes through a digital filter and a data shaper to filter out high-frequency noise and jitter, and finally forms a phase adjustment signal in a phase accumulator. The phase adjustment signal is transmitted to the phase interpolation module to adjust the phase of the sampling clock to realize the closed loop of the system. In the system structure of the present invention, the phase detector has a simple structure and has low power consumption and area, and at the same time, the data shaper can improve data accuracy, effectively suppress system oscillation, and increase system robustness.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Moreover, the described specific features, structures, materials or characteristics may be combined in any one or N embodiments or examples in an appropriate manner. In addition, those skilled in the art can combine and combine different embodiments or examples and features of different embodiments or examples described in this specification without conflicting with each other.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In the description of the present invention, "N" means at least two, such as two, three, etc., unless otherwise specifically defined.

Claims (7)

1. A key circuit system for clock data recovery at the receiving end of an 8.1Gbps eDP high-speed display interface, characterized in that it includes: A sampling synchronization module, the input terminal of the sampling synchronization module is connected to the input serial signal, and is used to synchronize the input signal of 8.1Gbps into parallel data; A phase detector, the input end of the phase detector is connected to the output end of the sampling synchronization module, and is used to judge the phase relationship between the sampling clock and the data bit according to the parallel data, and adjust the sampling according to the phase relationship output Multiple lead and lag signals for clock phase; A majority voter, the input end of the majority voter is connected to the output end of the phase detector, and is used to judge a plurality of leading and lagging signal samples generated by the phase detector, and output a phase error signal; A digital filter, the input end of the digital filter is connected to the output end of the majority voter, and is used to perform proportional and integral operations on the phase error signal output by the majority voter, through the proportional path data and the integral path data Finally add to obtain the output data of the digital filter; A data shaper, the input end of the data shaper is connected to the output end of the digital filter, which is used to compress the output data of the digital filter, reduce the jump range of the output data value, and convert the amplitude information For the duty cycle information, the high-pass filter is used to shape the quantization noise and filter out the low-frequency part; A phase accumulator, the input end of the phase accumulator is connected to the output end of the data shaper, and the output end is connected to the input end of the phase interpolation module, which is used to record the phase-adjusted information according to the output data of the data shaper , and output a phase adjustment signal corresponding to the data bit width according to the accuracy of the phase interpolation module; The phase interpolation module, the output terminal of the phase interpolation module is connected to the other input terminal of the sampling synchronization module, and is used to adjust the phase of the sampling clock of the sampling synchronization module according to the phase adjustment signal; A verification module, the input end of the verification module is connected to the other output end of the sampling synchronization module, and the output end outputs a verification signal and output data, which are used to verify the output data of the sampling synchronization module and determine the system Whether to self-adaptively converge, and verify the bit error rate index according to the verification signal. 2. The system according to claim 1, wherein the sampling synchronization module is further used to adopt a 1/2 rate oversampling scheme, using two edge sampling clocks and two data sampling clocks to collect synchronous edges respectively bit information and data bit information. 3. The system according to claim 1, wherein the phase detector judges the phase relationship between the sampling clock and the data bits according to the parallel data as follows: Among them, E0 is the information collected by the first edge sampling clock, E1 is the information collected by the second edge sampling clock, D0 is the information collected by the first data sampling clock, Indicates an XOR operation, and the phase detector performs logic operations on a group of adjacent data bit information and edge bit information, and outputs "advance" and "lag" information of the sampling clock phase. 4. system according to claim 1, is characterized in that, the judgment calculation formula of described majority voter is: Among them, up _i means that the i-th data phase detection is a leading signal, dn _i means that the i-th data phase detection is a lagging signal, up _sig means that the number of leading signals in k sets of data is more than the number of lagging signals, and dn _sig means k sets of data The number of lagging signals is more than the number of leading signals, and up_dn is the output value of the majority voter. The first stage of the majority voter will count the number of k leading and lagging signals respectively. The second stage compares the numbers of the two signals. If k When the number of leading signals in the group data is more than the number of lagging signals, the majority voter outputs a leading signal; otherwise, it outputs a lagging signal. When the number of leading signals is equal to the number of lagging signals, the majority of voting devices output no action signal , which means no phase adjustment. 5. The system according to claim 1, wherein the digital filter is further used for, the output data of the majority voter is calculated through the proportional path and the integral path respectively, and the proportional path carries out the data with sign bit Shift to the left to achieve power-of-two amplification; the integral path sums the data at each clock cycle, and shifts the summed data to the right with a signed bit to realize power-of-two reduction, and the proportional path data and the integral path data are The addition operation of signed numbers is used to obtain the output data of the digital filter. 6. The system according to claim 1, wherein the phase interpolation module provides a four-phase sampling clock, the sampling clock period is 1/2 of the serial data period, and each phase difference between the four-phase sampling clocks is fixed Π/2 phase of . 7. The system according to claim 1, wherein the verification module is further used to randomly take the continuous 32-bit serial data at the input end, and fill in the 0-31 bit registers sequentially after 32 clocks, The current inspection circuit 1+X ²⁸ +X ³¹ generates subsequent correct data, and then performs XOR processing on the generated data and the sampled data, observes the XOR result, and determines whether the current sampled data is correct, where X represents the first n bits.