CN106936531A - A kind of multi-disc is based on the synchronous method of JESD204B agreements ADC - Google Patents

Abstract

The invention discloses a multi-chip synchronization method based on the JESD204B protocol ADC. By adjusting the SYSREF (system reference) signal, it first ensures that the SYSREF signal and the sampling clock DCLK_ADC of the _ADC meet the best setup time and hold time, and then Adjust the local multi-frame cycle delay at the receiving end, that is, the time interval T _RXLMFC from the SYSREF signal to the rising edge of the LMFC (local multi-frame clock), so that the worst link can achieve deterministic delay, ensuring that multiple ADCs based on the JESD204B protocol Synchronization, thereby ensuring that multiple ADCs are synchronized when the power is repeated or the link is re-established.

Description

A method for synchronizing multiple ADCs based on JESD204B protocol

technical field

The invention belongs to the technical field of signal sampling, and more specifically relates to a method for synchronizing multi-chip ADCs based on the JESD204B protocol.

Background technique

The JESD204B serial transmission protocol (referred to as the JESD204B protocol) is an important interface standard in ADC transmission. Compared with the traditional parallel LVDS interface standard, it has the advantages of fast speed and less IO pins, and is gradually being adopted by major ADC manufacturers. favor.

The sending end of the JESD204B protocol, that is, the ADC and the receiving end are divided into a transport layer, a data link layer and a physical layer. The highest link rate is 12.5Gb/s. On the whole, the sampling data (such as 12bit, 8bit, etc.) is packaged into serial data after 8B/10B encoding at the sending end, serially transmitted to the receiving end, deserialized, decoded and then restored to the original sampling at the receiving end data.

Although the JESD204B protocol has great advantages such as fast speed and less occupied IO pins, the uncertain delay in the link has greatly hindered the synchronization of multiple ADCs based on the JESD204B protocol, and the time-alternating sampling system ( TIADC systems) and other applications present obstacles. The uncertain delay is reflected in the process of link re-establishment or power-on again. Under the JESD204B protocol, the receiving end cannot receive data at a certain point in time or at the edge of a certain local multi-frame clock cycle, which makes the delay of the link significant. non-repeatability.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies of the prior art, and propose a multi-chip synchronization method based on the JESD204B protocol ADC to achieve deterministic delay.

In order to realize the above-mentioned purpose of the invention, the synchronous method of multichip of the present invention based on JESD204B agreement ADC is characterized in that, comprises the following steps:

(1) In a data acquisition system built with multiple ADCs based on the JESD204B protocol, an FPGA as a sampling data receiver, and a clock management module capable of generating SYSREF (system reference) signals, the clock management module is adjusted to produce ADC samples that meet the requirements The clock DCLK_ADC is input to each _ADC respectively, and the FPGA reference clock DCLK_FPGA that meets the requirements is generated and input to each _FPGA . At the same time, the clock management module inputs the SYSREF signal generated by it to each ADC and each FPGA;

(2), Configure the registers of each _ADC , and make the establishment time window of the received SYSREF signal relative to the sampling clock DCLK_ADC greater than the time threshold T1, and keep the time window greater than the time threshold T2. The time threshold T1 and the time threshold T2 are based on the specific The ADC chip is determined;

(3), adjust the internal register of the clock management module through the serial SPI protocol, set the initial analog delay value of the SYSREF signal to 0, and generate a single SYSREF signal;

(4), read the value of the set-up time error flag register and the hold time error flag register of each ADC;

(5) For any ADC, if at least one of the setup time error flag register and the hold time error flag register is not "0" (that is, "1"), the setup time error flag register and the setup time error flag register and Keep the time error flag register cleared, then increase the SYSREF signal analog delay value, and adjust the internal register of the clock management module through the serial SPI protocol, reset the analog delay value of the SYSREF signal, regenerate a single SYSREF signal, and return to the step ( 4);

If the values of the setup time error flag register and the hold time error flag register are both "0", it indicates that the setup time and hold time of the SYSREF signal and the _ADC sampling clock DCLK_ADC are satisfied, then jump to step (6);

(6) Calculate the time interval T _RXLMFC from the SYSREF signal to the rising edge of the LMFC (local multi-frame clock) in the receiving end, that is, the FPGA, so that there is an N value and satisfy the following formula at the same time:

(T _TXOUT +T _WIRE(max) +T _RXIN ( _max ))＜((N+1)×T _LMFC -T _TXLMFC +T _RXLMFC )

(T _TXOUT +T _WIRE(min) +T _RXIN(min) )＞(N×T _LMFC -T _TXLMFC +T _RXLMFC )

Among them, T _TXOUT is the time interval from the rising edge of the LMFC in the ADC at the transmitting end to the serial data output, and T _WIRE(max) and T _WIRE(min) are the maximum and maximum line delays from the ADC to the FPGA at the receiving end, respectively. The minimum value, T _RXIN(max) and T _RXIN(min) are the maximum and minimum values of the time interval from the receiving end, that is, the serial data received by the FPGA to the rising edge of LMFC, respectively, T _LMFC is the period of the local multi-frame clock, and T _TXLMFC is The sending end is the time interval between the SYSREF signal in the ADC and the rising edge of the LMFC;

(7), the time interval T _RXLMFC that step (6) obtains is sent to the LMFC delay register in the receiving end FPGA, has thus just guaranteed the deterministic delay of link, and then realized the synchronism of many slices based on JESD204B agreement ADC.

The purpose of the present invention is achieved like this.

The multi-chip synchronization method of the ADC based on the JESD204B protocol of the present invention, through the adjustment of the SYSREF (system reference) signal, it first ensures that the sampling clock DCLK_ADC of the SYSREF signal and the _ADC meets the best setup time and hold time, and then adjusts the local The multi-frame cycle delay is the time interval T _RXLMFC from the SYSREF signal to the rising edge of the LMFC (local multi-frame clock), so that the worst link can achieve deterministic delay, ensuring the synchronization of multiple ADCs based on the JESD204B protocol, thereby ensuring In order to synchronize multiple ADCs when power is repeated or the link is re-established.

Description of drawings

Fig. 1 is the functional block diagram of the data acquisition system built based on the JESD204B protocol ADC in multiple slices in the present invention;

Figure 2 is a diagram of the uncertainty delay at the receiving end;

Fig. 3 is a waveform diagram of sampling data mosaicing for ADC synchronous validity verification, wherein (a) is a waveform diagram of sampling data mosaic error, and (b) is a waveform diagram of sampling data mosaicing correctly.

detailed description

Specific embodiments of the present invention will be described below in conjunction with the accompanying drawings, so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when detailed descriptions of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

Fig. 1 is a functional block diagram of a multi-chip data acquisition system constructed based on the JESD204B protocol ADC in the present invention.

In the present embodiment, as shown in Figure 1, the data acquisition system built based on the JESD204B protocol ADC in the present invention is composed of multiple chips based on the JESD204B protocol ADC, an FPGA as a sampling data receiving end, and a SYSREF (system reference) signal capable of producing The clock management module construction.

In this embodiment, as shown in Figure 1, a data acquisition system is constructed by two ADCs whose model is AD9625, two FPGAs whose model is kintex-7, and a phase-locked loop chip whose model is LMK04828. The sending end of the data acquisition system, the FPGA as the receiving end of the data acquisition system, the phase-locked loop chip as the clock management module, and one FPGA corresponds to one ADC.

In the present embodiment, the multi-chip synchronization method of the present invention based on the JESD204B protocol ADC includes the following steps:

Step S1: Adjust the clock management module to generate the ADC sampling clock DCLK_ _ADC that meets the requirements and input them to each ADC, and generate the FPGA reference clock DCLK_ _FPGA that meets the requirements and input it to each FPGA. At the same time, the clock management module generates the SYSREF The signal is input to each piece of ADC and each piece of FPGA;

Step S2, configure the registers of each slice ADC, and make the receiving SYSREF signal greater than the time threshold T1 with respect to the setup time window of the sampling clock _{DCLK_ADC} , keep the time window greater than the time threshold T2, in the present embodiment, the time threshold T1 is 150ps, time threshold T2 is 100ps;

In this embodiment, the AD9625 is first configured through the SPI protocol, and the setup time window register and the hold time window register are 0x13C[7:5] and 0x13B[7:5] registers respectively. Their step is 35ps, then send 5 to the 0x13C[7:5] register, and send 3 to the 0x13B[7:5] register.

Step S3: adjust the internal register of the PLL chip through the serial SPI protocol, set the initial analog delay value of the SYSREF signal to 0, and generate a single SYSREF signal;

In this embodiment, the initial analog delays of the SYSREF signals of ADC1 and ADC2 are adjusted to be 0, and then the registers of the PLL chip are adjusted to generate a single SYSREF signal.

S4. Read back the values of the setup time error flag register and the hold time error flag register of the ADC to see if they are "0".

In this embodiment, the setup time error flag register and the hold time error flag register are 0x100[3] and 0x100[2] respectively, which represent whether the setup time window and the hold time window of the SYSREF signal and the sampling clock DCLK_ADC of the _ADC are greater than When the values set in step S2 are read for the first time, the values of the registers 0x100[3] and 0x100[2] are respectively read back and found to be "1".

Step S5: For any ADC, if at least one of the setup time error flag register and the hold time error flag register is not "0" (i.e. "1"), set the setup time error flag register and the hold time through the corresponding clearing method of the ADC Clear the error flag register, then increase the analog delay value of the SYSREF signal, and adjust the internal register of the clock management module through the serial SPI protocol, reset the analog delay value of the SYSREF signal, regenerate a single SYSREF signal, and return to step S4;

If the values of the setup time error flag register and the hold time error flag register are both "0", it indicates that the setup time and hold time of the SYSREF signal and the _ADC sampling clock DCLK_ADC are satisfied, then jump to step S6.

In this embodiment, set register 0x03A[6] to "0", set to "1" and then set to "0" to clear 0x100[3] and 0x100[2].

In this embodiment, the delay value of the SYSREF signal is adjusted to 180 ps, and a single SYSREF signal is regenerated. It is found that the values of 0x100[3] and 0x100[2] are both stable as "0", indicating that the setup time and hold time of the SYSREF signal and the _ADC sampling clock DCLK_ADC have been satisfied.

Step S6: Calculate the time interval T _RXLMFC from the SYSREF signal to the rising edge of the LMFC (local multi-frame clock) in the receiving end, that is, the FPGA, so that there is an N value and satisfy the following formula simultaneously:

(T _TXOUT +T _WIRE(max) +T _RXIN(max) )＜((N+1)×T _LMFC -T _TXLMFC +T _RXLMFC )

(T _TXOUT +T _WIRE(min) +T _RXIN(min) )＞(N×T _LMFC -T _TXLMFC +T _RXLMFC )

Among them, T _TXOUT is the time interval from the rising edge of the LMFC in the ADC at the transmitting end to the serial data output, and T _WIRE(max) and T _WIRE(min) are the maximum and maximum line delays from the ADC to the FPGA at the receiving end, respectively. The minimum value, T _RXIN(max) and T _RXIN(min) are the maximum and minimum values of the time interval from the receiving end, that is, the serial data received by the FPGA to the rising edge of LMFC, respectively, T _LMFC is the period of the local multi-frame clock, and T _TXLMFC is The sending end is the time interval between the SYSREF signal in the ADC and the rising edge of the LMFC.

In this embodiment, T _TXOUT is 6 frame periods, T _WIRE(min) is 0 frame periods, T _WIRE(max) is 0 frame periods, T _RXIN(max) and T _RXIN(min) are 92 frame periods and 84 frame periods, T _LMFC is 32 frame periods, T _TXLMFC is 0 frame periods, T _RXLMFC incremental value is selected as 0 at first, then T _RXLMFC is just 28 frame periods (in this embodiment, T The increase value of _RXLMFC is 4 times of the increase value of T _RXLMFC , and T _RXLMFC is increased on the basis of 28), at this time, a satisfying N value cannot be obtained at the same time.

Increase the incremental value corresponding to T _RXLMFC to 5, then T _RXLMFC becomes 28+5*4=48 frame periods, and bring the value into it again to obtain the N value of 1, which meets the requirements.

Step S7: Send the incremental value corresponding to the time interval T _RXLMFC obtained in step S6 to the LMFC delay register in the FPGA of the receiving end, so as to ensure the deterministic delay of the link, and then realize the synchronization of multiple ADCs based on the JESD204B protocol.

In this embodiment, the incremental value of T _RXLMFC is 5 (the corresponding value of T _RXLMFC is 48 frame periods), and 5 is sent to the LMFC delay register 0x010[11:8] in two FPGAs, thus ensuring the chain The deterministic delay of the road realizes the synchronization of two ADCs based on the JESD204B protocol.

simulation

1. Verify the deterministic delay of the receiving end

It is proved that the present invention realizes the deterministic delay by the moment value of the sampling data received by the receiving end. Before using this method, the receiving end, that is, the moment when the FPGA starts to receive the sampled data may be one of the two situations in Figure 2, that is, the moment when the received sampled data starts is uncertain with the power-on, and sometimes it is as early as Sometimes later, the delay of the link is uncertain.

After using the present invention, after repeated power-on and repeated tests, the obtained result is always a situation in Fig. 2, which proves that the present invention realizes deterministic delay.

2. Verify the effectiveness of ADC synchronization.

Adjust the phase-locked loop chip so that the sampling clock at the front end of ADC2 lags behind the sampling clock at the front end of ADC1 by 200ps. If the two ADCs are stable and synchronized, the two ADCs can form a time-alternating sampling system with a sampling rate of 5GSPS. The effectiveness of ADC synchronization is proved by whether the data of the two ADCs can be stably merged.

When the SYSREF signal does not adopt the present invention, combining the sampling data of two ADCs will result in the situation in Figure 3(a) or Figure 3(b), and the generation of these two situations is random as the power is turned on. The fundamental reason is that the SYSREF signal is in the metastable region of the ADC sampling clock, causing the SYSREF signal to point to the previous ADC sampling cycle at some point and point to the next sampling cycle at some point, which is uncertain.

After using the present invention, it is ensured that the setup time and the hold time of SYSREF have a time window, no metastable state occurs, and through continuous repeated power-on and testing, the data of the two ADCs can be stably assembled into Fig. 3 (b )form. The form in Figure 3(b) is also the reason why the sampling clocks of the two ADCs at the front end have a certain phase difference. The obtained stable time-alternating sampling system proves the effectiveness of the synchronization of the two ADCs.

Although the illustrative specific embodiments of the present invention have been described above, so that those skilled in the art can understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, As long as various changes are within the spirit and scope of the present invention defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concept of the present invention are included in the protection list.

Claims (2)

1. a multi-chip synchronous method based on JESD204B protocol ADC, is characterized in that, comprises the following steps: (1) In a data acquisition system built with multiple ADCs based on the JESD204B protocol, an FPGA as a sampling data receiver, and a clock management module capable of generating SYSREF (system reference) signals, the clock management module is adjusted to produce ADC samples that meet the requirements The clock DCLK_ADC is input to each _ADC respectively, and the FPGA reference clock DCLK_FPGA that meets the requirements is generated and input to each _FPGA . At the same time, the clock management module inputs the SYSREF signal generated by it to each ADC and each FPGA; (2), Configure the registers of each _ADC , and make the establishment time window of the received SYSREF signal relative to the sampling clock DCLK_ADC greater than the time threshold T1, and keep the time window greater than the time threshold T2. The time threshold T1 and the time threshold T2 are based on the specific The ADC chip is determined; (3), adjust the internal register of the clock management module through the serial SPI protocol, set the initial analog delay value of the SYSREF signal to 0, and generate a single SYSREF signal; (4), read the value of the set-up time error flag register and the hold time error flag register of each ADC; (5) For any ADC, if at least one of the setup time error flag register and the hold time error flag register is not "0" (that is, "1"), the setup time error flag register and the setup time error flag register and Keep the time error flag register cleared, then increase the SYSREF signal analog delay value, and adjust the internal register of the clock management module through the serial SPI protocol, reset the analog delay value of the SYSREF signal, regenerate a single SYSREF signal, and return to the step ( 4); If the values of the setup time error flag register and the hold time error flag register are both "0", it indicates that the setup time and hold time of the SYSREF signal and the _ADC sampling clock DCLK_ADC are satisfied, then jump to step (6); (6) Calculate the time interval T _RXLMFC from the SYSREF signal to the rising edge of the LMFC (local multi-frame clock) in the receiving end, that is, the FPGA, so that there is an N value and satisfy the following formula at the same time: (T _TXOUT +T _WIRE(max) +T _RXIN ( _max ))＜((N+1)×T _LMFC -T _TXLMFC +T _RXLMFC ) (T _TXOUT +T _WIRE(min) +T _RXIN(min) )＞(N×T _LMFC -T _TXLMFC +T _RXLMFC ) Among them, T _TXOUT is the time interval from the rising edge of the LMFC in the ADC at the transmitting end to the serial data output, and T _WIRE(max) and T _WIRE(min) are the maximum and maximum line delays from the ADC to the FPGA at the receiving end, respectively. The minimum value, T _RXIN(max) and T _RXIN(min) are the maximum and minimum values of the time interval from the receiving end, that is, the serial data received by the FPGA to the rising edge of LMFC, respectively, T _LMFC is the period of the local multi-frame clock, and T _TXLMFC is The sending end is the time interval between the SYSREF signal in the ADC and the rising edge of the LMFC; (7), the incremental value corresponding to the time interval T _RXLMFC obtained in step (6) is sent to the LMFC delay register in the receiving end FPGA, so that the deterministic delay of the link is guaranteed, and then multiple chips based on the JESD204B protocol ADC are realized synchronization. 2. The synchronization method according to claim 1, characterized in that the time threshold T1=150 ps and the time threshold T2=100 ps in step (2).