JP3581584B2 - Delay amount correction circuit, ATM exchange, and delay amount correction method - Google Patents

Description

例えば、遅延分解能Ｄｉ＝１００［ｐｓ］、セットアップとホールド時間の和ｓｅｔｕｐ＋ｈｏｌｄ＝４００［ｐｓ］とすると、遅延精度Ｄａ＝５００［ｐｓ］となる。
【００３２】
以上のように、本発明によれば、遅延回路の遅延量を簡易なディジタル回路で補正することにより遅延変動の少ない遅延回路をＣＭＯＳゲートアレイで実現できる。これにより高速伝送が可能になる。
【００３３】
つぎに、本発明にかかる第２の実施の形態を、図７を用いて説明する。第２の実施の形態においては、図１で示した遅延補正構成のうち、遅延手段の一つを固定遅延３７とした構成としている。第１の実施の形態で示した様に、位相検出手段３５、補正・制御手段３６によって、遅延手段３３、固定遅延３７の出力すなわち位相検出手段３５に入力されるクロックの位相は、遅延される前の位相に対して、データ周期分だけ遅れた位相に制御される。
【００３４】
図１において、同じ遅延量の遅延手段を２段使用した場合には、１段目の遅延手段３３出力の位相は、データ周期の半分だけ遅れた位相となるが、図７に示す構成では、固定遅延３７の遅延量によって１段目出力の位相をあらかじめ定めた位相に決めておくことができる。
【００３５】
つぎに、本発明にかかる第３の実施の形態を、図８を用いて説明する。第３の実施の形態においては、図８に示すように、受信側ＬＳＩ１２において、データ入力側に遅延手段３８を備えた構成としている。この構成においても、第１の実施の形態と同様に、位相検出手段３５の入力におけるクロックの位相をデータの周期分遅らせる様に遅延量の制御を行なう。遅延手段３８ではデータ周期の半分の遅延量となるため、クロックに対してデータの位相を遅らせてフリップフロップ７でデータ取り込みを行なうことができる。
【００３６】
以上の様に、遅延回路出力の位相を位相検出手段３５で検出し、補正・制御手段にて常に一定の遅延量となるように制御を行なうことで、フリップフロップ７に入力されるデータとクロックの位相関係を調整することができる。
【００３７】
つぎに、本発明にかかる第４の実施の形態を、図１０を用いて説明する。図１０は、第１〜３の実施の形態における遅延量補正回路を利用して、高速データ伝送を可能にしたＡＴＭ交換機の構成図を示している。前述したようにＡＴＭ交換機では、高速、広帯域ＩＳＤＮへ対応するために装置の大容量化が求められている。
【００３８】
以下、ＡＴＭ交換機の動作を説明する。まず、複数のＡＴＭ端末３２は、音声、映像等の情報を、セルと呼ばれる固定長５３バイトのデータのかたまりに分割して送信する。各ＡＴＭ端末３２からのセルは、回線対応部３１を介して回線ユニットからスイッチのユニットに伝送される。スイッチのユニットでは、セル内部の宛先ヘッダ情報に基づき専用ハードウェアで高速にスイッチング（交換）する。これを自己ルーティングと呼ぶ。交換されたセルは、元の情報に組み立てられ宛て先のＡＴＭ端末に受信される。
【００３９】
ＡＴＭ交換機の装置内において、ＬＳＩ間のデータ伝送は、基板、バックボード、ケーブルを使用した伝送線路５を介して行う。個々の回線を大容量化するには、データを並列に伝送し並列データ本数を増やせばよいが、装置規模の増大及び、ＬＳＩ、基板、バックボードのピン数不足の問題がある。そのため、データ線当たりの伝送速度を高速化し、さらにパラレル／シリアル変換回路２５を用いてシリアルデータ伝送を行いデータ信号本数を低減する。シリアル変換されたデータは高速伝送が要求され、このシリアル伝送の伝送速度が、個々の回線の大容量化を決定する。
【００４０】
また、大容量化に加えて装置の小型化が求められており、装置の小型化にはＬＳＩ当たりの回路規模が必須であるため、高集積可能なＣＭＯＳゲートアレイを用いる。
【００４１】
上記実施の形態で示した様に、遅延変動量の少ない遅延回路の補正方式によって、タイミングマージンを拡大できるためＣＭＯＳ ＬＳＩでの高速データ伝送が実現でき、これによりＡＴＭ交換機の大容量且つ小型化が実現できる。
【００４２】
【発明の効果】
本発明によれば、プロセス、温度・電源変動の影響による遅延量の変動を低減できるため、受信側におけるタイミングマージンを拡大させ、ＣＭＯＳゲートアレイで高速データ伝送が可能になる。
【００４３】
また、 遅延回路及び補正回路を、アナログ素子などを使用することなく、簡易なディジタル回路で実現でき、高集積可能なＣＭＯＳゲートアレイで高速伝送が実現でき、これにより大容量で且つ小型化したＡＴＭ交換機が実現できる。
【図面の簡単な説明】
【図１】本発明の実施の形態に係る遅延補正方式の構成図である。
【図２】本発明の実施の形態の係る動作概要を示すタイミングチャートである。
【図３】本発明の実施の形態に係る遅延補正方式の回路構成図である。
【図４】本発明の実施の形態に係る遅延回路の構成例である。
【図５】本発明の実施の形態に係るカウンタの回路構成例である。
【図６】本発明の実施の形態に係る制御回路の回路構成例である。
【図７】本発明の実施の形態に係る固定遅延を使用した遅延補正方式の構成図である。
【図８】本発明の実施の形態に係るデータ遅延量を補正する補正方式の構成図である。
【図９】本発明の実施の形態に係る分周クロック並送方式の構成図である。
【図１０】本発明の実施の形態に係るＡＴＭ交換機の構成図である。
【図１１】従来の伝送方式の構成図である。
【符号の説明】
１…送信側最終段フリップフロップ、２…２分周回路、３…出力バッファ、４…送信側ＬＳＩ、５…伝送線路、６…入力バッファ、７…受信側初段フリップフロップ、８…差動バッファ、９、１０…可変遅延回路、１１…補正回路、１２…受信側ＬＳＩ、１３…比較器、１４…カウンタ、１５…ＥＯＲ論理、１６…ＡＮＤ論理、１７…制御回路、１８…ＣＭＯＳゲート、１９…セレクタ、２０…遅延素子、２１…フリップフロップ、２２…ＯＲ論理、２３…レジスタ、２４…シリアル／パラレル変換回路、２５…パラレル／シリアル変換回路、２６…入出力ＬＳＩ、２７…ＡＴＭ ＳＷ ＬＳＩ、２８…内部論理、２９…ＳＷ部、３０…遅延回路、３１…回線対応部、３２…ＡＴＭ端末、３３、３４、３８…遅延手段、３５…位相検出手段、３６…補正・制御手段、３７…固定遅延。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to timing adjustment in high-speed transmission of digital data, and more particularly to a circuit for correcting an amount of delay in an ATM switch or the like.
[0002]
[Prior art]
2. Description of the Related Art As a conventional technique, there is a technique disclosed in "Digital transmission path test system and digital transmission path test system" in JP-A-7-15405.
[0003]
Hereinafter, this technique will be described. FIG. 11 shows a conventional transmission system. FIG. 11 shows a transmission system in which a clock is transmitted in parallel with data from the transmission side.
[0004]
Hereinafter, the operation and the circuit configuration will be described. In the transmission-side LSI 4 shown in FIG. 11, data (DATA) from the internal logic synchronized with the frame signal is retimed by the clock (CLK) in the last-stage flip-flop 1. The retimed clock and data are output via the output buffer 3 and transmitted through the transmission line 5 to be input to the receiving LSI 12. Here, when the change point of the input data and the rising change point (rising edge) of the clock have the same phase, the receiving LSI needs to adjust the clock phase in order to capture the data. That is, the clock is delayed to a phase that can be captured by the delay element 20, and the data is captured.
[0005]
[Problems to be solved by the invention]
With the development of high-speed and broadband networks, demand for high-speed and wideband ISDN (Integrated Services Digital Network) is expanding. In an ATM (Asynchronous Transfer Mode) switching system that enables high-speed and wideband ISDN, it is essential to increase the capacity of an ATM switch that switches signals from a plurality of ATM terminals.
[0006]
In order to increase the capacity of the device and to reduce the size of the device without increasing the size of the device, it is essential to increase the logical scale per LSI applied to the device. For that purpose, it is necessary to configure a device by applying a CMOS LSI which can be highly integrated.
[0007]
In addition, since the ATM exchange has a different clock source for each unit, data transmission between units generally uses a method of transmitting clocks in parallel. At this time, the data is transmitted by converting the data from parallel to serial (parallel / serial) due to a shortage of pins of the LSI, the board, and the backboard. High-speed transmission is required for serial-converted data transmission. For example, when the number of pins is reduced by a 4: 1 parallel / serial conversion circuit, the transmission speed of serial data is required to be four times that of parallel data. For this reason, in the ATM exchange, high-speed transmission using a CMOS gate array capable of high integration is a problem in realizing the device.
[0008]
Factors that limit the transmission speed include skew due to differences in wiring length, data pattern-dependent jitter, waveform degradation in the transmission line, and fluctuations in the delay amount of the delay element 20. These factors reduce the timing margin.
[0009]
In the configuration of the above-mentioned conventional example, there is a method of using a CMOS gate as a delay element to realize the delay element 20 for delaying the phase of the clock with a CMOS gate array. However, the CMOS gate is affected by process, temperature and power supply fluctuation. However, there is a problem that the amount of delay varies greatly. As a result, the timing margin of the receiving flip-flop is reduced, so that the transmission speed is limited to about several tens Mbit / s.
Accordingly, it is an object of the present invention to provide a delay amount correction circuit, an ATM switch, and a delay amount correction method for reducing the fluctuation of the delay amount.
[0010]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention provides a first delay unit for delaying an input digital signal, a second delay unit for delaying a digital signal delayed by the first delay unit, Correction means for changing a delay amount of the first delay means when a phase difference between the input digital signal and the digital signal delayed by the second delay means is not a predetermined phase difference; Output means for outputting the digital signal delayed by the first delay means. For example, when correcting the delay amounts of the first and second delay means so as to be the same, the digital signal output from the output means and the digital signal delayed by the first delay means are compared with each other in advance. Control can be performed so that the phase difference is half of the determined phase difference. For example, when the input digital signal is a clock, the signal is corrected to a signal that rises at an intermediate position between a change point of the clock signal and the next change point. Thus, the delay amount can be corrected according to the fluctuating phase difference, and the fluctuation of the delay amount can be reduced.
[0011]
More specifically, the correction means includes a comparator for determining whether a phase difference between the input digital signal and the digital signal delayed by the second delay means is larger or smaller than a predetermined phase difference. When the result of the comparator indicates that the phase difference between the input digital signal and the digital signal delayed by the second delay means is larger than the predetermined phase difference, the delay amount is changed to be smaller. A control circuit for changing the delay amount so as to increase the delay amount when the phase difference is smaller than the predetermined phase difference. In this case, the correction means further includes a counter for detecting that the result of the comparator is the same result for a predetermined number of consecutive times, and the control circuit is configured to determine, by the counter, that the result of the comparator is The control of the change of the delay amount may be executed when it is detected that the delay has been performed a predetermined number of times. The comparator can be configured by a flip-flop.
[0012]
Further, as another solution means, a first delay means for delaying the input digital signal, a second delay means for delaying the digital signal delayed by the first delay means, and There may be provided a correction means for detecting a phase between the digital signal and the digital signal delayed by the second delay means, and for changing the delay amount according to statistics of the detected phase.
[0013]
These delay amount correction circuits can be used for timing adjustment of a clock or the like in high-speed transmission of an ATM switch or the like.
[0014]
According to the present invention, it is possible to realize a delay amount correction circuit for reducing fluctuations in delay amount, and to realize a large-capacity and high-speed device by enabling high-integration and high-speed signal transmission. Can be.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a first embodiment according to the present invention will be described with reference to FIGS.
[0016]
First, a data transmission method to which the present invention is applied will be described with reference to FIG. As shown in FIG. 9, data transmission between LSIs is a clock parallel transmission system in which a clock is transmitted in parallel with data to be transmitted. Here, as the clocks to be transmitted in parallel, the frequency-divided clocks having a period of デ ー タ of the data change period are transmitted in parallel by the divide-by-2 circuit 2. This is because the normal clock is NRZ (Not Return to Zero) and the data is NZ (Return to Zero), so the clock frequency is twice the data frequency. Therefore, the transmission line 5 needs a frequency band twice as fast as the data transmission speed. By dividing the parallel clock by two, the clock has the same frequency as the data, so that the data transmission speed can be doubled without increasing the frequency band on the transmission line 5.
[0017]
The transmitted data is input to the receiving flip-flop 7, and the divided clock that has been transmitted in parallel is input to the variable delay circuit 9. The data is taken in by the delay clock after passing through the variable delay circuit 9. As described above, since the CMOS gate has a large delay variation, the delay amount of the variable delay circuit 9 is corrected by a control signal from the correction circuit 11.
[0018]
Next, the configuration on the receiving side of the first embodiment will be described with reference to FIG. FIG. 1 shows the configuration of the delay amount correction circuit. The delay amount correction circuit is configured as the receiving-side LSI 12 and includes first and second delay units 33 and 34 for delaying the phase of the clock transmitted in parallel, an input digital signal, and a second delay unit 34. A phase detecting unit 35 for detecting a case where the phase difference from the delayed digital signal is not a predetermined phase difference, and a correcting / controlling unit 36 for controlling the delay amount of the delay units 33 and 34 are provided. The phase of the clock is detected using these means, and correction is performed so that the amount of delay of the clock with respect to the data becomes constant.
[0019]
Hereinafter, the configuration and operation of the delay amount correction circuit will be described with reference to FIGS. According to the correction method of the present invention, the input clock is delayed in two stages, the “H” or “L” level of the delayed clock is determined, the delay amount of the variable delay circuit is increased or decreased, and the delay amount is reduced. , The same as the data period which is a predetermined phase difference. FIG. 3 shows a circuit configuration according to the first embodiment. The delay amount correcting circuit includes a variable delay circuit 9 or 10 serving as first and second delay means, and a phase difference between an input clock and a clock delayed by the variable delay circuit 2 is determined by a predetermined phase difference. In the embodiment, a comparator 13 that determines whether the phase is larger or smaller than an opposite phase), a counter 14 that detects that the same result is repeated a predetermined number of times as a result of the comparator, and a counter, And a control circuit for changing a delay amount when the result is detected to be continuous for a predetermined number of times.
[0020]
Next, a circuit configuration for each function will be described.
[0021]
The variable delay circuits 9 and 10 have a gate switching type configuration. FIG. 4 shows the configuration of the variable delay circuits 9 and 10. 4A and 4B, a plurality of CMOS gates 18 having a small delay amount (delay) are connected in multiple stages in a cascade, and each gate output is input to a selector 19. The selector 19 varies the delay amount by selecting one of the gate outputs according to a switching signal from the control circuit 17. In the present embodiment, the delay amounts of the variable delay circuits 9 and 10 are controlled to be the same.
[0022]
The comparator 13 shown in FIG. 3 is composed of a flip-flop, uses the input clock as a data input, performs retiming with the delayed clock after passing through the variable delay circuits 9 and 10, and determines the phase based on the output level of the flip-flop. I do. The comparator 13 determines that the phase of the input clock is not opposite to the phase of the delayed clock after passing through the variable delay circuits 9 and 10. When the output is at “H” level, the delay clock delay is small. When the output is at “L” level, it is determined that the delay amount of the delay clock is large.
[0023]
The output of the comparator 13 is input to a counter 14 provided for each of the positive and negative outputs. . FIG. 5 shows the configuration of the 2-bit counter. When re-timing near the data change point in the comparator 13, when the phase is reversed, the flip-flop output may become an indefinite output (metastable). In this state, there is a possibility that the phase of the delay clock is erroneously determined. To prevent this, the counter 14 is provided which counts the number of times the predetermined number H or L continues. The counter 14 operates in synchronization with the input clock, counts up only when the input is at the "H" level, and sets the counter value to the initial value, that is, "00" when the input is at the "L" level. Only when the "H" level is continuously input and the counter value is "11", an overflow signal (CO signal) synchronized with the clock is output, and this overflow output is used as the determination result. Therefore, the comparator 13 outputs the determination result only when the “H” level or the “L” level (the negative output of the flip-flop is “H”) is output four times in succession.
[0024]
As a result of the above-described determination by the comparator 13 and the counter 14, if the phase of the delayed clock is delayed with respect to the input clock (the delay amount is small), an UP signal is output to increase the delay amount, and (Large delay amount) outputs a DOWN signal to reduce the delay amount. In cases other than the above, a HOLD signal indicating holding of the delay amount is output.
[0025]
Although the present embodiment is configured with a 2-bit counter, the same effect can be obtained even if the number of bits is increased due to a trade-off between the number of bits of the counter and the gate size and control time.
[0026]
FIG. 6 shows a configuration of the control circuit 17. The control circuit 17 is constituted by a shift register having the same number of registers 23 as the number of gate stages of the variable delay circuits 9 and 10, and shifts according to the result of the delay clock phase determination (UP, DOWN, and HOLD signals). All the registers 23 operate in synchronization with the input clock, and the output is input as a switching signal of the variable delay circuit. At this time, the output of each register 23 always changes by only 1 bit, thereby preventing a hazard at the time of signal switching in the variable delay circuits 9 and 10. The operation of each register is described below.
[0027]
・ Up signal input: When Qn-1 = 1 (lower order bit), set Qn = 1 (right shift)
-At the time of DOWN signal input: When Qn + 1 = 0 (upper bit), set Qn = 0 (left shift)
・ At the time of HOLD signal input: Set Qn = Qn (retain the value)
Next, the operation in the present embodiment will be described with reference to FIG. FIG. 2 is a timing chart showing an outline of the operation of the present embodiment.
[0028]
As shown in the figure, when the phase determination of the delay clock (d) and the increase / decrease of the delay amount are repeatedly performed, the phase of the delay clock (d) becomes near the falling edge of the input clock (b), that is, the phase of the input clock. Settles out of phase. The delay clock (d) has passed through the variable delay circuits 9 and 10, and if the delay amounts of the variable delay circuits 9 and 10 are the same, the phase of the output clock (c) of the variable delay circuit 9 is delayed. This is half the phase of the clock delay. That is, assuming that the data period is T, the delay amount is D ≒ (T / 2). Since the data (a) is captured by the output clock (c) of the variable delay circuit 9, the rising edge of the clock is near half the data change period T, and the data capture is performed to satisfy the setup and hold time of the flip-flop. It becomes possible.
[0029]
Hereinafter, the delay accuracy when the correction method of the present invention is used will be described.
[0030]
The delay accuracy is determined by the resolution of the variable delay circuit and the delay setting error of the correction circuit. The delay resolution is the gate delay per stage, and the delay setting error is the sum of the setup and hold time of the flip-flop of the comparator. Assuming that the delay resolution is Di and the sum of the setup and hold time of the flip-flop is (setup + hold), the delay accuracy Da can be expressed by the following equation.
[0031]
(Equation 1)

For example, if delay resolution Di = 100 [ps] and sum of setup and hold time setup + hold = 400 [ps], delay accuracy Da = 500 [ps].
[0032]
As described above, according to the present invention, a delay circuit with small delay variation can be realized by a CMOS gate array by correcting the delay amount of the delay circuit with a simple digital circuit. This enables high-speed transmission.
[0033]
Next, a second embodiment according to the present invention will be described with reference to FIG. In the second embodiment, one of the delay units in the delay correction configuration shown in FIG. As described in the first embodiment, the output of the delay means 33 and the fixed delay 37, that is, the phase of the clock input to the phase detection means 35 is delayed by the phase detection means 35 and the correction / control means 36. The phase is controlled to be delayed by the data period from the previous phase.
[0034]
In FIG. 1, when two stages of delay units having the same delay amount are used, the phase of the output of the delay unit 33 in the first stage is a phase delayed by half the data period, but in the configuration shown in FIG. The phase of the first-stage output can be determined to a predetermined phase according to the delay amount of the fixed delay 37.
[0035]
Next, a third embodiment according to the present invention will be described with reference to FIG. In the third embodiment, as shown in FIG. 8, the receiving LSI 12 has a configuration in which a delay unit 38 is provided on the data input side. Also in this configuration, similarly to the first embodiment, the amount of delay is controlled so that the phase of the clock at the input of the phase detection means 35 is delayed by the period of the data. Since the delay means 38 has a delay amount that is half the data period, the data phase can be delayed with respect to the clock so that the flip-flop 7 can take in the data.
[0036]
As described above, the phase of the output of the delay circuit is detected by the phase detection means 35, and the control is performed by the correction / control means so as to always provide a constant delay amount. Can be adjusted.
[0037]
Next, a fourth embodiment according to the present invention will be described with reference to FIG. FIG. 10 is a configuration diagram of an ATM switch that enables high-speed data transmission by using the delay amount correction circuits according to the first to third embodiments. As described above, the ATM exchange is required to have a large capacity in order to cope with high-speed and wideband ISDN.
[0038]
Hereinafter, the operation of the ATM exchange will be described. First, the plurality of ATM terminals 32 divide information such as audio and video into data blocks each having a fixed length of 53 bytes and are called cells. The cell from each ATM terminal 32 is transmitted from the line unit to the switch unit via the line corresponding unit 31. The switch unit performs high-speed switching (exchange) with dedicated hardware based on destination header information inside the cell. This is called self-routing. The exchanged cells are assembled into the original information and received by the destination ATM terminal.
[0039]
In the device of the ATM exchange, data transmission between LSIs is performed via a transmission line 5 using a board, a backboard, and a cable. In order to increase the capacity of each line, data may be transmitted in parallel to increase the number of parallel data. However, there are problems such as an increase in the scale of the device and an insufficient number of pins of the LSI, the board, and the backboard. Therefore, the transmission speed per data line is increased, and serial data transmission is performed using the parallel / serial conversion circuit 25 to reduce the number of data signals. High-speed transmission is required for serial-converted data, and the transmission speed of this serial transmission determines the increase in the capacity of each line.
[0040]
Further, in addition to the increase in capacity, there is a demand for downsizing of the device. Since the circuit size per LSI is indispensable for downsizing of the device, a CMOS gate array capable of high integration is used.
[0041]
As described in the above embodiment, the timing margin can be expanded by the correction method of the delay circuit having a small amount of delay variation, so that high-speed data transmission by the CMOS LSI can be realized, thereby increasing the capacity and miniaturization of the ATM switch. realizable.
[0042]
【The invention's effect】
According to the present invention, the fluctuation of the delay amount due to the influence of the process, the temperature, and the power supply can be reduced, so that the timing margin on the receiving side can be expanded and high-speed data transmission can be performed by the CMOS gate array.
[0043]
Further, the delay circuit and the correction circuit can be realized by a simple digital circuit without using an analog element or the like, and high-speed transmission can be realized by a highly-integrated CMOS gate array. An exchange can be realized.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a delay correction method according to an embodiment of the present invention.
FIG. 2 is a timing chart showing an operation outline according to the embodiment of the present invention.
FIG. 3 is a circuit configuration diagram of a delay correction method according to the embodiment of the present invention.
FIG. 4 is a configuration example of a delay circuit according to an embodiment of the present invention.
FIG. 5 is a circuit configuration example of a counter according to the embodiment of the present invention.
FIG. 6 is a circuit configuration example of a control circuit according to an embodiment of the present invention.
FIG. 7 is a configuration diagram of a delay correction method using a fixed delay according to the embodiment of the present invention.
FIG. 8 is a configuration diagram of a correction method for correcting a data delay amount according to the embodiment of the present invention.
FIG. 9 is a configuration diagram of a divided clock parallel transmission system according to the embodiment of the present invention.
FIG. 10 is a configuration diagram of an ATM exchange according to an embodiment of the present invention.
FIG. 11 is a configuration diagram of a conventional transmission system.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Last stage flip-flop on transmission side, 2 ... Divide-by-2 circuit, 3 ... Output buffer, 4 ... LSI on transmission side, 5 ... Transmission line, 6 ... Input buffer, 7 ... First stage flip-flop on reception side, 8 ... Differential buffer , 9, 10 ... variable delay circuit, 11 ... correction circuit, 12 ... receiving LSI, 13 ... comparator, 14 ... counter, 15 ... EOR logic, 16 ... AND logic, 17 ... control circuit, 18 ... CMOS gate, 19 .. Selector, 20 delay element, 21 flip-flop, 22 OR logic, 23 register, 24 serial / parallel converter, 25 parallel / serial converter, 26 input / output LSI, 27 ATM SW LSI, 28 internal logic, 29 SW section, 30 delay circuit, 31 line correspondence section, 32 ATM terminal, 33, 34, 38 delay means, 35 phase detection means, 3 ... correction and control means, 37 ... fixed delay.

Claims (6)

First delay means for delaying an input digital signal;
Second delay means for delaying the digital signal delayed by the first delay means;
Correction means for changing a delay amount of the first delay means when a phase difference between the input digital signal and the digital signal delayed by the second delay means is not a predetermined phase difference; ,
Output means for outputting a digital signal delayed by said first delay means,
The delay amount correction circuit , wherein the correction unit further changes a delay amount of the second delay unit . First delay means for delaying an input digital signal;
Second delay means for delaying the digital signal delayed by the first delay means;
Correction means for changing a delay amount of the first delay means when a phase difference between the input digital signal and the digital signal delayed by the second delay means is not a predetermined phase difference; ,
Output means for outputting a digital signal delayed by said first delay means,
The correction means,
A comparator for determining whether a phase difference between the input digital signal and the digital signal delayed by the second delay means is larger or smaller than a predetermined phase difference;
As a result of the comparator, when the phase difference between the input digital signal and the digital signal delayed by the second delay means is larger than the predetermined phase difference, the delay amount is changed to be small. A control circuit for changing the delay amount so as to increase the delay amount when the phase difference is smaller than the predetermined phase difference . 2. The delay amount correction circuit according to claim 1 ,
A comparator for determining whether a phase difference between the input digital signal and the digital signal delayed by the second delay unit is larger or smaller than a predetermined phase difference;
As a result of the comparator, when the phase difference between the input digital signal and the digital signal delayed by the second delay means is larger than the predetermined phase difference, the delay amount is changed to be small. A control circuit for changing the delay amount so as to increase the delay amount when the phase difference is smaller than the predetermined phase difference. First delay means for delaying an input digital signal;
Second delay means for delaying the digital signal delayed by the first delay means;
Correction means for changing a delay amount of the first delay means when a phase difference between the input digital signal and the digital signal delayed by the second delay means is not a predetermined phase difference; ,
Output means for outputting a digital signal delayed by said first delay means,
A comparator for determining whether a phase difference between the input digital signal and the digital signal delayed by the second delay means is larger or smaller than a predetermined phase difference; and As a result, a counter for detecting that the same result is repeated a predetermined number of times is provided,
When the counter detects that the result of the comparator has continued for a predetermined number of times, the phase difference between the input digital signal and the digital signal delayed by the second delay unit is determined by the counter. When the phase difference is larger than the predetermined phase difference, the control circuit changes the delay amount so as to decrease, and when the phase difference is smaller than the predetermined phase difference, the control circuit changes the delay amount so as to increase. delay correction circuit according to claim <br/> that. 2. The delay amount correction circuit according to claim 1 ,
A comparator for determining whether a phase difference between the input digital signal and the digital signal delayed by the second delay means is larger or smaller than a predetermined phase difference; and As a result, a counter for detecting that the same result is repeated a predetermined number of times is provided,
When the counter detects that the result of the comparator has continued for a predetermined number of times, the phase difference between the input digital signal and the digital signal delayed by the second delay unit is determined by the counter. When the phase difference is larger than the predetermined phase difference, the control circuit changes the delay amount so as to decrease, and when the phase difference is smaller than the predetermined phase difference, the control circuit changes the delay amount so as to increase. A delay amount correction circuit, characterized in that: The delay amount correction circuit according to claim 2, 3, 4, or 5 ,
The delay amount correction circuit, wherein the comparator is a flip-flop.

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