CN117672841B - Manufacturing method of device connection structure of silicon pillar array and device connection structure - Google Patents
Manufacturing method of device connection structure of silicon pillar array and device connection structure Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 85
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims abstract description 42
- 239000013078 crystal Substances 0.000 claims abstract description 32
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- 238000001291 vacuum drying Methods 0.000 claims abstract description 9
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- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention provides a manufacturing method of a device connection structure of a silicon column array and the device connection structure, wherein the manufacturing method comprises the following steps: s1, preparing a silicon wafer: performing preliminary cleaning and drying on the silicon wafer; s2, etching crystal orientation searching: observing the target etching crystal orientation through preliminary pre-etching of the center of the silicon wafer; s3, mask preparation: preparing a SiO 2 mask on the surface of the silicon wafer through thermal oxidation, and preparing a directional etching glue layer pattern by using a photoetching machine; s4, alkaline wet etching: immersing the target silicon wafer in a mixed solution of KOH and TMAH for etching; s5, preparing a glass protective layer: and removing the etched surface impurities, sequentially performing centrifugal washing and vacuum drying, and then pouring molten glass on the surface of the silicon wafer to protect the silicon wafer. The manufacturing method of the device connection structure of the silicon column array has the advantages of high manufacturing efficiency, good quality, high reliability and low production cost.
Description
Technical Field
The invention relates to the technical field of chip device interconnection, in particular to a manufacturing method of a device connection structure of a silicon column array and the device connection structure.
Background
In the modern technological field, the innovation of the material and process of the interconnection in the chip has become one of the most critical technical difficulties in the research and development of the current high-end chip, and the design and manufacturing process method of the device connection are the key to realize the functions of the efficient, reliable and accurate electronic device. The chip interconnection technology of the existing packaging technology mainly comprises the following four types.
1. Wire bonding: which connects metal leads on a chip with metal pins on a package substrate by using metal wires (e.g., aluminum wires or gold wires) having good electrical conductivity. 2. Flip chip bonding: in the flip chip technology, the connection between the bare chip and the substrate is not realized through a wire, but the chip is turned over and inversely mounted on the packaging substrate, and the connection is directly realized through a metal solder ball. 3. Hybrid bonding: firstly, through holes are formed by deep reactive ion etching or physical drilling, and copper is filled in an electroplating mode. And then flattening the surface by chemical mechanical polishing, and activating the surface by plasma to prepare for pre-bonding. And after the upper wafer and the lower wafer are aligned, pre-bonding is completed, and the diffusion of the bonding surface of the copper through hole is further promoted through annealing operation, so that good electrical connection is completed. 4. Through Silicon Via (TSV) bonding: the TSVs do not connect the chip to the chip using a conventional wiring method, but rather connect the chip vertically by drilling holes in the chip and filling conductive material such as metal to accommodate the electrodes. After the wafer with the TSVs is fabricated, micro bumps are formed on the top and bottom of the wafer by encapsulation, and then the bumps are connected.
However, some Xu Quexian of the above wire bonds still exist in high-density packaging and miniaturization devices, and the wire bonds cannot meet the requirement of higher interconnection density due to the limited line width. And also is unsuitable for newer devices that require high-speed operation due to their long electrical paths. Flip chip bonding requires strict process control and fine alignment operations to ensure bonding quality and reliability; at the same time, it is difficult to perform multi-chip stacking, which is disadvantageous for memory products requiring high density. Hybrid bonding, which is the key point for subsequent research and development because of its higher integration density, is capable of simultaneously achieving electrical connection and physical support, but this method is relatively complex and time-consuming, and has high production costs. Through Silicon Via (TSV) bonding the physically obtained through silicon vias have the disadvantage of low accuracy and low depth.
Disclosure of Invention
The invention provides a manufacturing method of a device connection structure of a silicon column array, and aims to solve the problems of low preparation efficiency, poor reliability, long time consumption, high production cost and poor quality of the traditional chip device connection.
The embodiment of the invention provides a manufacturing method of a device connection structure of a silicon column array, which comprises the following steps:
S1, preparing a silicon wafer: performing preliminary cleaning and drying on the silicon wafer;
s2, etching crystal orientation searching: observing the target etching crystal orientation through preliminary pre-etching of the center of the silicon wafer;
S3, mask preparation: preparing a SiO 2 mask on the surface of the silicon wafer through thermal oxidation, and preparing a directional etching glue layer pattern by using a photoetching machine;
s4, alkaline wet etching: immersing the target silicon wafer in a mixed solution of KOH and TMAH for etching;
s5, preparing a glass protective layer: and removing the etched surface impurities, sequentially performing centrifugal washing and vacuum drying, and then pouring molten glass on the surface of the silicon wafer to protect the silicon wafer.
Preferably, the S1 specifically includes: the target silicon wafer (110) is rinsed with deionized water and then vacuum dried.
Preferably, the step S2 specifically includes the following steps:
S21, uniformly spin-coating a 5um adhesive layer on the surface of the silicon wafer, and then drying and curing the adhesive layer;
S22, placing the silicon wafer of the S21 under a photoetching machine for alignment, and obtaining a square pre-etching opening at the center of the silicon wafer after exposure, development, washing and drying;
S23, soaking the silicon wafer in the mixed etching liquid of KOH and TMAH for 10min, taking out, washing and drying;
s24, placing the silicon wafer of S23 under a field emission scanning electron microscope to observe etching surface conditions, recording a positioning angle theta, and marking a target crystal orientation.
Preferably, in S22, the square pre-etched opening pattern obtained after the photolithography has a size of 1×1cm.
Preferably, in S23, after 10min in the mixed etching solution, the method further includes the following steps:
and placing the dried silicon wafer under a microscope to observe the etching surface, finding out a crystal plane vertical to the surface, marking the crystal orientation, and measuring out the angle of the target positioning angle theta.
Preferably, in S23, the mass ratio is as follows:
in the mixed etching solution, the KOH content is 30wt%, the TMAH content is 1wt%, the drying temperature is 50-90 ℃ and the drying time is 1-2 h.
Preferably, the step S3 specifically includes the following steps:
s31, placing the silicon wafer marked with the crystal orientation in an ultrafast high-temperature furnace for oxidization;
s32, spin-coating a 5um adhesive layer on the surface of the silicon wafer in the S31, and then drying and curing the adhesive layer;
S33, placing the silicon wafer in the S32 under a photoetching machine to align with the positioning mark line, and obtaining a mask pattern designed in advance after exposure, development, washing and drying;
s34, removing redundant SiO 2 outside the mask area through the BOE solution.
Preferably, in S31, the oxidation temperature is 1100 ℃, and the heating time is 2min.
Preferably, the step S4 specifically includes the following steps:
etching a vertical silicon column array on the surface by using etching liquid, immersing the target silicon wafer after the double-layer mask is prepared in an etching tank of KOH and TMAH solution, controlling the temperature to be constant at 85 ℃, continuously using ultrasonic stirring and the etching liquid circulation to ensure the uniformity of etching in each place, and fishing out and cleaning after the etching time is up;
wherein the etching time is 20min, and the ambient temperature is 27 ℃.
In a second aspect, an embodiment of the present invention provides a device connection structure, where the device connection structure is manufactured by the method for manufacturing a device connection structure of a silicon pillar array as described above.
Compared with the prior art, the invention has the beneficial effects that the silicon wafer is primarily cleaned and dried; observing the target etching crystal orientation through preliminary pre-etching of the center of the silicon wafer; preparing a SiO 2 mask on the surface of the silicon wafer through thermal oxidation, and preparing a directional etching glue layer pattern by using a photoetching machine; immersing the target silicon wafer in a mixed solution of KOH and TMAH for etching; and removing the etched surface impurities, sequentially performing centrifugal washing and vacuum drying, and then pouring molten glass on the surface of the silicon wafer to protect the silicon wafer. The high doped silicon column array is processed by wet etching, so that the processing time is greatly reduced compared with that of dry etching, and the wet etching has the advantages of simplicity in operation and low cost, and can effectively reduce the processing difficulty and the production cost; meanwhile, the vertical silicon micro-column array with high depth is obtained, and a new thought method is provided for high-density device connection. The anisotropic etching of the silicon wafer in the KOH solution causes the side surface (111) not to be corroded basically, thereby obtaining a smooth and complete silicon micron column, providing more stable and reliable connection for subsequent device connection, and being beneficial to improving the reliability and long-term stability of the device.
Drawings
The present invention will be described in detail with reference to the accompanying drawings. The foregoing and other aspects of the invention will become more apparent and more readily appreciated from the following detailed description taken in conjunction with the accompanying drawings. In the accompanying drawings:
Fig. 1 is a flowchart of a method for manufacturing a device connection structure of a silicon pillar array according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of S1 provided by an embodiment of the present invention;
FIG. 3 is a schematic diagram of S2 provided by an embodiment of the present invention;
FIG. 4 is a top view of a silicon pillar array mask in accordance with the present invention;
fig. 5 is a schematic diagram of S4 provided in an embodiment of the present invention.
In the figure: 101. a silicon wafer; 201. pre-etching the opening; 301. a mask layer; 401. an array of silicon pillars.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1 to 5, an embodiment of the present invention provides a method for manufacturing a device connection structure of a silicon pillar array, the method including the following steps:
s1, preparing a silicon wafer: and (5) performing primary cleaning and drying on the silicon wafer.
Preferably, the S1 specifically includes: the target silicon wafer (110) is rinsed with deionized water and then vacuum dried.
S2, etching crystal orientation searching: and observing the target etching crystal orientation through preliminary pre-etching of the center of the silicon wafer.
S3, mask preparation: and preparing a SiO 2 mask on the surface of the silicon wafer through thermal oxidation, and preparing a directional etching glue layer pattern by using a photoetching machine.
S4, alkaline wet etching: and soaking the target silicon wafer in a mixed solution of KOH and TMAH for etching.
Among them, TMAH, which is called tetramethyl ammonium hydroxide (Tetramethylammonium hydroxide) as a common organic amine salt basic compound, is widely used in the fields of semiconductors, optics, chemistry, etc., and is used herein as an etchant for silicon wafers.
S5, preparing a glass protective layer: and removing the etched surface impurities, sequentially performing centrifugal washing and vacuum drying, and then pouring molten glass on the surface of the silicon wafer to protect the silicon wafer.
Specifically, the silicon wafer is primarily cleaned and dried; observing the target etching crystal orientation through preliminary pre-etching of the center of the silicon wafer; preparing a SiO 2 mask on the surface of the silicon wafer through thermal oxidation, and preparing a directional etching glue layer pattern by using a photoetching machine; immersing the target silicon wafer in a mixed solution of KOH and TMAH for etching; and removing the etched surface impurities, sequentially performing centrifugal washing and vacuum drying, and then pouring molten glass on the surface of the silicon wafer to protect the silicon wafer. The high doped silicon column array is processed by wet etching, so that the processing time is greatly reduced compared with that of dry etching, and the wet etching has the advantages of simplicity in operation and low cost, and can effectively reduce the processing difficulty and the production cost; the anisotropic etching of the silicon wafer in the KOH solution causes the side surface (111) not to be corroded basically, thereby obtaining a smooth and complete silicon micron column, providing more stable and reliable connection for subsequent device connection, and being beneficial to improving the reliability and long-term stability of the device. A mask pattern of a target silicon micron column is designed through a photoetching machine, a silicon wafer is soaked in a mixed solution of KOH and TMAH, and etching liquid is continuously etched vertically to the (1 1 0) surface without being corroded to the side surface by utilizing the difference of etching rates of silicon in different crystal directions, so that a high-depth vertical silicon column is obtained, and a novel processing method is provided for high-density device connection so as to meet the increasingly functional requirements and the size requirements.
In this embodiment, the step S2 specifically includes the following steps:
S21, uniformly spin-coating a 5um adhesive layer on the surface of the silicon wafer, and then drying and curing the adhesive layer;
S22, placing the silicon wafer of the S21 under a photoetching machine for alignment, and obtaining a square pre-etching opening at the center of the silicon wafer after exposure, development, washing and drying;
S23, soaking the silicon wafer in the mixed etching liquid of KOH and TMAH for 10min, taking out, washing and drying.
S24, placing the silicon wafer of S23 under a field emission scanning electron microscope to observe etching surface conditions, recording a positioning angle theta, and marking a target crystal orientation.
Preferably, in S22, the square pre-etched opening pattern obtained after the photolithography has a size of 1×1cm.
Preferably, in S23, after 10min in the mixed etching solution, the method further includes the following steps:
and placing the dried silicon wafer under a microscope to observe the etching surface, finding out a crystal plane vertical to the surface, marking the crystal orientation, and measuring out the angle of the target positioning angle theta.
Preferably, in S23, the mass ratio is as follows:
in the mixed etching solution, the KOH content is 30wt%, the TMAH content is 1wt%, the drying temperature is 50-90 ℃ and the drying time is 1-2 h.
Specifically, the target etching crystal orientation is observed through preliminary pre-etching at the center of the silicon wafer. And spin-coating a thin and uniform adhesive layer on the surface of the cleaned and dried silicon wafer, baking and curing the adhesive layer on the surface for a period of time, placing the silicon wafer under a photoetching machine to expose a square area aligned to the center by 1x1cm, dissolving uncured photoresist by using a developing solution, removing part of the photoresist in the exposed area, and finally performing necessary drying and cleaning to obtain the pre-etched silicon wafer with the center Kong Jiaoceng removed. Then soaking the silicon wafer in a mixed solution of KOH and TMAH for pre-etching for 10 minutes, removing redundant glue layers and impurities on the surface by using an organic solvent, and then taking out, cleaning and drying. And placing the dried silicon wafer under a microscope to observe the condition of an etching surface, finding a (111) crystal face vertical to the surface, marking the crystal orientation, and measuring the angle of the target positioning angle theta.
In this embodiment, the step S3 specifically includes the following steps:
s31, placing the silicon wafer marked with the crystal orientation in an ultrafast high-temperature furnace for oxidization;
s32, spin-coating a 5um adhesive layer on the surface of the silicon wafer in the S31, and then drying and curing the adhesive layer;
S33, placing the silicon wafer in the S32 under a photoetching machine to align with the positioning mark line, and obtaining a mask pattern designed in advance after exposure, development, washing and drying;
s34, removing redundant SiO 2 outside the mask area through the BOE solution.
Preferably, in S31, the oxidation temperature is 1100 ℃, and the heating time is 2min.
Specifically, a silicon wafer with a marked crystal orientation is placed in a high-temperature furnace, oxygen is introduced to carry out high-temperature oxidation, a layer of SiO 2 protective film is obtained on the surface of the silicon wafer, after the silicon wafer is cooled to room temperature, a 5um thick adhesive layer is uniformly spin-coated on a target silicon wafer, after the surface adhesive layer is dried and solidified for a period of time, the silicon wafer is placed under a photoetching machine to align with the marked crystal orientation, a diamond-shaped area which is designed in advance and distributed around a circular ring is exposed, then an uncured photoresist is dissolved by using a developing solution, part of the photoresist in the exposed area is removed, and finally, a (111) crystal orientation adhesive layer mask perpendicular to the surface (110) is obtained after necessary drying and cleaning. And finally removing the redundant SiO 2 outside the mask area by using a BOE solution. Thus, the mask pattern preparation is completed.
In this embodiment, the step S4 specifically includes the following steps:
etching a vertical silicon column array on the surface by using etching liquid, immersing the target silicon wafer after the double-layer mask is prepared in an etching tank of KOH and TMAH solution, controlling the temperature to be constant at 85 ℃, continuously using ultrasonic stirring and the etching liquid circulation to ensure the uniformity of etching in each place, and fishing out and cleaning after the etching time is up;
wherein the etching time is 20min, and the ambient temperature is 27 ℃.
Specifically, a vertical silicon column array is etched on the surface by using etching liquid, a target silicon wafer after double-layer mask preparation is soaked in an etching tank of KOH and TMAH solution, the temperature is controlled to be constant at 85 ℃, ultrasonic stirring and etching liquid circulation are continuously used for guaranteeing the uniformity of etching in each place, and the target silicon wafer is fished out and cleaned after the etching time is up.
In this embodiment, in the step S5, the rotational speed of the centrifugal washing is 500-800 rpm, and the washing time is 30-40 min;
The drying temperature of the vacuum drying is 60-80 ℃ and the drying time is 3-4 h.
Specifically, surface impurities are removed, and a glass protective layer is prepared. And removing the residual adhesive layer and SiO2 on the surface of the silicon wafer by using an organic solvent and hydrofluoric acid, cleaning by using deionized water, and sequentially performing centrifugal washing and vacuum drying to finally obtain the diamond-shaped silicon micron columns distributed around the ring on the silicon wafer. And then pouring molten glass on the surface to protect the silicon wafer, and thinning the two end faces to expose the surface silicon layer, so that the device connection is directly carried out by using the highly doped silicon micron column.
The silicon wafer is a wafer with (1, 0) surface doped with N type, the geometric dimension is 4 inches, the thickness is 500um, and the resistivity is 5-10Ω & cm.
In this embodiment, the specific manufacturing process is as follows:
Performing preliminary cleaning and drying treatment on the silicon wafer 101 to obtain a clean impurity-free silicon wafer 101; preliminary pre-etching is performed on the center of the silicon wafer 101 to observe a target etching crystal direction, a pre-etching opening 201 is formed, an SiO 2 mask is prepared on the surface of the silicon wafer 101 through thermal oxidation, a plurality of mask layers 301 of a directional etching glue layer pattern are prepared through a photoetching machine, and the mask layers 301 are a plurality of diamond patterns distributed annularly around the periphery of the silicon wafer 101; the etched silicon pillar array 401 is obtained by performing an alkaline wet etching method on the surface of the silicon wafer outside the area of the mask layer 301.
The embodiment of the invention also provides a device connecting structure of the silicon column array, which is prepared by the method for manufacturing the device connecting structure of the silicon column array.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, article or apparatus that comprises the element.
While the embodiments of the present invention have been illustrated and described in connection with the drawings, what is presently considered to be the most practical and preferred embodiments of the invention, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, is intended to cover various equivalent modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (8)
1. A method of manufacturing a device connection structure for an array of silicon pillars, the method comprising the steps of:
S1, preparing a silicon wafer: performing preliminary cleaning and drying on the silicon wafer;
s2, etching crystal orientation searching: observing a target etching crystal orientation through preliminary pre-etching of the center of the silicon wafer;
the step S2 specifically comprises the following steps:
S21, uniformly spin-coating a 5um adhesive layer on the surface of the silicon wafer, and then drying and curing the adhesive layer;
S22, placing the silicon wafer of the S21 under a photoetching machine for alignment, and obtaining a square pre-etching opening at the center of the silicon wafer after exposure, development, washing and drying;
S23, soaking the silicon wafer in the mixed etching liquid of KOH and TMAH for 10min, taking out, washing and drying;
s24, placing the silicon wafer of the S23 under a field emission scanning electron microscope to observe etching surface conditions, recording a positioning angle theta, and marking a target crystal orientation;
S3, mask preparation: preparing a SiO 2 mask on the surface of the silicon wafer through thermal oxidation, and preparing a directional etching glue layer pattern by using a photoetching machine;
Placing the silicon wafer with the marked crystal orientation in a high-temperature furnace, introducing oxygen for high-temperature oxidation, obtaining a layer of SiO 2 um protective film on the surface of the silicon wafer, uniformly spin-coating a 5um thick adhesive layer on a target silicon wafer after cooling to room temperature, placing the silicon wafer under a photoetching machine after drying and curing the surface adhesive layer for a period of time, aligning the marked crystal orientation, exposing a diamond-shaped area which is designed in advance and distributed around a ring, dissolving uncured photoresist by using a developing solution, removing part of the photoresist in the exposed area, and finally drying and cleaning to obtain a crystal orientation adhesive layer mask perpendicular to the surface orientation; removing redundant SiO 2 outside the mask area by using a BOE solution, and completing the preparation of the mask pattern;
S4, alkaline wet etching: soaking the target silicon wafer in a mixed solution of KOH and TMAH for etching;
s5, preparing a glass protective layer: and removing the etched surface impurities, sequentially performing centrifugal washing and vacuum drying, and then pouring molten glass on the surface of the silicon wafer to protect the silicon wafer.
2. The method for manufacturing a device connection structure of a silicon pillar array according to claim 1, wherein S1 specifically includes: and cleaning the silicon wafer by using deionized water, and then carrying out vacuum drying treatment.
3. The method for manufacturing a device connection structure of a silicon pillar array according to claim 1, wherein in S22, a square pre-etched opening pattern size obtained after photolithography is 1 x 1cm.
4. The method for manufacturing a device connection structure of a silicon pillar array according to claim 1, wherein in S23, after 10 minutes in the mixed etching solution, the method further comprises the steps of:
and placing the dried silicon wafer under a microscope to observe the etching surface, finding out a crystal plane vertical to the surface, marking the crystal orientation, and measuring out the angle of the target positioning angle theta.
5. The method for manufacturing a device connection structure of a silicon pillar array according to claim 1, wherein in S23, the mass ratio is as follows:
in the mixed etching solution, the KOH content is 30wt%, the TMAH content is 1wt%, the drying temperature is 50-90 ℃ and the drying time is 1-2 h.
6. The method of manufacturing a device connection structure for a silicon pillar array according to claim 1, wherein in S3, the oxidation temperature is 1100 ℃ and the heating time is 2min.
7. The method for manufacturing a device connection structure of a silicon pillar array according to claim 1, wherein S4 specifically includes the steps of:
etching a vertical silicon column array on the surface by using etching liquid, immersing the target silicon wafer after the double-layer mask is prepared in an etching tank of KOH and TMAH solution, controlling the temperature to be constant at 85 ℃, continuously using ultrasonic stirring and the etching liquid circulation to ensure the uniformity of etching in each place, and fishing out and cleaning after the etching time is up;
wherein the etching time is 20min, and the ambient temperature is 27 ℃.
8. A device connection structure, characterized in that the device connection structure is manufactured by the manufacturing method of the device connection structure of the silicon pillar array according to any one of claims 1 to 7.
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