CN117672841A - Manufacturing method and device connection structure of device connection structure of silicon pillar array - Google Patents

Abstract

The invention provides a manufacturing method of a device connection structure of a silicon column array and the device connection structure, wherein the manufacturing method comprises the following steps: s1, preparing a silicon wafer: performing preliminary cleaning and drying on the silicon wafer; s2, etching crystal orientation searching: observing the target etching crystal orientation through preliminary pre-etching of the center of the silicon wafer; s3, mask preparation: siO is prepared on the surface of the silicon wafer through thermal oxidation ₂ Masking and preparing a directional etching glue layer pattern by using a photoetching machine; s4, alkaline wet etching: immersing the target silicon wafer in a mixed solution of KOH and TMAH for etching; s5, preparing a glass protective layer: and removing the etched surface impurities, sequentially performing centrifugal washing and vacuum drying, and then pouring molten glass on the surface of the silicon wafer to protect the silicon wafer. The manufacturing method of the device connection structure of the silicon column array has the advantages of high manufacturing efficiency, good quality, high reliability and low production cost.

Description

Manufacturing method and device connection structure of device connection structure of silicon pillar array

Technical field

The invention relates to the technical field of chip device interconnection, and in particular to a manufacturing method and device connection structure of a silicon pillar array device connection structure.

Background technique

In the field of modern science and technology, the innovation of intra-chip interconnect materials and processes has become one of the most critical technical difficulties in the current high-end chip research and development. The design and manufacturing process methods of device connections are the key to achieving efficient, reliable and precise electronic device functions. There are mainly four types of existing chip interconnection technologies in packaging processes.

1. Wire bonding: It connects the metal leads on the chip to the metal pins on the packaging substrate by using metal wires with good electrical conductivity (such as aluminum wires or gold wires). 2. Flip-chip bonding: In flip-chip technology, the bare chip and the substrate are no longer connected through wiring. Instead, the chip is flipped and installed upside down on the packaging substrate, and the connection is directly realized through metal solder balls. 3. Hybrid bonding: First, through-holes are formed through deep reactive ion etching or physical drilling, and copper is filled using electroplating. The surface is then planarized by chemical mechanical polishing, and then plasma is used to activate the surface to prepare for pre-bonding. After the upper and lower wafers are aligned, pre-bonding is completed, and the annealing operation is performed to further promote the diffusion of the copper through-hole bonding surface, thereby completing a good electrical connection. 4. Through silicon via (TSV) bonding: TSV does not use traditional wiring methods to connect chips to chips. Instead, it connects chips vertically by drilling holes on the chip and filling it with conductive materials such as metal to accommodate electrodes. After making a wafer with TSVs, micro-bumps are formed on the top and bottom of it by packaging, and then these bumps are connected.

However, the above-mentioned wire bonding still has some shortcomings in high-density packaging and miniaturized devices. Due to the limited line width, wire bonding cannot meet higher interconnection density requirements. At the same time, due to its long electrical path, it is not suitable for newer equipment that requires high-speed operation. Flip-chip bonding requires strict process control and fine alignment operations to ensure bonding quality and reliability; at the same time, it is difficult to stack multiple chips, which is detrimental to storage products that require high density. Hybrid bonding is the focus of subsequent research and development due to its higher integration density and ability to simultaneously achieve electrical connection and physical support. However, this method is complex, time-consuming, and has high production costs. Through-silicon via (TSV) bonding The through-silicon vias obtained through physical means have the disadvantage of low precision and low depth.

Contents of the invention

The invention provides a method for manufacturing a device connection structure of a silicon pillar array, aiming to solve the problems of low preparation efficiency, poor reliability, long time consumption, high production cost and poor quality of existing chip device connections.

An embodiment of the present invention provides a method for manufacturing a device connection structure of a silicon pillar array. The manufacturing method includes the following steps:

S1. Silicon wafer preparation: preliminary cleaning and drying of silicon wafers;

S2. Finding the etching crystal direction: observe the target etching crystal direction through preliminary pre-etching at the center of the silicon wafer;

S3. Mask preparation: prepare a SiO ₂ mask on the surface of the silicon wafer through thermal oxidation, and then use a photolithography machine to prepare a directional etching glue layer pattern;

S4. Alkaline wet etching: soak the target silicon wafer in a mixture of KOH and TMAH for etching;

S5. Prepare a glass protective layer: remove etched surface impurities and perform centrifugal washing and vacuum drying in sequence, and then pour molten glass on the surface to protect the silicon wafer.

Preferably, S1 specifically includes: cleaning the target silicon wafer (110) with deionized water, and then performing a vacuum drying process.

Preferably, the S2 specifically includes the following steps:

S21. Spin-coat a layer of 5um glue layer evenly on the surface of the silicon wafer, and then dry and solidify the glue layer;

S22. Place the silicon wafer of S21 under the photolithography machine and align it. After exposure, development, rinsing, and drying, a square pre-etched hole is obtained in the center of the silicon wafer;

S23. Soak the silicon wafer of S22 in the mixed etching solution of KOH and TMAH for 10 minutes, then take it out and wash and dry it;

S24. Place the silicon wafer of S23 under a field emission scanning electron microscope to observe the etching surface, record the positioning angle θ, and mark the target crystal direction.

Preferably, in S22, the size of the square pre-etched hole pattern obtained after photolithography is 1×1 cm.

Preferably, in S23, after 10 minutes in the mixed etching solution, the following steps are also included:

Place the dried silicon wafer under a microscope to observe the etching surface, find the crystal plane perpendicular to the surface and mark the crystal direction, and measure the target positioning angle θ.

Preferably, in the S23, according to the mass ratio:

In the mixed etching solution, the content of KOH is 30wt%, the content of TMAH is 1wt%, the drying temperature is 50°C to 90°C, and the drying time is 1 to 2 hours.

Preferably, the S3 specifically includes the following steps:

S31. Place the silicon wafer with the crystal orientation marked in an ultra-fast high-temperature furnace for oxidation;

S32. Spin-coat a 5um glue layer on the surface of the silicon wafer in S31, and then dry and solidify the glue layer;

S33. Place the silicon wafer in S32 under the photolithography machine and align it with the positioning mark line, and obtain the pre-designed mask pattern after exposure, development, rinse, and drying;

S34. Use BOE solution to remove excess SiO ₂ outside the mask area.

Preferably, in the S31, the oxidation temperature is 1100°C and the heating time is 2 minutes.

Preferably, the S4 specifically includes the following steps:

Use the etching solution to carve a vertical silicon pillar array on the surface. Soak the target silicon wafer after preparing the double-layer mask in the etching tank of KOH and TMAH solutions. Control the temperature at a constant 85°C and constantly use ultrasonic stirring and The etching solution is circulated to ensure the uniformity of etching in each place. After the etching time is up, take it out and clean it;

Among them, the etching time is 20 minutes, and the ambient temperature is 27°C.

In a second aspect, embodiments of the present invention provide a device connection structure, which is manufactured by the above-mentioned method for manufacturing a device connection structure of a silicon pillar array.

Compared with the existing technology, the beneficial effects of the present invention include: preliminary cleaning and drying of the silicon wafer; observing the target etching crystal direction through preliminary pre-etching of the center of the silicon wafer; and performing thermal oxidation on the silicon wafer. Prepare a SiO ₂ mask on the surface of the wafer, and then use a photolithography machine to prepare a directional etching glue layer pattern; immerse the target silicon wafer in a mixture of KOH and TMAH for etching; remove the etched surface Impurities are removed by centrifugal washing and vacuum drying in sequence, and then molten glass is poured on the surface to protect the silicon wafer. In this way, the highly doped silicon pillar array is processed by wet etching, which greatly reduces the processing time compared with dry etching, and wet etching has the advantages of simple operation and low cost, and can effectively Reduce processing difficulty and production cost; at the same time, this can obtain a high-depth vertical silicon micron pillar array, providing new ideas and methods for high-density device connection. The anisotropic etching of the silicon wafer in the KOH solution makes the side (111) basically not corroded, thereby obtaining smooth and complete silicon micron pillars, which provides a more stable and reliable connection for subsequent device connections, helping to improve the device performance. reliability and long-term stability.

Description of drawings

The present invention will be described in detail below with reference to the accompanying drawings. The above or other aspects of the present invention will become clearer and easier to understand by the following detailed description in conjunction with the accompanying drawings. In the attached picture:

Figure 1 is a flow chart of a method for manufacturing a device connection structure of a silicon pillar array provided by an embodiment of the present invention;

Figure 2 is a schematic diagram of S1 provided by an embodiment of the present invention;

Figure 3 is a schematic diagram of S2 provided by an embodiment of the present invention;

Figure 4 is a top view of the silicon pillar array mask in the present invention;

Figure 5 is a schematic diagram of S4 provided by the embodiment of the present invention.

In the picture: 101, silicon wafer; 201, pre-etched opening; 301, mask layer; 401, silicon pillar array.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention and are not intended to limit the present invention.

As shown in FIGS. 1 to 5 , embodiments of the present invention provide a method for manufacturing a device connection structure of a silicon pillar array. The manufacturing method includes the following steps:

S1. Silicon wafer preparation: preliminary cleaning and drying of the silicon wafer.

Preferably, the S1 specifically includes: cleaning the target silicon wafer (110) with deionized water, and then performing a vacuum drying process.

S2. Etching crystal direction search: Observe the target etching crystal direction through preliminary pre-etching in the center of the silicon wafer.

S3. Mask preparation: prepare a SiO ₂ mask on the surface of the silicon wafer through thermal oxidation, and then use a photolithography machine to prepare a directional etching glue layer pattern.

S4. Alkaline wet etching: soak the target silicon wafer in a mixture of KOH and TMAH for etching.

Among them, TMAH, the full name is Tetramethylammonium hydroxide, is a common organic amine salt alkaline compound, which is widely used in semiconductor, optics, chemistry and other fields. In this article, it is used as an engraving material for silicon wafers. Corrosion agent.

S5. Prepare a glass protective layer: remove etched surface impurities and perform centrifugal washing and vacuum drying in sequence, and then pour molten glass on the surface to protect the silicon wafer.

Specifically, the silicon wafer is initially cleaned and dried; the target etching direction is observed through preliminary pre-etching of the center of the silicon wafer; and a SiO ₂ mask is prepared on the surface of the silicon wafer through thermal oxidation. , then use a photolithography machine to prepare a directional etching glue layer pattern; soak the target silicon wafer in a mixture of KOH and TMAH for etching; remove the etched surface impurities and perform centrifugal washing and vacuum drying in sequence, and then Molten glass is poured onto its surface to protect the silicon wafer. In this way, the highly doped silicon pillar array is processed by wet etching, which greatly reduces the processing time compared with dry etching, and wet etching has the advantages of simple operation and low cost, and can effectively Reduce processing difficulty and production cost; the anisotropic etching of the silicon wafer in the KOH solution makes the side (111) basically not corroded, thereby obtaining smooth and complete silicon micron pillars, providing a more stable and reliable connection for subsequent device connections. , helping to improve device reliability and long-term stability. Use a photolithography machine to design the mask pattern of the target silicon micron pillars, soak the silicon wafer in a mixed solution of KOH and TMAH, and use the difference in etching rates of silicon in different crystal directions to make the etching solution continuously move toward (1 1 0) The surface is vertically etched without basically etching to the side, thereby obtaining high-depth vertical silicon pillars, which provides a new processing method for high-density device connection to meet the growing functional needs and size requirements.

In this embodiment, the S2 specifically includes the following steps:

S21. Spin-coat a layer of 5um glue layer evenly on the surface of the silicon wafer, and then dry and solidify the glue layer;

S22. Place the silicon wafer of S21 under the photolithography machine and align it. After exposure, development, rinsing, and drying, a square pre-etched hole is obtained in the center of the silicon wafer;

S23. Soak the silicon wafer of S22 in the mixed etching solution of KOH and TMAH for 10 minutes, then take it out, wash and dry it.

S24. Place the silicon wafer of S23 under a field emission scanning electron microscope to observe the etching surface, record the positioning angle θ, and mark the target crystal direction.

Preferably, in S22, the size of the square pre-etched hole pattern obtained after photolithography is 1×1 cm.

Preferably, in S23, after 10 minutes in the mixed etching solution, the following steps are also included:

Place the dried silicon wafer under a microscope to observe the etching surface, find the crystal plane perpendicular to the surface and mark the crystal direction, and measure the target positioning angle θ.

Preferably, in the S23, according to the mass ratio:

In the mixed etching solution, the content of KOH is 30wt%, the content of TMAH is 1wt%, the drying temperature is 50°C to 90°C, and the drying time is 1 to 2 hours.

Specifically, the target etching crystal direction is observed through preliminary pre-etching in the center of the silicon wafer. Spin-coat a thin and uniform adhesive layer on the surface of the cleaned and dried silicon wafer. After drying and solidifying the surface adhesive layer for a period of time, place the silicon wafer under the photolithography machine and align it with a square area of 1x1cm in the center. Expose, then use a developer to dissolve the uncured photoresist, and remove part of the photoresist in the exposed area. Finally, after necessary drying and cleaning, the pre-etched silicon wafer with the center hole glue layer removed is obtained. Then, the silicon wafer is immersed in a mixed solution of KOH and TMAH for 10 minutes to pre-etch. Then, an organic solvent is used to remove excess glue layer and impurities on the surface, and then it is taken out for cleaning and drying. Place the dried silicon wafer under a microscope to observe the etching surface, find the (111) crystal plane perpendicular to the surface and mark the crystal direction, and measure the target positioning angle θ.

In this embodiment, the S3 specifically includes the following steps:

S31. Place the silicon wafer with the crystal orientation marked in an ultra-fast high-temperature furnace for oxidation;

S32. Spin-coat a 5um glue layer on the surface of the silicon wafer in S31, and then dry and solidify the glue layer;

S33. Place the silicon wafer in S32 under the photolithography machine and align it with the positioning mark line, and obtain the pre-designed mask pattern after exposure, development, rinse, and drying;

S34. Use BOE solution to remove excess SiO ₂ outside the mask area.

Preferably, in the S31, the oxidation temperature is 1100°C and the heating time is 2 minutes.

Specifically, by placing the silicon wafer with the crystal orientation marked in a high-temperature furnace, introducing oxygen for high-temperature oxidation, a 5um SiO ₂ protective film is obtained on the surface of the silicon wafer, and after cooling to room temperature, it is formed on the target silicon wafer. Evenly spin-coat a 5um thick adhesive layer. After drying and solidifying the surface adhesive layer for a period of time, place the silicon wafer under the photolithography machine and align it with the marked crystal orientation. The diamond-shaped area is exposed, and then a developer is used to dissolve the uncured photoresist, and part of the photoresist in the exposed area is removed. Finally, after necessary drying and cleaning, (111) perpendicular to the surface (110) is obtained. Crystal orientation glue layer mask. Finally, use BOE solution to remove excess SiO ₂ outside the mask area. At this point, the mask pattern preparation is completed.

In this embodiment, the S4 specifically includes the following steps:

Use the etching solution to carve a vertical silicon pillar array on the surface. Soak the target silicon wafer after preparing the double-layer mask in the etching tank of KOH and TMAH solutions. Control the temperature at a constant 85°C and constantly use ultrasonic stirring and The etching solution is circulated to ensure the uniformity of etching in each place. After the etching time is up, take it out and clean it;

Among them, the etching time is 20 minutes, and the ambient temperature is 27°C.

Specifically, an etching solution is used to carve a vertical silicon pillar array on the surface, and the target silicon wafer after preparing the double-layer mask is immersed in an etching tank of KOH and TMAH solutions. The temperature is controlled to be constant at 85°C, and the target silicon wafer is continuously used. Ultrasonic stirring and etching solution circulation are used to ensure the uniformity of etching in each place. After the etching time is up, take it out and clean it.

In this embodiment, in the S5, the rotation speed of the centrifugal washing is 500-800 rpm, and the washing time is 30-40 minutes;

The drying temperature of the vacuum drying is 60-80°C, and the drying time is 3-4 hours.

Specifically, surface impurities are removed and a glass protective layer is prepared. Use organic solvents and hydrofluoric acid to remove the remaining glue layer and SiO2 on the surface of the silicon wafer. After cleaning with deionized water, centrifuge washing and vacuum drying are performed in sequence. Finally, the target rhombic silicon micron pillars distributed around the ring are obtained on the silicon wafer. Molten glass is then poured on the surface to protect the silicon wafer, and both end surfaces are thinned to expose the surface silicon layer. Highly doped silicon micron pillars are used to directly connect devices.

Wherein, the silicon wafer is a (1 1 0) plane N-type doped wafer, with a geometric size of 4 inches, a thickness of 500um, and a resistivity of 5-10Ω·cm.

In this embodiment, the specific manufacturing process is as follows:

By performing a preliminary cleaning and drying process on the silicon wafer 101, a clean and impurity-free silicon wafer 101 is obtained; the center of the silicon wafer 101 is preliminarily pre-etched to observe the target etching crystal direction and form a pre-etching opening. 201. Prepare a SiO ₂ mask on the surface of the silicon wafer 101 through thermal oxidation, and then use a photolithography machine to prepare multiple mask layers 301 of directional etching glue layer patterns. The mask layers 301 are wrapped around the silicon wafer. A plurality of diamond patterns are distributed annularly around the wafer 101; the etched silicon pillar array 401 is obtained by performing an alkaline wet etching method on the surface of the silicon wafer outside the mask layer 301 area.

An embodiment of the present invention also provides a device connection structure of a silicon pillar array, which is manufactured by the above-mentioned method for manufacturing a device connection structure of a silicon pillar array.

It should be noted that, as used herein, the terms "comprises," "comprises," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, article, or device that includes a list of elements not only includes those elements, but also Includes other elements not expressly listed or elements inherent to the process, article or apparatus. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in the process, article, or apparatus that includes the element.

The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementations. The above-mentioned specific implementations are only illustrative. It is not intended to be limiting. Under the inspiration of the present invention, those of ordinary skill in the art can also make many forms and equivalent changes without departing from the spirit of the present invention and the scope protected by the claims, which all belong to the present invention. Within protection.

Claims (10)

1. A method of manufacturing a device connection structure for an array of silicon pillars, the method comprising the steps of:

s1, preparing a silicon wafer: performing preliminary cleaning and drying on the silicon wafer;

s2, etching crystal orientation searching: observing the target etching crystal orientation through preliminary pre-etching of the center of the silicon wafer;

s3, mask preparation: siO is prepared on the surface of the silicon wafer through thermal oxidation ₂ Masking and preparing a directional etching glue layer pattern by using a photoetching machine;

s4, alkaline wet etching: immersing the target silicon wafer in a mixed solution of KOH and TMAH for etching;

s5, preparing a glass protective layer: and removing the etched surface impurities, sequentially performing centrifugal washing and vacuum drying, and then pouring molten glass on the surface of the silicon wafer to protect the silicon wafer.

2. The method for manufacturing a device connection structure of a silicon pillar array according to claim 1, wherein S1 specifically includes: the target silicon wafer (110) is rinsed with deionized water and then vacuum dried.

3. The method for manufacturing a device connection structure of a silicon pillar array according to claim 1, wherein S2 specifically comprises the steps of:

s21, uniformly spin-coating a 5um adhesive layer on the surface of the silicon wafer, and then drying and curing the adhesive layer;

s22, placing the silicon wafer of the S21 under a photoetching machine for alignment, and obtaining a square pre-etching opening at the center of the silicon wafer after exposure, development, washing and drying;

s23, soaking the silicon wafer in the mixed etching liquid of KOH and TMAH for 10min, taking out, washing and drying;

s24, placing the silicon wafer of S23 under a field emission scanning electron microscope to observe etching surface conditions, recording a positioning angle theta, and marking a target crystal orientation.

4. The method for fabricating a device connection structure for a silicon pillar array according to claim 3, wherein in S22, the size of the square pre-etched opening pattern obtained after the photolithography is 1x 1cm.

5. The method for manufacturing a device connection structure of a silicon pillar array according to claim 3, wherein in S23, after 10 minutes in the mixed etching solution, the method further comprises the steps of:

and placing the dried silicon wafer under a microscope to observe the etching surface, finding out a crystal plane vertical to the surface, marking the crystal orientation, and measuring out the angle of the target positioning angle theta.

6. The method for manufacturing a device connection structure of a silicon pillar array according to claim 3, wherein in S23, the mass ratio is as follows:

in the mixed etching solution, the KOH content is 30wt%, the TMAH content is 1wt%, the drying temperature is 50-90 ℃ and the drying time is 1-2 h.

7. The method for manufacturing a device connection structure of a silicon pillar array according to claim 1, wherein S3 specifically comprises the steps of:

s31, placing the silicon wafer marked with the crystal orientation in an ultrafast high-temperature furnace for oxidization;

s32, spin-coating a 5um adhesive layer on the surface of the silicon wafer in the S31, and then drying and curing the adhesive layer;

s33, placing the silicon wafer in the S32 under a photoetching machine to align with the positioning mark line, and obtaining a mask pattern designed in advance after exposure, development, washing and drying;

s34, removing redundant SiO outside the mask area through BOE solution ₂ 。

8. The method of manufacturing a device connection structure for a silicon pillar array according to claim 7, wherein in S31, the oxidation temperature is 1100 ℃ and the heating time is 2min.

9. The method for manufacturing a device connection structure of a silicon pillar array according to claim 1, wherein S4 specifically includes the steps of:

etching a vertical silicon column array on the surface by using etching liquid, immersing the target silicon wafer after the double-layer mask is prepared in an etching tank of KOH and TMAH solution, controlling the temperature to be constant at 85 ℃, continuously using ultrasonic stirring and the etching liquid circulation to ensure the uniformity of etching in each place, and fishing out and cleaning after the etching time is up;

wherein the etching time is 20min, and the ambient temperature is 27 ℃.

10. A device connection structure characterized in that it is manufactured by the manufacturing method of the device connection structure of the silicon pillar array according to any one of claims 1 to 9.