CN114927479A - Preparation method of semiconductor structure and semiconductor structure - Google Patents

Abstract

The embodiment of the disclosure discloses a preparation method of a semiconductor structure and the semiconductor structure, wherein the preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a laminated structure formed by sequentially laminating a sacrificial layer and a supporting layer on the substrate; the laminated structure comprises a first sacrificial layer close to one side of the substrate, and the material of the first sacrificial layer comprises high-density material.

Description

A kind of preparation method of semiconductor structure and semiconductor structure

technical field

The present disclosure relates to the field of integrated circuit manufacturing, and in particular, to a method for preparing a semiconductor structure and a semiconductor structure.

Background technique

In recent years, the semiconductor industry has developed rapidly. In terms of technology, we are increasingly pursuing nano-devices. The feature size in chip production continues to shrink. The entire technology continues to develop in the direction of further miniaturization of key dimensions, and the spacing between electronic devices is getting smaller and smaller. The smaller it is, the greater the challenge to the proper functioning of each electronic device. Ensuring that tiny electronic devices function properly and maintain a high density distribution is one of the decisive factors in the success or failure of the process. Therefore, eliminating or reducing the problem of high aspect ratio pattern deformation plays an extremely important role in the production of DRAM, in which lithography resolution and pattern conversion times are important elements that affect the high aspect ratio pattern deformation. First of all, the smaller the size of the lithography technology, the smaller the wavelength of the light source is, because the diffraction and interference between the light rays will cause the phenomenon of overexposure or underexposure, resulting in the failure of the target pattern, while the extreme ultraviolet rays with small wavelengths require High technical cost; and multiple pattern conversions will increase the risk of foreign matter entering the pattern or pattern damage, resulting in the adhesion or loss of the final pattern, thereby affecting the product yield. Therefore, there is an urgent need to develop a more safe and effective processing technology that prevents deformation of high aspect ratio patterns.

SUMMARY OF THE INVENTION

In view of this, embodiments of the present disclosure provide a method for fabricating a semiconductor structure and a semiconductor structure.

According to a first aspect of the embodiments of the present disclosure, a method for fabricating a semiconductor structure is provided, including:

provide a substrate;

A stacked structure formed by stacking a sacrificial layer and a supporting layer in sequence is formed on the substrate; the stacked structure includes a first sacrificial layer on the side close to the substrate, and the material of the first sacrificial layer includes high dense material.

In some embodiments, the high density material is polysilicon.

In some embodiments, it also includes:

forming a first mask layer, a first buffer layer, a second mask layer and a second buffer layer stacked in sequence on the stacked structure;

patterning the second buffer layer and the second mask layer to form a first pattern;

forming a first mask pattern on the sidewall of the first pattern, the first mask pattern extending along a first direction;

removing the second buffer layer and the second mask layer;

A third mask layer, a third buffer layer, a fourth mask layer and a fourth buffer layer are formed on the first buffer layer in sequence; the third mask layer covers the first buffer layer, and filling the gaps between the first mask patterns;

patterning the fourth buffer layer and the fourth mask layer to form a second pattern;

A second mask pattern is formed on the sidewall of the second pattern, the second mask pattern extends along a second direction, and the second direction is oblique to the first direction;

The fourth buffer layer and the fourth mask layer are removed.

In some embodiments, the first mask pattern and the second mask pattern are arranged crosswise to form holes arranged in an array; the size of the holes along the first direction and the size along the second direction The range is 30nm to 40nm.

In some embodiments, it also includes:

Before forming the sequentially stacked first mask layer, first buffer layer, second mask layer and second buffer layer, a target mask layer is formed on the stacked structure, and the first mask layer is located on the on the target mask layer;

After removing the fourth buffer layer and the fourth mask layer, the method further includes:

removing the exposed third buffer layer and the third mask layer based on the second mask pattern;

patterning the first mask layer and the first buffer layer based on the first mask pattern and the second mask pattern;

removing the first mask pattern, the second mask pattern, the remaining third buffer layer and the remaining third mask layer;

The target mask layer is patterned based on the patterned first mask layer and the first buffer layer.

In some embodiments, it also includes:

etching the stacked structure based on the patterned target mask layer to form a first through hole;

A third sacrificial layer is formed on the sidewall of the first through hole.

In some embodiments, the material of the third sacrificial layer includes silicon oxide.

In some embodiments, it also includes:

After the third sacrificial layer is formed, an electrode layer is formed on the sidewall of the third sacrificial layer and the bottom surface of the first through hole.

In some embodiments, the laminated structure further includes a first support layer, a second sacrificial layer and a second support layer stacked in sequence on the first sacrificial layer;

After forming the electrode layer, the method further includes: removing part of the second support layer to form the first opening;

Based on the first opening, the second sacrificial layer and a part of the third sacrificial layer between the first support layer and the second support layer are removed, and the remaining second support layer and the electrode are retained A third sacrificial layer between layers.

In some embodiments, the material of the first sacrificial layer and the material of the second sacrificial layer have high etch selectivity ratios.

In some embodiments, it also includes:

after removing the second sacrificial layer and a portion of the third sacrificial layer between the first support layer and the second support layer, removing a portion of the first support layer to form a second opening;

Based on the second opening, the first sacrificial layer is removed.

In some embodiments, the first sacrificial layer is removed by etching with an alkaline solution.

In some embodiments, it also includes:

After the first sacrificial layer is removed, the remaining third sacrificial layer is partially removed, and the remaining third sacrificial layer between the first support layer and the electrode layer remains.

In some embodiments, the second sacrificial layer and part of the third sacrificial layer are removed using a mixed solution of HF and NH ₄ F, or a mixed gas of HF and NH ₃ .

According to a second aspect of the embodiments of the present disclosure, there is provided a semiconductor structure, comprising:

substrate;

a first support layer on the substrate, and a second support layer on the first support layer;

a capacitor hole, penetrating the first support layer and the second support layer;

an electrode layer covering the sidewall and bottom surface of the capacitor hole;

A third sacrificial layer is located between one side of the first support layer and the second support layer and the electrode layer.

In the embodiment of the present disclosure, the material of the first sacrificial layer located in the lower layer in the stacked structure is set to be a high-density material, so that the stacked structure has better performance. On the one hand, the structure above the first sacrificial layer is etched For example, when the second sacrificial layer or supporting layer is used, because the first sacrificial layer is a high-density material, it has a high etching selectivity ratio with the second sacrificial layer or supporting layer, so that even if the etching solution or gas is etched to the first At the sacrificial layer, it can also effectively prevent the etching solution or gas from damaging the first sacrificial layer, so as not to etch through the first sacrificial layer. collapse.

Description of drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the accompanying drawings required in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some implementations of the present disclosure. For example, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

FIG. 1 is a schematic flowchart of a method for fabricating a semiconductor structure provided by an embodiment of the present disclosure;

2a to 2w are schematic structural diagrams of a semiconductor structure provided in an embodiment of the present disclosure during a fabrication process;

FIG. 3 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

Description of reference numbers:

10-substrate; 11-word line; 12-capacitor contact plug;

20-laminated structure; 21-first sacrificial layer; 22-first supporting layer; 23-second sacrificial layer; 24-second supporting layer; 25-third sacrificial layer; 201-first through hole; 250- The third sacrificial layer pre-layer; 251—the first part of the third sacrificial layer; 252—the second part of the third sacrificial layer;

30 - the third support layer;

40-target mask layer; 41-first target mask layer; 42-second target mask layer; 401-first patterned target mask layer; 402-second patterned target mask layer; 410-th A target mask layer opening; 420—a second target mask layer opening;

51-first mask layer; 52-first buffer layer; 53-second mask layer; 54-second buffer layer; 55-third mask layer; 56-third buffer layer; 57-fourth mask film layer; 58-fourth buffer layer; 501-first pattern; 502-second pattern; 503-third pattern; 510-first mask pattern; 520-second mask pattern; 530-hole;

61-first photoresist layer; 62-second photoresist layer;

70-electrode layer; 700-electrode layer pre-layer; 701-capacitance hole;

801-first opening; 802-second opening.

Detailed ways

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be more thoroughly understood, and will fully convey the scope of the present disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, some technical features that are well known in the art have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual embodiment are described herein, and well-known functions and constructions are not described in detail.

In the drawings, the sizes of layers, regions, elements, and their relative sizes may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on the other elements or layers , adjacent thereto, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. The discussion of a second element, component, region, layer or section does not imply that the first element, component, region, layer or section is necessarily present in the present disclosure.

Spatial relational terms such as "under", "below", "under", "under", "above", "above", etc., are used herein for convenience Description is used to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description in order to explain the technical solutions of the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure is capable of other embodiments in addition to these detailed descriptions.

In chip production, the feature size is constantly shrinking, and the patterning process is becoming more and more complex. More films need to be stacked. The etching selection ratio between different films is used to achieve the purpose of pattern conversion to achieve smaller size.

In some embodiments, there is a method of removing the silicon oxide between SiCNs with HF solution, but possibly due to the different crystal orientation characteristics of the deposited titanium nitride, the HF solution will penetrate the titanium nitride and etch to the underlying silicon oxide, When etching the support layer SiCN, it may be etched through the silicon oxide or even to the silicon nitride at the bottom, and even cause pattern collapse.

Based on this, an embodiment of the present disclosure provides a method for preparing a semiconductor structure. Please refer to FIG. 1 for details. As shown in the figure, the method includes the following steps:

Step 101: providing a substrate;

Step 102 : forming a stacked structure formed by sequentially stacking a sacrificial layer and a supporting layer on the substrate; the stacked structure includes a first sacrificial layer on the side close to the substrate, and the first sacrificial layer is Materials include high density materials.

The method for fabricating the semiconductor structure provided by the embodiments of the present disclosure will be further described in detail below with reference to specific embodiments.

2a to 2w are schematic structural diagrams of the semiconductor structure provided in the embodiment of the present disclosure during the fabrication process. It should be explained that the structures below the target mask layer are not shown in FIGS. 2d to 2o.

First, referring to FIG. 2a , step 101 is performed to provide a substrate 10 .

The substrate 10 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a SOI (Silicon On Insulator, Silicon On Insulator) substrate or a GOI (Germanium On Insulator, Germanium On Insulator) substrate etc., it can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V group compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), or a laminated structure , such as Si/SiGe, etc., and other epitaxial structures, such as SGOI (silicon germanium on insulator) and the like.

In one embodiment, continuing to refer to FIG. 2 a , word lines 11 and capacitive contact plugs 12 are formed in the substrate 10 , and the capacitive contact plugs 12 are electrically connected to the electrode layers formed subsequently. It should be explained that, in addition to word lines and capacitive contact plugs, other device structures are also formed in the substrate, which are not shown in the embodiments of the present disclosure.

Next, referring to FIG. 2 b , step 102 is performed to form a stacked structure 20 formed by sequentially stacking a sacrificial layer and a support layer on the substrate 10 ; A sacrificial layer 21, the material of the first sacrificial layer 21 includes high-density materials, which can make the laminated structure have better performance. On the one hand, the structure above the first sacrificial layer, such as the second sacrificial layer, is etched or supporting layer, because the first sacrificial layer is a high-density material, it has a high etching selectivity ratio with the second sacrificial layer or supporting layer, so even if the etching solution or gas is etched to the first sacrificial layer, it can be The first sacrificial layer is effectively prevented from being damaged by the etching solution or gas, and the first sacrificial layer is not etched through.

In one embodiment, the high density material is polysilicon. It should be explained that the material of the first sacrificial layer can also be other high-density materials.

The stacked structure 20 further includes a first supporting layer 22 , a second sacrificial layer 23 and a second supporting layer 24 which are stacked on the first sacrificial layer 21 in sequence.

Materials of the first support layer 22 and the second support layer 24 include but are not limited to SiCN, and materials of the second sacrificial layer 23 include but are not limited to borophosphosilicate glass (BPSG).

Continuing to refer to FIG. 2 b , a third support layer 30 is formed on the stacked structure 20 . The material of the third support layer 30 includes but is not limited to SiCN.

In actual operation, the first sacrificial layer 21 , the first supporting layer 22 , the second sacrificial layer 23 , the second supporting layer 24 and the third supporting layer 30 can use one or more thin films A deposition process is formed; specifically, the deposition process includes, but is not limited to, a chemical vapor deposition (CVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, or a combination thereof.

Next, referring to FIGS. 2 c to 2 l , the method further includes: forming a first mask layer 51 , a first buffer layer 52 , a second mask layer 53 and a second buffer layer in sequence on the stacked structure 20 layer 54;

patterning the second buffer layer 54 and the second mask layer 53 to form a first pattern 501;

A first mask pattern 510 is formed on the sidewall of the first pattern 501, and the first mask pattern 510 extends along a first direction;

removing the second buffer layer 54 and the second mask layer 53;

A third mask layer 55 , a third buffer layer 56 , a fourth mask layer 57 and a fourth buffer layer 58 are formed on the first buffer layer 52 in sequence; the third mask layer 55 covers the the first buffer layer 52, and fills the gaps between the first mask patterns 510;

patterning the fourth buffer layer 58 and the fourth mask layer 57 to form a second pattern 502;

A second mask pattern 520 is formed on the sidewall of the second pattern 502, the second mask pattern 520 extends along a second direction, and the second direction is oblique to the first direction;

The fourth buffer layer 58 and the fourth mask layer 57 are removed.

Specifically, referring to FIG. 2 c first, a first mask layer 51 , a first buffer layer 52 , a second mask layer 53 and a second buffer layer 54 are formed on the stacked structure 20 in sequence.

In actual operation, the first mask layer 51 , the first buffer layer 52 , the second mask layer 53 and the second buffer layer 54 can be formed using one or more thin film deposition processes; specifically, the deposition processes include But not limited to chemical vapor deposition (CVD) processes, plasma enhanced chemical vapor deposition (PECVD) processes, atomic layer deposition (ALD) processes, or combinations thereof.

In one embodiment, continuing to refer to FIG. 2 c , before forming the first mask layer 51 , the first buffer layer 52 , the second mask layer 53 and the second buffer layer 54 which are stacked in sequence, in the stacked structure 20 A target mask layer 40 is formed thereon, and the first mask layer 51 is located on the target mask layer 40 . Specifically, a target mask layer 40 is formed on the third support layer 30 .

In actual operation, the target mask layer 40 may be formed using one or more thin film deposition processes; specifically, the deposition processes include but are not limited to chemical vapor deposition (CVD) processes, plasma-enhanced chemical vapor deposition ( PECVD) process, atomic layer deposition (ALD) process, or a combination thereof.

Continuing to refer to FIG. 2 c , the method further includes: forming a first photoresist layer 61 on the second buffer layer 54 .

In practice, the first photoresist layer 61 can be formed using one or more thin film deposition processes; specifically, the deposition processes include but are not limited to chemical vapor deposition (CVD) processes, plasma-enhanced chemical vapor deposition processes Deposition (PECVD) process, Atomic Layer Deposition (ALD) process, or a combination thereof.

Next, referring to FIGS. 2 d to 2 e , the second buffer layer 54 and the second mask layer 53 are patterned to form a first pattern 501 .

Specifically, referring to FIG. 2 d first, the first photoresist layer 61 is patterned to display the first pattern to be etched on the first photoresist layer 61 .

Next, referring to FIG. 2 e , according to the patterned first photoresist layer, the second buffer layer 54 and the second mask layer 53 are patterned to form a first pattern 501 . And after the first pattern 501 is formed, the first photoresist layer 61 is removed.

Next, referring to FIG. 2f, a first mask pattern 510 is formed on the sidewall of the first pattern 501, and the first mask pattern 510 extends along a first direction.

Specifically, a first mask pattern pre-layer (not shown in the figure) may be formed first, the first mask pattern pre-layer covers the sidewalls and the top of the one pattern 501 , and the cover is exposed by the first pattern 501 the surface of the first buffer layer 52 .

Next, referring to FIG. 2f, the part of the first mask pattern pre-layer located on the top of the first pattern 501 and the surface of the first buffer layer 52 is removed, and the part located on the sidewall of the first pattern 501 is retained to form a first Mask pattern 510 .

Next, referring to FIG. 2g , the second buffer layer 54 and the second mask layer 53 are removed, and only the first mask pattern 510 remains. (2) of FIG. 2g is a top view of the first mask pattern. As shown in (2) of FIG. 2g, the first mask pattern 510 is elongated and extends in the first direction.

Next, referring to FIG. 2h, a third mask layer 55, a third buffer layer 56, a fourth mask layer 57 and a fourth buffer layer 58 are formed on the first buffer layer 52 in sequence; the third mask layer The film layer 55 covers the first buffer layer 52 and fills the gaps between the first mask patterns 510 .

In actual operation, the third mask layer 55 , the third buffer layer 56 , the fourth mask layer 57 and the fourth buffer layer 58 may be formed using one or more thin film deposition processes; specifically, the deposition processes include But not limited to chemical vapor deposition (CVD) processes, plasma enhanced chemical vapor deposition (PECVD) processes, atomic layer deposition (ALD) processes, or combinations thereof.

Continuing to refer to FIG. 2h , the method further includes: forming a second photoresist layer 62 on the fourth buffer layer 58 .

In practice, the second photoresist layer 62 can be formed using one or more thin film deposition processes; specifically, the deposition processes include but are not limited to chemical vapor deposition (CVD) processes, plasma-enhanced chemical vapor deposition processes Deposition (PECVD) process, Atomic Layer Deposition (ALD) process, or a combination thereof.

Next, referring to FIGS. 2i and 2j , the fourth buffer layer 58 and the fourth mask layer 57 are patterned to form a second pattern 502 .

Specifically, referring to FIG. 2 i first, the second photoresist layer 62 is patterned to display the second pattern to be etched on the second photoresist layer 62 .

Next, referring to FIG. 2j , according to the patterned second photoresist layer, the fourth buffer layer 58 and the fourth mask layer 57 are patterned to form a second pattern 502 . And after the second pattern 502 is formed, the second photoresist layer 62 is removed.

Next, referring to FIG. 2k, a second mask pattern 520 is formed on the sidewall of the second pattern 502, and the second mask pattern 520 extends along a second direction, and the second direction is oblique to the first direction pay.

Specifically, a second mask pattern pre-layer (not shown in the figure) may be formed first, the second mask pattern pre-layer covers the sidewalls and the top of the two patterns 502 , and the cover is exposed by the second pattern 502 the surface of the third buffer layer 56 .

Next, referring to FIG. 2k , the part of the second mask pattern pre-layer located on the top of the second pattern 502 and the surface of the third buffer layer 56 is removed, and the part located on the sidewall of the second pattern 502 is retained to form the second pattern 502 . Mask pattern 520 .

Next, referring to FIG. 21 , the fourth buffer layer 58 and the fourth mask layer 57 are removed, and only the second mask pattern 520 remains. Figure (2) in FIG. 21 is a top view of the first mask pattern and the second mask pattern. As shown in Figure (2) in FIG. 21 , the second mask pattern 520 is in the shape of a long strip and extends along the A second direction extends, and the second direction is oblique to the first direction.

In one embodiment, the included angle between the first direction and the second direction ranges from 55° to 65°. Specifically, the angle between the first direction and the second direction may be 55°, 60°, 65°, and so on.

In one embodiment, the first mask pattern and the second mask pattern may be formed by etching using an ArF-WET lithography technology with a minimum feature size of 38 nm, but is not limited to this lithography technology.

In one embodiment, as shown in (2) of FIG. 21 , the first mask pattern 510 and the second mask pattern 520 are arranged in a cross manner to form holes 530 arranged in an array; The size of the hole 530 along the first direction and the size of the hole 530 along the second direction range from 30 nm to 40 nm.

In the manufacturing process of the original semiconductor structure, the widths of the first mask pattern and the second mask pattern are 20 nm˜30 nm, but in the embodiment of the present disclosure, the first mask pattern is reduced and the width of the second mask pattern become 10nm-15nm, therefore, the size of the hole along the first direction and the size along the second direction change from 15nm-25nm to 30nm-40nm in the embodiment of the present disclosure . The size of the hole is increased by reducing the widths of the first mask pattern and the second mask pattern.

In some embodiments, the designed device pattern is formed by two indirect self-aligned double patterning (SADP) technology, but if the by-products after etching enter into the etch-back pattern or destroy the etch-back Etching the pattern can easily cause some short-circuit problems for the subsequent capacitor device molding. The reduction of the feature size also increases the difficulty of foreign matter processing, and the multiple pattern conversions increase this risk. Therefore, in the embodiment of the present disclosure, the size of the feature is increased by increasing the size of the hole, thereby reducing the problem of short circuiting of the capacitor device.

In one embodiment, the first mask layer 51 , the second mask layer 53 , the third mask layer 55 and the fourth mask layer 57 in the above-mentioned embodiment may include, but are not limited to, a spin-on mask layer (SOH). , Spin-on Hard mask). The spin-on mask layer may include an amorphous carbon layer or an amorphous silicon layer. The first buffer layer 52, the second buffer layer 54, the third buffer layer 56 and the fourth buffer layer 58 may include, but are not limited to, a silicon nitride layer or an oxide layer, and the oxide layer may include an oxide layer formed of ethyl orthosilicate. silicon layer. Materials of the first mask pattern 510 and the second mask pattern 520 may include, but are not limited to, oxide materials.

Next, referring to FIGS. 2m to 2o , after removing the fourth buffer layer 58 and the fourth mask layer 57 , the method further includes: removing the exposed portion of the buffer layer 520 based on the second mask pattern 520 . the third buffer layer 56 and the third mask layer 55;

Based on the first mask pattern 510 and the second mask pattern 520, pattern the first mask layer 51 and the first buffer layer 52 to form a third pattern 503;

removing the first mask pattern 510, the second mask pattern 520, the remaining third buffer layer 56 and the remaining third mask layer 55;

Based on the patterned first mask layer 51 and the first buffer layer 52 , the target mask layer 40 is patterned.

Specifically, the exposed third buffer layer 56 and the third mask layer 55 are first etched using the second mask pattern 520 as a mask, and during this process, the first mask will not be removed Pattern 510. Then, based on the first mask pattern 510 , the second mask pattern 520 , the remaining third buffer layer 56 and the remaining third mask layer 55 as masks, the first mask layer is etched. mask layer 51 and the first buffer layer 52 . Then, the first mask pattern 510 , the second mask pattern 520 , the remaining third buffer layer 56 and the remaining third mask layer 55 are removed. Then, using the remaining first mask layer 51 and the first buffer layer 52 as masks, the target mask layer 40 is etched to pattern the target mask layer 40 .

Referring to FIG. 2m , the target mask layer 40 includes a first target mask layer 41 and a second target mask layer 42 . In one embodiment, the first target mask layer 41 includes, but is not limited to, a polysilicon layer, and the second target mask layer 42 includes, but is not limited to, an oxide layer. For example, the second target mask layer 42 includes a silicon oxide layer formed of ethyl orthosilicate.

In one embodiment, the patterning of the target mask layer 40 based on the patterned first mask layer 51 and the first buffer layer 52 includes:

patterning the second target mask layer 42 based on the patterned first mask layer 51 and the first buffer layer 52 to obtain a second patterned target mask layer 402;

removing the patterned first mask layer 51 and the first buffer layer 52;

patterning the first target mask layer 41 based on the second patterned target mask layer 402 to obtain a first patterned target mask layer 401;

The second patterned target mask layer 402 is removed.

Specifically, referring to FIG. 2m and FIG. 2n first, the second target mask layer 42 is etched using the patterned first mask layer 51 and the first buffer layer 52 as masks to obtain a second pattern A target mask layer 402 is formed. Referring to (2) in FIG. 2n, the second patterned target mask layer 402 is formed with second target mask layer openings 420 of uniform size and uniform distribution, and the second target mask layer openings 420 may be in an array Arrange. For example, a plurality of circular or elliptical openings arranged in an array may be formed in the second patterned target mask layer 402 , and each opening has the same width along the same direction. Then, the patterned first mask layer 51 and the first buffer layer 52 are removed. Then, referring to FIG. 2o, using the second patterned target mask layer 402 as a mask, the first target mask layer 41 is etched to obtain the first patterned target mask layer 401; and the second patterned target mask layer is removed Membrane layer 402 . Referring to (2) in FIG. 2o, the first patterned target mask layer 401 is formed with first target mask layer openings 410 with uniform size and uniform distribution, and the first target mask layer openings 410 may be in an array Arrange. For example, a plurality of circular or elliptical openings arranged in an array may be formed in the first patterned target mask layer 401 , and each opening has the same width along the same direction.

Next, referring to FIGS. 2p to 2r , the method for preparing the semiconductor structure further includes: etching the stacked structure 20 based on the patterned target mask layer 40 to form a first through hole 201 ; A third sacrificial layer 25 is formed on the sidewall of the first through hole 201 .

Specifically, referring to FIG. 2p , based on the patterned target mask layer 40 , the stacked structure 20 is etched to form a first through hole 201 . More specifically, in the process of etching the stacked structure 20 , the third support layer 30 is etched at the same time, so that the first through holes 201 penetrate through the third support layer 30 and the stacked structure 20 . Here, the diameter of the first through hole should not be too large, in order to prevent the thickness of the third sacrificial layer used as compensation from being too thick. After the third sacrificial layer is removed by etching, the thickness of the remaining supporting layer is not enough, resulting in the formation of patterns. of collapse.

Next, referring to FIG. 2 q , a third sacrificial layer pre-layer 250 is formed on the sidewall and bottom surface of the first through hole 201 and the surface of the third support layer 30 .

Next, referring to FIG. 2r , the bottom surface of the first through hole 201 and the third sacrificial layer pre-layer 250 on the surface of the third support layer 30 are etched and removed, so as to form the first through hole 201 on the sidewall of the first through hole 201 . Three sacrificial layers 25 .

In one embodiment, the material of the third sacrificial layer 25 includes silicon oxide.

The third sacrificial layer 25 may be formed by a low temperature silicon oxide chemical vapor deposition process.

The thickness of the third sacrificial layer 25 may be determined by the difference between the diameter of the first through hole 201 and the diameter of the electrode hole used to form the electrode layer subsequently. Here, the third sacrificial layer is used to compensate the enlarged aperture of the first through hole, and with the protection of the third sacrificial layer at the sidewall, the semiconductor can be better protected in the subsequent process of etching and removing the first sacrificial layer The topography of the structure prevents the device from collapsing.

Next, referring to FIGS. 2s to 2t , the method for preparing the semiconductor structure further includes: after forming the third sacrificial layer 25 , forming on the sidewall of the third sacrificial layer 25 and the bottom surface of the first through hole 201 electrode layer 70 .

Specifically, referring to FIG. 2 s first, an electrode layer pre-layer 700 is formed on the sidewall of the third sacrificial layer 25 , the bottom surface of the first through hole 201 , and the surface of the third support layer 30 .

Next, referring to FIG. 2t , the electrode layer pre-layer 700 on the surface of the third support layer 30 is etched and removed to form an electrode layer 70 on the sidewall of the third sacrificial layer 25 and the bottom surface of the first through hole 201 .

The material of the electrode layer 70 includes, but is not limited to, titanium nitride.

Next, referring to FIG. 2u , after the electrode layer 70 is formed, the method further includes: removing part of the second support layer 24 to form a first opening 801 ;

Based on the first opening 801 , the second sacrificial layer 23 and part of the third sacrificial layer 25 between the first support layer 22 and the second support layer 24 are removed, and the remaining second support is retained A third sacrificial layer between layer 24 and the electrode layer 70 .

In one embodiment, specifically, the second sacrificial layer 23 and part of the third sacrificial layer 25 may be removed by using a mixed solution of HF and NH ₄ F, or a mixed gas of HF and NH ₃ .

Specifically, when part of the second support layer 24 is removed, part of the third support layer 30 and part of the electrode layer 70 are removed at the same time. The rest of the second support layer 24 and the rest of the third support layer 30 and the third sacrificial layer remaining between the electrode layer 70 is the first portion 251 of the third sacrificial layer.

Next, referring to FIG. 2v, after removing the second sacrificial layer 23 and part of the third sacrificial layer 25 between the first support layer 22 and the second support layer 24, remove part of the first support layer 22, to form a second opening 802 ; based on the second opening 802 , the first sacrificial layer 21 is removed.

Specifically, the first sacrificial layer 21 may be removed by etching with an alkaline solution. The alkaline solution includes, but is not limited to, TMAH, NaOH, KOH or NH4OH.

In one embodiment, the material of the first sacrificial layer 21 and the material of the second sacrificial layer 23 have a high etching selectivity ratio.

Next, referring to FIG. 2w, the method further includes: after removing the first sacrificial layer 21, partially removing the remaining third sacrificial layer 25, leaving the remaining first support layer 22 and the electrode layer The third sacrificial layer between 70.

In actual operation, a mixed solution of HF and NH ₄ F or a mixed gas of HF and NH ₃ may be used to remove part of the third sacrificial layer.

The remaining third sacrificial layer remaining between the first support layer 22 and the electrode layer 70 is the second portion 252 of the third sacrificial layer.

The first part and the second part of the third sacrificial layer can be used as support layers to ensure the stability of the semiconductor structure.

The embodiment of the present disclosure further provides a semiconductor structure, and FIG. 3 is a schematic structural diagram of the semiconductor structure provided by the embodiment of the present disclosure.

As shown in FIG. 3 , the semiconductor structure includes: a substrate 10 ; a first support layer 22 located on the substrate 10 , and a second support layer 24 located on the first support layer 22 ; capacitor holes 701, penetrating through the first support layer 22 and the second support layer 24; an electrode layer 70, covering the sidewall and bottom surface of the capacitor hole 701; a third sacrificial layer 25, located on the first support layer 22 and the bottom surface of the capacitor hole 701; between one side of the second support layer 24 and the electrode layer 70 .

The substrate 10 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a SOI (Silicon On Insulator, Silicon On Insulator) substrate or a GOI (Germanium On Insulator, Germanium On Insulator) substrate etc., it can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V group compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), or a laminated structure , such as Si/SiGe, etc., and other epitaxial structures, such as SGOI (silicon germanium on insulator) and the like.

In one embodiment, word lines 11 and capacitive contact plugs 12 are formed in the substrate 10 , and the capacitive contact plugs 12 are electrically connected to the electrode layer 70 . It should be explained that, in addition to word lines and capacitive contact plugs, other device structures are also formed in the substrate, which are not shown in the embodiments of the present disclosure.

In one embodiment, the semiconductor structure further includes: a third support layer 30 located on the second support layer 24 .

In one embodiment, the third sacrificial layer further includes a portion between the third support layer 30 and the electrode layer 70 .

The part of the third sacrificial layer located between the second support layer 24 and the third support layer 30 and the electrode layer 70 is the first part 251 of the third sacrificial layer, and the third sacrificial layer is located at the first part 251 of the third sacrificial layer. The portion between the first support layer 22 and the electrode layer 70 is the second portion 252 of the third sacrificial layer. The first part and the second part of the third sacrificial layer can be used as support layers to ensure the stability of the semiconductor structure.

In one embodiment, the materials of the first support layer 22 , the second support layer 24 and the third support layer 30 include but are not limited to SiCN. The material of the third sacrificial layer 25 includes silicon oxide. The material of the electrode layer 70 includes, but is not limited to, titanium nitride.

The above are only preferred embodiments of the present disclosure, and are not intended to limit the protection scope of the present disclosure. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present disclosure shall be included in the within the scope of the present disclosure.

Claims (15)

1. A method for fabricating a semiconductor structure, comprising:

providing a substrate;

forming a laminated structure formed by sequentially laminating a sacrificial layer and a supporting layer on the substrate; the laminated structure comprises a first sacrificial layer close to one side of the substrate, and the material of the first sacrificial layer comprises high-density material.

2. The method of claim 1,

the high-density material is polycrystalline silicon.

3. The method of claim 1, further comprising:

forming a first mask layer, a first buffer layer, a second mask layer and a second buffer layer which are sequentially stacked on the stacked structure;

patterning the second buffer layer and the second mask layer to form a first pattern;

forming a first mask pattern on sidewalls of the first pattern, the first mask pattern extending in a first direction;

removing the second buffer layer and the second mask layer;

forming a third mask layer, a third buffer layer, a fourth mask layer and a fourth buffer layer which are sequentially stacked on the first buffer layer; the third mask layer covers the first buffer layer and fills gaps among the first mask patterns;

patterning the fourth buffer layer and the fourth mask layer to form a second pattern;

forming a second mask pattern on sidewalls of the second pattern, the second mask pattern extending in a second direction, the second direction being oblique to the first direction;

and removing the fourth buffer layer and the fourth mask layer.

4. The method of claim 3,

the first mask patterns and the second mask patterns are arranged in a crossed mode to form holes arranged in an array mode; the size of the hole along the first direction and the size of the hole along the second direction are in a range of 30nm to 40 nm.

5. The method of claim 3, further comprising:

before a first mask layer, a first buffer layer, a second mask layer and a second buffer layer which are sequentially stacked are formed, a target mask layer is formed on the stacked structure, and the first mask layer is located on the target mask layer;

after removing the fourth buffer layer and the fourth mask layer, the method further includes:

removing the exposed third buffer layer and the exposed third mask layer based on the second mask pattern;

patterning the first mask layer and the first buffer layer based on the first mask pattern and the second mask pattern;

removing the first mask pattern, the second mask pattern, the reserved third buffer layer and the reserved third mask layer;

and patterning the target mask layer based on the patterned first mask layer and the patterned first buffer layer.

6. The method of claim 5, further comprising:

etching the laminated structure based on the patterned target mask layer to form a first through hole;

and forming a third sacrificial layer on the side wall of the first through hole.

7. The method of claim 6,

the material of the third sacrificial layer comprises silicon oxide.

8. The method of claim 6, further comprising:

after the third sacrificial layer is formed, an electrode layer is formed on the side wall of the third sacrificial layer and the bottom surface of the first through hole.

9. The method of claim 8,

the laminated structure also comprises a first supporting layer, a second sacrificial layer and a second supporting layer which are sequentially laminated on the first sacrificial layer;

after forming the electrode layer, the method further comprises: removing part of the second support layer to form a first opening;

based on the first opening, removing the second sacrificial layer and a part of the third sacrificial layer between the first support layer and the second support layer, and remaining the third sacrificial layer between the second support layer and the electrode layer.

10. The method of claim 9,

the material of the first sacrificial layer and the material of the second sacrificial layer have a high etching selectivity ratio.

11. The method of claim 9, further comprising:

after removing the second sacrificial layer and part of the third sacrificial layer between the first support layer and the second support layer, removing part of the first support layer to form a second opening;

removing the first sacrificial layer based on the second opening.

12. The method of claim 11,

and etching and removing the first sacrificial layer by using an alkaline solution.

13. The method of claim 11, further comprising:

after the first sacrificial layer is removed, partially removing the remaining third sacrificial layer, and remaining the third sacrificial layer between the first support layer and the electrode layer.

14. The method of claim 13,

using HF and NH ₄ F mixed solution, or HF and NH ₃ And removing the second sacrificial layer and part of the third sacrificial layer by using mixed gas.

15. A semiconductor structure, comprising:

a substrate;

a first support layer on the substrate, and a second support layer on the first support layer;

a capacitor hole penetrating through the first support layer and the second support layer;

an electrode layer covering the sidewall and the bottom surface of the capacitor hole;

and the third sacrificial layer is positioned between one side of the first support layer and one side of the second support layer and the electrode layer.

Images